Lines Matching defs:rps
35 static struct igp_ps *rs780_get_ps(struct radeon_ps *rps)
37 struct igp_ps *ps = rps->ps_priv;
719 struct radeon_ps *rps,
723 rps->caps = le32_to_cpu(non_clock_info->ulCapsAndSettings);
724 rps->class = le16_to_cpu(non_clock_info->usClassification);
725 rps->class2 = le16_to_cpu(non_clock_info->usClassification2);
728 rps->vclk = le32_to_cpu(non_clock_info->ulVCLK);
729 rps->dclk = le32_to_cpu(non_clock_info->ulDCLK);
731 rps->vclk = 0;
732 rps->dclk = 0;
735 if (r600_is_uvd_state(rps->class, rps->class2)) {
736 if ((rps->vclk == 0) || (rps->dclk == 0)) {
737 rps->vclk = RS780_DEFAULT_VCLK_FREQ;
738 rps->dclk = RS780_DEFAULT_DCLK_FREQ;
742 if (rps->class & ATOM_PPLIB_CLASSIFICATION_BOOT)
743 rdev->pm.dpm.boot_ps = rps;
744 if (rps->class & ATOM_PPLIB_CLASSIFICATION_UVDSTATE)
745 rdev->pm.dpm.uvd_ps = rps;
749 struct radeon_ps *rps,
752 struct igp_ps *ps = rs780_get_ps(rps);
782 if (rps->class & ATOM_PPLIB_CLASSIFICATION_BOOT) {
940 struct radeon_ps *rps)
942 struct igp_ps *ps = rs780_get_ps(rps);
944 r600_dpm_print_class_info(rps->class, rps->class2);
945 r600_dpm_print_cap_info(rps->caps);
946 printk("\tuvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk);
951 r600_dpm_print_ps_status(rdev, rps);
985 struct radeon_ps *rps = rdev->pm.dpm.current_ps;
986 struct igp_ps *ps = rs780_get_ps(rps);
995 seq_printf(m, "uvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk);
1032 struct radeon_ps *rps = rdev->pm.dpm.current_ps;
1033 struct igp_ps *ps = rs780_get_ps(rps);
1071 rs780_enable_voltage_scaling(rdev, rps);