Lines Matching defs:rdev
52 static void rs600_gpu_init(struct radeon_device *rdev);
53 int rs600_mc_wait_for_idle(struct radeon_device *rdev);
61 static bool avivo_is_in_vblank(struct radeon_device *rdev, int crtc)
69 static bool avivo_is_counter_moving(struct radeon_device *rdev, int crtc)
85 * @rdev: radeon_device pointer
90 void avivo_wait_for_vblank(struct radeon_device *rdev, int crtc)
94 if (crtc >= rdev->num_crtc)
103 while (avivo_is_in_vblank(rdev, crtc)) {
105 if (!avivo_is_counter_moving(rdev, crtc))
110 while (!avivo_is_in_vblank(rdev, crtc)) {
112 if (!avivo_is_counter_moving(rdev, crtc))
118 void rs600_page_flip(struct radeon_device *rdev, int crtc_id, u64 crtc_base, bool async)
120 struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id];
137 for (i = 0; i < rdev->usec_timeout; i++) {
149 bool rs600_page_flip_pending(struct radeon_device *rdev, int crtc_id)
151 struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id];
161 struct radeon_device *rdev = dev->dev_private;
222 void rs600_pm_misc(struct radeon_device *rdev)
224 int requested_index = rdev->pm.requested_power_state_index;
225 struct radeon_power_state *ps = &rdev->pm.power_state[requested_index];
251 radeon_atom_set_voltage(rdev, voltage->vddc_id, SET_VOLTAGE_TYPE_ASIC_VDDC);
305 if ((rdev->flags & RADEON_IS_PCIE) &&
306 !(rdev->flags & RADEON_IS_IGP) &&
307 rdev->asic->pm.set_pcie_lanes &&
309 rdev->pm.power_state[rdev->pm.current_power_state_index].pcie_lanes)) {
310 radeon_set_pcie_lanes(rdev,
316 void rs600_pm_prepare(struct radeon_device *rdev)
318 struct drm_device *ddev = rdev->ddev;
334 void rs600_pm_finish(struct radeon_device *rdev)
336 struct drm_device *ddev = rdev->ddev;
353 bool rs600_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd)
375 void rs600_hpd_set_polarity(struct radeon_device *rdev,
379 bool connected = rs600_hpd_sense(rdev, hpd);
403 void rs600_hpd_init(struct radeon_device *rdev)
405 struct drm_device *dev = rdev->ddev;
425 radeon_hpd_set_polarity(rdev, radeon_connector->hpd.hpd);
427 radeon_irq_kms_enable_hpd(rdev, enable);
430 void rs600_hpd_fini(struct radeon_device *rdev)
432 struct drm_device *dev = rdev->ddev;
453 radeon_irq_kms_disable_hpd(rdev, disable);
456 int rs600_asic_reset(struct radeon_device *rdev, bool hard)
467 rv515_mc_stop(rdev, &save);
469 dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status);
477 pci_save_state(rdev->pdev);
479 pci_clear_master(rdev->pdev);
489 dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status);
497 dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status);
505 dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status);
507 pci_restore_state(rdev->pdev);
510 dev_err(rdev->dev, "failed to reset GPU\n");
513 dev_info(rdev->dev, "GPU reset succeed\n");
514 rv515_mc_resume(rdev, &save);
521 void rs600_gart_tlb_flush(struct radeon_device *rdev)
539 static int rs600_gart_init(struct radeon_device *rdev)
543 if (rdev->gart.robj) {
548 r = radeon_gart_init(rdev);
552 rdev->gart.table_size = rdev->gart.num_gpu_pages * 8;
553 return radeon_gart_table_vram_alloc(rdev);
556 static int rs600_gart_enable(struct radeon_device *rdev)
561 if (rdev->gart.robj == NULL) {
562 dev_err(rdev->dev, "No VRAM object for PCIE GART.\n");
565 r = radeon_gart_table_vram_pin(rdev);
598 rdev->gart.table_addr);
599 WREG32_MC(R_00013C_MC_PT0_CONTEXT0_FLAT_START_ADDR, rdev->mc.gtt_start);
600 WREG32_MC(R_00014C_MC_PT0_CONTEXT0_FLAT_END_ADDR, rdev->mc.gtt_end);
604 WREG32_MC(R_000112_MC_PT0_SYSTEM_APERTURE_LOW_ADDR, rdev->mc.vram_start);
605 WREG32_MC(R_000114_MC_PT0_SYSTEM_APERTURE_HIGH_ADDR, rdev->mc.vram_end);
612 rs600_gart_tlb_flush(rdev);
614 (unsigned)(rdev->mc.gtt_size >> 20),
615 (unsigned long long)rdev->gart.table_addr);
616 rdev->gart.ready = true;
620 static void rs600_gart_disable(struct radeon_device *rdev)
628 radeon_gart_table_vram_unpin(rdev);
631 static void rs600_gart_fini(struct radeon_device *rdev)
633 radeon_gart_fini(rdev);
634 rs600_gart_disable(rdev);
635 radeon_gart_table_vram_free(rdev);
653 void rs600_gart_set_page(struct radeon_device *rdev, unsigned i,
656 void __iomem *ptr = (void *)rdev->gart.ptr;
660 int rs600_irq_set(struct radeon_device *rdev)
669 if (ASIC_IS_DCE2(rdev))
675 if (!rdev->irq.installed) {
680 if (atomic_read(&rdev->irq.ring_int[RADEON_RING_TYPE_GFX_INDEX])) {
683 if (rdev->irq.crtc_vblank_int[0] ||
684 atomic_read(&rdev->irq.pflip[0])) {
687 if (rdev->irq.crtc_vblank_int[1] ||
688 atomic_read(&rdev->irq.pflip[1])) {
691 if (rdev->irq.hpd[0]) {
694 if (rdev->irq.hpd[1]) {
697 if (rdev->irq.afmt[0]) {
704 if (ASIC_IS_DCE2(rdev))
713 static inline u32 rs600_irq_ack(struct radeon_device *rdev)
720 rdev->irq.stat_regs.r500.disp_int = RREG32(R_007EDC_DISP_INTERRUPT_STATUS);
721 if (G_007EDC_LB_D1_VBLANK_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) {
725 if (G_007EDC_LB_D2_VBLANK_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) {
729 if (G_007EDC_DC_HOT_PLUG_DETECT1_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) {
734 if (G_007EDC_DC_HOT_PLUG_DETECT2_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) {
740 rdev->irq.stat_regs.r500.disp_int = 0;
743 if (ASIC_IS_DCE2(rdev)) {
744 rdev->irq.stat_regs.r500.hdmi0_status = RREG32(R_007404_HDMI0_STATUS) &
746 if (G_007404_HDMI0_AZ_FORMAT_WTRIG(rdev->irq.stat_regs.r500.hdmi0_status)) {
752 rdev->irq.stat_regs.r500.hdmi0_status = 0;
760 void rs600_irq_disable(struct radeon_device *rdev)
769 rs600_irq_ack(rdev);
772 int rs600_irq_process(struct radeon_device *rdev)
778 status = rs600_irq_ack(rdev);
780 !rdev->irq.stat_regs.r500.disp_int &&
781 !rdev->irq.stat_regs.r500.hdmi0_status) {
785 rdev->irq.stat_regs.r500.disp_int ||
786 rdev->irq.stat_regs.r500.hdmi0_status) {
789 radeon_fence_process(rdev, RADEON_RING_TYPE_GFX_INDEX);
792 if (G_007EDC_LB_D1_VBLANK_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) {
793 if (rdev->irq.crtc_vblank_int[0]) {
794 drm_handle_vblank(rdev->ddev, 0);
795 rdev->pm.vblank_sync = true;
796 wake_up(&rdev->irq.vblank_queue);
798 if (atomic_read(&rdev->irq.pflip[0]))
799 radeon_crtc_handle_vblank(rdev, 0);
801 if (G_007EDC_LB_D2_VBLANK_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) {
802 if (rdev->irq.crtc_vblank_int[1]) {
803 drm_handle_vblank(rdev->ddev, 1);
804 rdev->pm.vblank_sync = true;
805 wake_up(&rdev->irq.vblank_queue);
807 if (atomic_read(&rdev->irq.pflip[1]))
808 radeon_crtc_handle_vblank(rdev, 1);
810 if (G_007EDC_DC_HOT_PLUG_DETECT1_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) {
814 if (G_007EDC_DC_HOT_PLUG_DETECT2_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) {
818 if (G_007404_HDMI0_AZ_FORMAT_WTRIG(rdev->irq.stat_regs.r500.hdmi0_status)) {
822 status = rs600_irq_ack(rdev);
825 schedule_delayed_work(&rdev->hotplug_work, 0);
827 schedule_work(&rdev->audio_work);
828 if (rdev->msi_enabled) {
829 switch (rdev->family) {
845 u32 rs600_get_vblank_counter(struct radeon_device *rdev, int crtc)
853 int rs600_mc_wait_for_idle(struct radeon_device *rdev)
857 for (i = 0; i < rdev->usec_timeout; i++) {
865 static void rs600_gpu_init(struct radeon_device *rdev)
867 r420_pipes_init(rdev);
869 if (rs600_mc_wait_for_idle(rdev))
870 dev_warn(rdev->dev, "Wait MC idle timeout before updating MC.\n");
873 static void rs600_mc_init(struct radeon_device *rdev)
877 rdev->mc.aper_base = pci_resource_start(rdev->pdev, 0);
878 rdev->mc.aper_size = pci_resource_len(rdev->pdev, 0);
879 rdev->mc.vram_is_ddr = true;
880 rdev->mc.vram_width = 128;
881 rdev->mc.real_vram_size = RREG32(RADEON_CONFIG_MEMSIZE);
882 rdev->mc.mc_vram_size = rdev->mc.real_vram_size;
883 rdev->mc.visible_vram_size = rdev->mc.aper_size;
884 rdev->mc.igp_sideport_enabled = radeon_atombios_sideport_present(rdev);
887 radeon_vram_location(rdev, &rdev->mc, base);
888 rdev->mc.gtt_base_align = 0;
889 radeon_gtt_location(rdev, &rdev->mc);
890 radeon_update_bandwidth_info(rdev);
893 void rs600_bandwidth_update(struct radeon_device *rdev)
900 if (!rdev->mode_info.mode_config_initialized)
903 radeon_update_display_priority(rdev);
905 if (rdev->mode_info.crtcs[0]->base.enabled)
906 mode0 = &rdev->mode_info.crtcs[0]->base.mode;
907 if (rdev->mode_info.crtcs[1]->base.enabled)
908 mode1 = &rdev->mode_info.crtcs[1]->base.mode;
910 rs690_line_buffer_adjust(rdev, mode0, mode1);
912 if (rdev->disp_priority == 2) {
924 uint32_t rs600_mc_rreg(struct radeon_device *rdev, uint32_t reg)
929 spin_lock_irqsave(&rdev->mc_idx_lock, flags);
933 spin_unlock_irqrestore(&rdev->mc_idx_lock, flags);
937 void rs600_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
941 spin_lock_irqsave(&rdev->mc_idx_lock, flags);
945 spin_unlock_irqrestore(&rdev->mc_idx_lock, flags);
948 static void rs600_debugfs(struct radeon_device *rdev)
950 if (r100_debugfs_rbbm_init(rdev))
954 void rs600_set_safe_registers(struct radeon_device *rdev)
956 rdev->config.r300.reg_safe_bm = rs600_reg_safe_bm;
957 rdev->config.r300.reg_safe_bm_size = ARRAY_SIZE(rs600_reg_safe_bm);
960 static void rs600_mc_program(struct radeon_device *rdev)
965 rv515_mc_stop(rdev, &save);
968 if (rs600_mc_wait_for_idle(rdev))
969 dev_warn(rdev->dev, "Wait MC idle timeout before updating MC.\n");
977 S_000004_MC_FB_START(rdev->mc.vram_start >> 16) |
978 S_000004_MC_FB_TOP(rdev->mc.vram_end >> 16));
980 S_000134_HDP_FB_START(rdev->mc.vram_start >> 16));
982 rv515_mc_resume(rdev, &save);
985 static int rs600_startup(struct radeon_device *rdev)
989 rs600_mc_program(rdev);
991 rv515_clock_startup(rdev);
993 rs600_gpu_init(rdev);
996 r = rs600_gart_enable(rdev);
1001 r = radeon_wb_init(rdev);
1005 r = radeon_fence_driver_start_ring(rdev, RADEON_RING_TYPE_GFX_INDEX);
1007 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r);
1012 if (!rdev->irq.installed) {
1013 r = radeon_irq_kms_init(rdev);
1018 rs600_irq_set(rdev);
1019 rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL);
1021 r = r100_cp_init(rdev, 1024 * 1024);
1023 dev_err(rdev->dev, "failed initializing CP (%d).\n", r);
1027 r = radeon_ib_pool_init(rdev);
1029 dev_err(rdev->dev, "IB initialization failed (%d).\n", r);
1033 r = radeon_audio_init(rdev);
1035 dev_err(rdev->dev, "failed initializing audio\n");
1042 int rs600_resume(struct radeon_device *rdev)
1047 rs600_gart_disable(rdev);
1049 rv515_clock_startup(rdev);
1051 if (radeon_asic_reset(rdev)) {
1052 dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
1057 atom_asic_init(rdev->mode_info.atom_context);
1059 rv515_clock_startup(rdev);
1061 radeon_surface_init(rdev);
1063 rdev->accel_working = true;
1064 r = rs600_startup(rdev);
1066 rdev->accel_working = false;
1071 int rs600_suspend(struct radeon_device *rdev)
1073 radeon_pm_suspend(rdev);
1074 radeon_audio_fini(rdev);
1075 r100_cp_disable(rdev);
1076 radeon_wb_disable(rdev);
1077 rs600_irq_disable(rdev);
1078 rs600_gart_disable(rdev);
1082 void rs600_fini(struct radeon_device *rdev)
1084 radeon_pm_fini(rdev);
1085 radeon_audio_fini(rdev);
1086 r100_cp_fini(rdev);
1087 radeon_wb_fini(rdev);
1088 radeon_ib_pool_fini(rdev);
1089 radeon_gem_fini(rdev);
1090 rs600_gart_fini(rdev);
1091 radeon_irq_kms_fini(rdev);
1092 radeon_fence_driver_fini(rdev);
1093 radeon_bo_fini(rdev);
1094 radeon_atombios_fini(rdev);
1095 kfree(rdev->bios);
1096 rdev->bios = NULL;
1099 int rs600_init(struct radeon_device *rdev)
1104 rv515_vga_render_disable(rdev);
1106 radeon_scratch_init(rdev);
1108 radeon_surface_init(rdev);
1110 r100_restore_sanity(rdev);
1112 if (!radeon_get_bios(rdev)) {
1113 if (ASIC_IS_AVIVO(rdev))
1116 if (rdev->is_atom_bios) {
1117 r = radeon_atombios_init(rdev);
1121 dev_err(rdev->dev, "Expecting atombios for RS600 GPU\n");
1125 if (radeon_asic_reset(rdev)) {
1126 dev_warn(rdev->dev,
1132 if (radeon_boot_test_post_card(rdev) == false)
1136 radeon_get_clock_info(rdev->ddev);
1138 rs600_mc_init(rdev);
1139 rs600_debugfs(rdev);
1141 r = radeon_fence_driver_init(rdev);
1145 r = radeon_bo_init(rdev);
1148 r = rs600_gart_init(rdev);
1151 rs600_set_safe_registers(rdev);
1154 radeon_pm_init(rdev);
1156 rdev->accel_working = true;
1157 r = rs600_startup(rdev);
1160 dev_err(rdev->dev, "Disabling GPU acceleration\n");
1161 r100_cp_fini(rdev);
1162 radeon_wb_fini(rdev);
1163 radeon_ib_pool_fini(rdev);
1164 rs600_gart_fini(rdev);
1165 radeon_irq_kms_fini(rdev);
1166 rdev->accel_working = false;