Lines Matching refs:rdev
41 static int rs400_debugfs_pcie_gart_info_init(struct radeon_device *rdev);
43 void rs400_gart_adjust_size(struct radeon_device *rdev)
46 switch (rdev->mc.gtt_size/(1024*1024)) {
57 (unsigned)(rdev->mc.gtt_size >> 20));
60 rdev->mc.gtt_size = 32 * 1024 * 1024;
65 void rs400_gart_tlb_flush(struct radeon_device *rdev)
68 unsigned int timeout = rdev->usec_timeout;
81 int rs400_gart_init(struct radeon_device *rdev)
85 if (rdev->gart.ptr) {
90 switch(rdev->mc.gtt_size / (1024 * 1024)) {
103 r = radeon_gart_init(rdev);
106 if (rs400_debugfs_pcie_gart_info_init(rdev))
108 rdev->gart.table_size = rdev->gart.num_gpu_pages * 4;
109 return radeon_gart_table_ram_alloc(rdev);
112 int rs400_gart_enable(struct radeon_device *rdev)
121 switch(rdev->mc.gtt_size / (1024 * 1024)) {
147 if (rdev->family == CHIP_RS690 || (rdev->family == CHIP_RS740)) {
154 tmp = REG_SET(RS690_MC_AGP_TOP, rdev->mc.gtt_end >> 16);
155 tmp |= REG_SET(RS690_MC_AGP_START, rdev->mc.gtt_start >> 16);
156 if ((rdev->family == CHIP_RS690) || (rdev->family == CHIP_RS740)) {
166 tmp = (u32)rdev->gart.table_addr & 0xfffff000;
167 tmp |= (upper_32_bits(rdev->gart.table_addr) & 0xff) << 4;
180 if ((rdev->family == CHIP_RS690) || (rdev->family == CHIP_RS740)) {
191 rs400_gart_tlb_flush(rdev);
193 (unsigned)(rdev->mc.gtt_size >> 20),
194 (unsigned long long)rdev->gart.table_addr);
195 rdev->gart.ready = true;
199 void rs400_gart_disable(struct radeon_device *rdev)
209 void rs400_gart_fini(struct radeon_device *rdev)
211 radeon_gart_fini(rdev);
212 rs400_gart_disable(rdev);
213 radeon_gart_table_ram_free(rdev);
235 void rs400_gart_set_page(struct radeon_device *rdev, unsigned i,
238 u32 *gtt = rdev->gart.ptr;
242 int rs400_mc_wait_for_idle(struct radeon_device *rdev)
247 for (i = 0; i < rdev->usec_timeout; i++) {
258 static void rs400_gpu_init(struct radeon_device *rdev)
261 r420_pipes_init(rdev);
262 if (rs400_mc_wait_for_idle(rdev)) {
268 static void rs400_mc_init(struct radeon_device *rdev)
272 rs400_gart_adjust_size(rdev);
273 rdev->mc.igp_sideport_enabled = radeon_combios_sideport_present(rdev);
275 rdev->mc.vram_is_ddr = true;
276 rdev->mc.vram_width = 128;
277 r100_vram_init_sizes(rdev);
279 radeon_vram_location(rdev, &rdev->mc, base);
280 rdev->mc.gtt_base_align = rdev->mc.gtt_size - 1;
281 radeon_gtt_location(rdev, &rdev->mc);
282 radeon_update_bandwidth_info(rdev);
285 uint32_t rs400_mc_rreg(struct radeon_device *rdev, uint32_t reg)
290 spin_lock_irqsave(&rdev->mc_idx_lock, flags);
294 spin_unlock_irqrestore(&rdev->mc_idx_lock, flags);
298 void rs400_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
302 spin_lock_irqsave(&rdev->mc_idx_lock, flags);
306 spin_unlock_irqrestore(&rdev->mc_idx_lock, flags);
314 struct radeon_device *rdev = dev->dev_private;
323 if (rdev->family == CHIP_RS690 || (rdev->family == CHIP_RS740)) {
384 static int rs400_debugfs_pcie_gart_info_init(struct radeon_device *rdev)
387 return radeon_debugfs_add_files(rdev, rs400_gart_info_list, 1);
393 static void rs400_mc_program(struct radeon_device *rdev)
398 r100_mc_stop(rdev, &save);
401 if (rs400_mc_wait_for_idle(rdev))
402 dev_warn(rdev->dev, "rs400: Wait MC idle timeout before updating MC.\n");
404 S_000148_MC_FB_START(rdev->mc.vram_start >> 16) |
405 S_000148_MC_FB_TOP(rdev->mc.vram_end >> 16));
407 r100_mc_resume(rdev, &save);
410 static int rs400_startup(struct radeon_device *rdev)
414 r100_set_common_regs(rdev);
416 rs400_mc_program(rdev);
418 r300_clock_startup(rdev);
420 rs400_gpu_init(rdev);
421 r100_enable_bm(rdev);
424 r = rs400_gart_enable(rdev);
429 r = radeon_wb_init(rdev);
433 r = radeon_fence_driver_start_ring(rdev, RADEON_RING_TYPE_GFX_INDEX);
435 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r);
440 if (!rdev->irq.installed) {
441 r = radeon_irq_kms_init(rdev);
446 r100_irq_set(rdev);
447 rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL);
449 r = r100_cp_init(rdev, 1024 * 1024);
451 dev_err(rdev->dev, "failed initializing CP (%d).\n", r);
455 r = radeon_ib_pool_init(rdev);
457 dev_err(rdev->dev, "IB initialization failed (%d).\n", r);
464 int rs400_resume(struct radeon_device *rdev)
469 rs400_gart_disable(rdev);
471 r300_clock_startup(rdev);
473 rs400_mc_program(rdev);
475 if (radeon_asic_reset(rdev)) {
476 dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
481 radeon_combios_asic_init(rdev->ddev);
483 r300_clock_startup(rdev);
485 radeon_surface_init(rdev);
487 rdev->accel_working = true;
488 r = rs400_startup(rdev);
490 rdev->accel_working = false;
495 int rs400_suspend(struct radeon_device *rdev)
497 radeon_pm_suspend(rdev);
498 r100_cp_disable(rdev);
499 radeon_wb_disable(rdev);
500 r100_irq_disable(rdev);
501 rs400_gart_disable(rdev);
505 void rs400_fini(struct radeon_device *rdev)
507 radeon_pm_fini(rdev);
508 r100_cp_fini(rdev);
509 radeon_wb_fini(rdev);
510 radeon_ib_pool_fini(rdev);
511 radeon_gem_fini(rdev);
512 rs400_gart_fini(rdev);
513 radeon_irq_kms_fini(rdev);
514 radeon_fence_driver_fini(rdev);
515 radeon_bo_fini(rdev);
516 radeon_atombios_fini(rdev);
517 kfree(rdev->bios);
518 rdev->bios = NULL;
521 int rs400_init(struct radeon_device *rdev)
526 r100_vga_render_disable(rdev);
528 radeon_scratch_init(rdev);
530 radeon_surface_init(rdev);
533 r100_restore_sanity(rdev);
535 if (!radeon_get_bios(rdev)) {
536 if (ASIC_IS_AVIVO(rdev))
539 if (rdev->is_atom_bios) {
540 dev_err(rdev->dev, "Expecting combios for RS400/RS480 GPU\n");
543 r = radeon_combios_init(rdev);
548 if (radeon_asic_reset(rdev)) {
549 dev_warn(rdev->dev,
555 if (radeon_boot_test_post_card(rdev) == false)
559 radeon_get_clock_info(rdev->ddev);
561 rs400_mc_init(rdev);
563 r = radeon_fence_driver_init(rdev);
567 r = radeon_bo_init(rdev);
570 r = rs400_gart_init(rdev);
573 r300_set_reg_safe(rdev);
576 radeon_pm_init(rdev);
578 rdev->accel_working = true;
579 r = rs400_startup(rdev);
582 dev_err(rdev->dev, "Disabling GPU acceleration\n");
583 r100_cp_fini(rdev);
584 radeon_wb_fini(rdev);
585 radeon_ib_pool_fini(rdev);
586 rs400_gart_fini(rdev);
587 radeon_irq_kms_fini(rdev);
588 rdev->accel_working = false;