Lines Matching refs:rdev
50 static int radeon_debugfs_pm_init(struct radeon_device *rdev);
51 static bool radeon_pm_in_vbl(struct radeon_device *rdev);
52 static bool radeon_pm_debug_check_in_vbl(struct radeon_device *rdev, bool finish);
53 static void radeon_pm_update_profile(struct radeon_device *rdev);
54 static void radeon_pm_set_clocks(struct radeon_device *rdev);
56 int radeon_pm_get_type_index(struct radeon_device *rdev,
63 for (i = 0; i < rdev->pm.num_power_states; i++) {
64 if (rdev->pm.power_state[i].type == ps_type) {
71 return rdev->pm.default_power_state_index;
74 void radeon_pm_acpi_event_handler(struct radeon_device *rdev)
76 if ((rdev->pm.pm_method == PM_METHOD_DPM) && rdev->pm.dpm_enabled) {
77 mutex_lock(&rdev->pm.mutex);
79 rdev->pm.dpm.ac_power = true;
81 rdev->pm.dpm.ac_power = false;
82 if (rdev->family == CHIP_ARUBA) {
83 if (rdev->asic->dpm.enable_bapm)
84 radeon_dpm_enable_bapm(rdev, rdev->pm.dpm.ac_power);
86 mutex_unlock(&rdev->pm.mutex);
87 } else if (rdev->pm.pm_method == PM_METHOD_PROFILE) {
88 if (rdev->pm.profile == PM_PROFILE_AUTO) {
89 mutex_lock(&rdev->pm.mutex);
90 radeon_pm_update_profile(rdev);
91 radeon_pm_set_clocks(rdev);
92 mutex_unlock(&rdev->pm.mutex);
97 static void radeon_pm_update_profile(struct radeon_device *rdev)
99 switch (rdev->pm.profile) {
101 rdev->pm.profile_index = PM_PROFILE_DEFAULT_IDX;
105 if (rdev->pm.active_crtc_count > 1)
106 rdev->pm.profile_index = PM_PROFILE_HIGH_MH_IDX;
108 rdev->pm.profile_index = PM_PROFILE_HIGH_SH_IDX;
110 if (rdev->pm.active_crtc_count > 1)
111 rdev->pm.profile_index = PM_PROFILE_MID_MH_IDX;
113 rdev->pm.profile_index = PM_PROFILE_MID_SH_IDX;
117 if (rdev->pm.active_crtc_count > 1)
118 rdev->pm.profile_index = PM_PROFILE_LOW_MH_IDX;
120 rdev->pm.profile_index = PM_PROFILE_LOW_SH_IDX;
123 if (rdev->pm.active_crtc_count > 1)
124 rdev->pm.profile_index = PM_PROFILE_MID_MH_IDX;
126 rdev->pm.profile_index = PM_PROFILE_MID_SH_IDX;
129 if (rdev->pm.active_crtc_count > 1)
130 rdev->pm.profile_index = PM_PROFILE_HIGH_MH_IDX;
132 rdev->pm.profile_index = PM_PROFILE_HIGH_SH_IDX;
136 if (rdev->pm.active_crtc_count == 0) {
137 rdev->pm.requested_power_state_index =
138 rdev->pm.profiles[rdev->pm.profile_index].dpms_off_ps_idx;
139 rdev->pm.requested_clock_mode_index =
140 rdev->pm.profiles[rdev->pm.profile_index].dpms_off_cm_idx;
142 rdev->pm.requested_power_state_index =
143 rdev->pm.profiles[rdev->pm.profile_index].dpms_on_ps_idx;
144 rdev->pm.requested_clock_mode_index =
145 rdev->pm.profiles[rdev->pm.profile_index].dpms_on_cm_idx;
149 static void radeon_unmap_vram_bos(struct radeon_device *rdev)
153 if (list_empty(&rdev->gem.objects))
156 list_for_each_entry_safe(bo, n, &rdev->gem.objects, list) {
162 static void radeon_sync_with_vblank(struct radeon_device *rdev)
164 if (rdev->pm.active_crtcs) {
165 rdev->pm.vblank_sync = false;
167 rdev->irq.vblank_queue, rdev->pm.vblank_sync,
172 static void radeon_set_power_state(struct radeon_device *rdev)
177 if ((rdev->pm.requested_clock_mode_index == rdev->pm.current_clock_mode_index) &&
178 (rdev->pm.requested_power_state_index == rdev->pm.current_power_state_index))
181 if (radeon_gui_idle(rdev)) {
182 sclk = rdev->pm.power_state[rdev->pm.requested_power_state_index].
183 clock_info[rdev->pm.requested_clock_mode_index].sclk;
184 if (sclk > rdev->pm.default_sclk)
185 sclk = rdev->pm.default_sclk;
191 if ((rdev->pm.pm_method == PM_METHOD_PROFILE) &&
192 (rdev->family >= CHIP_BARTS) &&
193 rdev->pm.active_crtc_count &&
194 ((rdev->pm.profile_index == PM_PROFILE_MID_MH_IDX) ||
195 (rdev->pm.profile_index == PM_PROFILE_LOW_MH_IDX)))
196 mclk = rdev->pm.power_state[rdev->pm.requested_power_state_index].
197 clock_info[rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx].mclk;
199 mclk = rdev->pm.power_state[rdev->pm.requested_power_state_index].
200 clock_info[rdev->pm.requested_clock_mode_index].mclk;
202 if (mclk > rdev->pm.default_mclk)
203 mclk = rdev->pm.default_mclk;
206 if (sclk < rdev->pm.current_sclk)
209 radeon_sync_with_vblank(rdev);
211 if (rdev->pm.pm_method == PM_METHOD_DYNPM) {
212 if (!radeon_pm_in_vbl(rdev))
216 radeon_pm_prepare(rdev);
220 radeon_pm_misc(rdev);
223 if (sclk != rdev->pm.current_sclk) {
224 radeon_pm_debug_check_in_vbl(rdev, false);
225 radeon_set_engine_clock(rdev, sclk);
226 radeon_pm_debug_check_in_vbl(rdev, true);
227 rdev->pm.current_sclk = sclk;
232 if (rdev->asic->pm.set_memory_clock && (mclk != rdev->pm.current_mclk)) {
233 radeon_pm_debug_check_in_vbl(rdev, false);
234 radeon_set_memory_clock(rdev, mclk);
235 radeon_pm_debug_check_in_vbl(rdev, true);
236 rdev->pm.current_mclk = mclk;
242 radeon_pm_misc(rdev);
244 radeon_pm_finish(rdev);
246 rdev->pm.current_power_state_index = rdev->pm.requested_power_state_index;
247 rdev->pm.current_clock_mode_index = rdev->pm.requested_clock_mode_index;
252 static void radeon_pm_set_clocks(struct radeon_device *rdev)
258 if ((rdev->pm.requested_clock_mode_index == rdev->pm.current_clock_mode_index) &&
259 (rdev->pm.requested_power_state_index == rdev->pm.current_power_state_index))
262 down_write(&rdev->pm.mclk_lock);
263 mutex_lock(&rdev->ring_lock);
267 struct radeon_ring *ring = &rdev->ring[i];
271 r = radeon_fence_wait_empty(rdev, i);
274 mutex_unlock(&rdev->ring_lock);
275 up_write(&rdev->pm.mclk_lock);
280 radeon_unmap_vram_bos(rdev);
282 if (rdev->irq.installed) {
284 drm_for_each_crtc(crtc, rdev->ddev) {
285 if (rdev->pm.active_crtcs & (1 << i)) {
288 rdev->pm.req_vblank |= (1 << i);
297 radeon_set_power_state(rdev);
299 if (rdev->irq.installed) {
301 drm_for_each_crtc(crtc, rdev->ddev) {
302 if (rdev->pm.req_vblank & (1 << i)) {
303 rdev->pm.req_vblank &= ~(1 << i);
311 radeon_update_bandwidth_info(rdev);
312 if (rdev->pm.active_crtc_count)
313 radeon_bandwidth_update(rdev);
315 rdev->pm.dynpm_planned_action = DYNPM_ACTION_NONE;
317 mutex_unlock(&rdev->ring_lock);
318 up_write(&rdev->pm.mclk_lock);
321 static void radeon_pm_print_states(struct radeon_device *rdev)
327 DRM_DEBUG_DRIVER("%d Power State(s)\n", rdev->pm.num_power_states);
328 for (i = 0; i < rdev->pm.num_power_states; i++) {
329 power_state = &rdev->pm.power_state[i];
332 if (i == rdev->pm.default_power_state_index)
334 if ((rdev->flags & RADEON_IS_PCIE) && !(rdev->flags & RADEON_IS_IGP))
341 if (rdev->flags & RADEON_IS_IGP)
360 struct radeon_device *rdev = ddev->dev_private;
361 int cp = rdev->pm.profile;
376 struct radeon_device *rdev = ddev->dev_private;
379 if ((rdev->flags & RADEON_IS_PX) &&
383 mutex_lock(&rdev->pm.mutex);
384 if (rdev->pm.pm_method == PM_METHOD_PROFILE) {
386 rdev->pm.profile = PM_PROFILE_DEFAULT;
388 rdev->pm.profile = PM_PROFILE_AUTO;
390 rdev->pm.profile = PM_PROFILE_LOW;
392 rdev->pm.profile = PM_PROFILE_MID;
394 rdev->pm.profile = PM_PROFILE_HIGH;
399 radeon_pm_update_profile(rdev);
400 radeon_pm_set_clocks(rdev);
405 mutex_unlock(&rdev->pm.mutex);
415 struct radeon_device *rdev = ddev->dev_private;
416 int pm = rdev->pm.pm_method;
429 struct radeon_device *rdev = ddev->dev_private;
432 if ((rdev->flags & RADEON_IS_PX) &&
439 if (rdev->pm.pm_method == PM_METHOD_DPM) {
445 mutex_lock(&rdev->pm.mutex);
446 rdev->pm.pm_method = PM_METHOD_DYNPM;
447 rdev->pm.dynpm_state = DYNPM_STATE_PAUSED;
448 rdev->pm.dynpm_planned_action = DYNPM_ACTION_DEFAULT;
449 mutex_unlock(&rdev->pm.mutex);
451 mutex_lock(&rdev->pm.mutex);
453 rdev->pm.dynpm_state = DYNPM_STATE_DISABLED;
454 rdev->pm.dynpm_planned_action = DYNPM_ACTION_NONE;
455 rdev->pm.pm_method = PM_METHOD_PROFILE;
456 mutex_unlock(&rdev->pm.mutex);
457 cancel_delayed_work_sync(&rdev->pm.dynpm_idle_work);
462 radeon_pm_compute_clocks(rdev);
472 struct radeon_device *rdev = ddev->dev_private;
473 enum radeon_pm_state_type pm = rdev->pm.dpm.user_state;
486 struct radeon_device *rdev = ddev->dev_private;
488 mutex_lock(&rdev->pm.mutex);
490 rdev->pm.dpm.user_state = POWER_STATE_TYPE_BATTERY;
492 rdev->pm.dpm.user_state = POWER_STATE_TYPE_BALANCED;
494 rdev->pm.dpm.user_state = POWER_STATE_TYPE_PERFORMANCE;
496 mutex_unlock(&rdev->pm.mutex);
500 mutex_unlock(&rdev->pm.mutex);
503 if (!(rdev->flags & RADEON_IS_PX) ||
505 radeon_pm_compute_clocks(rdev);
516 struct radeon_device *rdev = ddev->dev_private;
517 enum radeon_dpm_forced_level level = rdev->pm.dpm.forced_level;
519 if ((rdev->flags & RADEON_IS_PX) &&
534 struct radeon_device *rdev = ddev->dev_private;
539 if ((rdev->flags & RADEON_IS_PX) &&
543 mutex_lock(&rdev->pm.mutex);
554 if (rdev->asic->dpm.force_performance_level) {
555 if (rdev->pm.dpm.thermal_active) {
559 ret = radeon_dpm_force_performance_level(rdev, level);
564 mutex_unlock(&rdev->pm.mutex);
573 struct radeon_device *rdev = dev_get_drvdata(dev);
576 if (rdev->asic->dpm.fan_ctrl_get_mode)
577 pwm_mode = rdev->asic->dpm.fan_ctrl_get_mode(rdev);
588 struct radeon_device *rdev = dev_get_drvdata(dev);
592 if(!rdev->asic->dpm.fan_ctrl_set_mode)
601 rdev->asic->dpm.fan_ctrl_set_mode(rdev, FDO_PWM_MODE_STATIC);
604 rdev->asic->dpm.fan_ctrl_set_mode(rdev, 0);
629 struct radeon_device *rdev = dev_get_drvdata(dev);
639 err = rdev->asic->dpm.set_fan_speed_percent(rdev, value);
650 struct radeon_device *rdev = dev_get_drvdata(dev);
654 err = rdev->asic->dpm.get_fan_speed_percent(rdev, &speed);
674 struct radeon_device *rdev = dev_get_drvdata(dev);
675 struct drm_device *ddev = rdev->ddev;
679 if ((rdev->flags & RADEON_IS_PX) &&
683 if (rdev->asic->pm.get_temperature)
684 temp = radeon_get_temperature(rdev);
695 struct radeon_device *rdev = dev_get_drvdata(dev);
700 temp = rdev->pm.dpm.thermal.min_temp;
702 temp = rdev->pm.dpm.thermal.max_temp;
718 struct radeon_device *rdev = dev_get_drvdata(dev);
719 struct drm_device *ddev = rdev->ddev;
723 if ((rdev->flags & RADEON_IS_PX) &&
727 if (rdev->asic->dpm.get_current_sclk)
728 sclk = radeon_dpm_get_current_sclk(rdev);
757 struct radeon_device *rdev = dev_get_drvdata(dev);
761 if (rdev->pm.pm_method != PM_METHOD_DPM &&
772 if (rdev->pm.no_fan &&
780 if ((!rdev->asic->dpm.get_fan_speed_percent &&
782 (!rdev->asic->dpm.fan_ctrl_get_mode &&
786 if ((!rdev->asic->dpm.set_fan_speed_percent &&
788 (!rdev->asic->dpm.fan_ctrl_set_mode &&
793 if ((!rdev->asic->dpm.set_fan_speed_percent &&
794 !rdev->asic->dpm.get_fan_speed_percent) &&
812 static int radeon_hwmon_init(struct radeon_device *rdev)
816 switch (rdev->pm.int_thermal_type) {
825 if (rdev->asic->pm.get_temperature == NULL)
827 rdev->pm.int_hwmon_dev = hwmon_device_register_with_groups(rdev->dev,
828 "radeon", rdev,
830 if (IS_ERR(rdev->pm.int_hwmon_dev)) {
831 err = PTR_ERR(rdev->pm.int_hwmon_dev);
832 dev_err(rdev->dev,
843 static void radeon_hwmon_fini(struct radeon_device *rdev)
845 if (rdev->pm.int_hwmon_dev)
846 hwmon_device_unregister(rdev->pm.int_hwmon_dev);
851 struct radeon_device *rdev =
857 if (!rdev->pm.dpm_enabled)
860 if (rdev->asic->pm.get_temperature) {
861 int temp = radeon_get_temperature(rdev);
863 if (temp < rdev->pm.dpm.thermal.min_temp)
865 dpm_state = rdev->pm.dpm.user_state;
867 if (rdev->pm.dpm.thermal.high_to_low)
869 dpm_state = rdev->pm.dpm.user_state;
871 mutex_lock(&rdev->pm.mutex);
873 rdev->pm.dpm.thermal_active = true;
875 rdev->pm.dpm.thermal_active = false;
876 rdev->pm.dpm.state = dpm_state;
877 mutex_unlock(&rdev->pm.mutex);
879 radeon_pm_compute_clocks(rdev);
882 static bool radeon_dpm_single_display(struct radeon_device *rdev)
884 bool single_display = (rdev->pm.dpm.new_active_crtc_count < 2) ?
888 if (single_display && rdev->asic->dpm.vblank_too_short) {
889 if (radeon_dpm_vblank_too_short(rdev))
896 if (single_display && (r600_dpm_get_vrefresh(rdev) >= 120))
902 static struct radeon_ps *radeon_dpm_pick_power_state(struct radeon_device *rdev,
908 bool single_display = radeon_dpm_single_display(rdev);
921 for (i = 0; i < rdev->pm.dpm.num_ps; i++) {
922 ps = &rdev->pm.dpm.ps[i];
955 if (rdev->pm.dpm.uvd_ps)
956 return rdev->pm.dpm.uvd_ps;
976 return rdev->pm.dpm.boot_ps;
1005 if (rdev->pm.dpm.uvd_ps) {
1006 return rdev->pm.dpm.uvd_ps;
1029 static void radeon_dpm_change_power_state_locked(struct radeon_device *rdev)
1035 bool single_display = radeon_dpm_single_display(rdev);
1038 if (!rdev->pm.dpm_enabled)
1041 if (rdev->pm.dpm.user_state != rdev->pm.dpm.state) {
1043 if ((!rdev->pm.dpm.thermal_active) &&
1044 (!rdev->pm.dpm.uvd_active))
1045 rdev->pm.dpm.state = rdev->pm.dpm.user_state;
1047 dpm_state = rdev->pm.dpm.state;
1049 ps = radeon_dpm_pick_power_state(rdev, dpm_state);
1051 rdev->pm.dpm.requested_ps = ps;
1056 if (rdev->pm.dpm.current_ps == rdev->pm.dpm.requested_ps) {
1058 if (ps->vce_active != rdev->pm.dpm.vce_active)
1061 if (rdev->pm.dpm.single_display != single_display)
1063 if ((rdev->family < CHIP_BARTS) || (rdev->flags & RADEON_IS_IGP)) {
1067 if (rdev->pm.dpm.new_active_crtcs != rdev->pm.dpm.current_active_crtcs) {
1069 radeon_bandwidth_update(rdev);
1071 radeon_dpm_display_configuration_changed(rdev);
1072 rdev->pm.dpm.current_active_crtcs = rdev->pm.dpm.new_active_crtcs;
1073 rdev->pm.dpm.current_active_crtc_count = rdev->pm.dpm.new_active_crtc_count;
1081 if (rdev->pm.dpm.new_active_crtcs ==
1082 rdev->pm.dpm.current_active_crtcs) {
1085 if ((rdev->pm.dpm.current_active_crtc_count > 1) &&
1086 (rdev->pm.dpm.new_active_crtc_count > 1)) {
1088 radeon_bandwidth_update(rdev);
1090 radeon_dpm_display_configuration_changed(rdev);
1091 rdev->pm.dpm.current_active_crtcs = rdev->pm.dpm.new_active_crtcs;
1092 rdev->pm.dpm.current_active_crtc_count = rdev->pm.dpm.new_active_crtc_count;
1102 radeon_dpm_print_power_state(rdev, rdev->pm.dpm.current_ps);
1104 radeon_dpm_print_power_state(rdev, rdev->pm.dpm.requested_ps);
1107 down_write(&rdev->pm.mclk_lock);
1108 mutex_lock(&rdev->ring_lock);
1111 ps->vce_active = rdev->pm.dpm.vce_active;
1113 ret = radeon_dpm_pre_set_power_state(rdev);
1118 radeon_bandwidth_update(rdev);
1120 radeon_dpm_display_configuration_changed(rdev);
1124 struct radeon_ring *ring = &rdev->ring[i];
1126 radeon_fence_wait_empty(rdev, i);
1130 radeon_dpm_set_power_state(rdev);
1133 rdev->pm.dpm.current_ps = rdev->pm.dpm.requested_ps;
1135 radeon_dpm_post_set_power_state(rdev);
1137 rdev->pm.dpm.current_active_crtcs = rdev->pm.dpm.new_active_crtcs;
1138 rdev->pm.dpm.current_active_crtc_count = rdev->pm.dpm.new_active_crtc_count;
1139 rdev->pm.dpm.single_display = single_display;
1141 if (rdev->asic->dpm.force_performance_level) {
1142 if (rdev->pm.dpm.thermal_active) {
1143 enum radeon_dpm_forced_level level = rdev->pm.dpm.forced_level;
1145 radeon_dpm_force_performance_level(rdev, RADEON_DPM_FORCED_LEVEL_LOW);
1147 rdev->pm.dpm.forced_level = level;
1150 radeon_dpm_force_performance_level(rdev, rdev->pm.dpm.forced_level);
1155 mutex_unlock(&rdev->ring_lock);
1156 up_write(&rdev->pm.mclk_lock);
1159 void radeon_dpm_enable_uvd(struct radeon_device *rdev, bool enable)
1163 if (rdev->asic->dpm.powergate_uvd) {
1164 mutex_lock(&rdev->pm.mutex);
1167 enable |= rdev->pm.dpm.sd > 0;
1168 enable |= rdev->pm.dpm.hd > 0;
1170 radeon_dpm_powergate_uvd(rdev, !enable);
1171 mutex_unlock(&rdev->pm.mutex);
1174 mutex_lock(&rdev->pm.mutex);
1175 rdev->pm.dpm.uvd_active = true;
1178 if ((rdev->pm.dpm.sd == 1) && (rdev->pm.dpm.hd == 0))
1180 else if ((rdev->pm.dpm.sd == 2) && (rdev->pm.dpm.hd == 0))
1182 else if ((rdev->pm.dpm.sd == 0) && (rdev->pm.dpm.hd == 1))
1184 else if ((rdev->pm.dpm.sd == 0) && (rdev->pm.dpm.hd == 2))
1189 rdev->pm.dpm.state = dpm_state;
1190 mutex_unlock(&rdev->pm.mutex);
1192 mutex_lock(&rdev->pm.mutex);
1193 rdev->pm.dpm.uvd_active = false;
1194 mutex_unlock(&rdev->pm.mutex);
1197 radeon_pm_compute_clocks(rdev);
1201 void radeon_dpm_enable_vce(struct radeon_device *rdev, bool enable)
1204 mutex_lock(&rdev->pm.mutex);
1205 rdev->pm.dpm.vce_active = true;
1207 rdev->pm.dpm.vce_level = RADEON_VCE_LEVEL_AC_ALL;
1208 mutex_unlock(&rdev->pm.mutex);
1210 mutex_lock(&rdev->pm.mutex);
1211 rdev->pm.dpm.vce_active = false;
1212 mutex_unlock(&rdev->pm.mutex);
1215 radeon_pm_compute_clocks(rdev);
1218 static void radeon_pm_suspend_old(struct radeon_device *rdev)
1220 mutex_lock(&rdev->pm.mutex);
1221 if (rdev->pm.pm_method == PM_METHOD_DYNPM) {
1222 if (rdev->pm.dynpm_state == DYNPM_STATE_ACTIVE)
1223 rdev->pm.dynpm_state = DYNPM_STATE_SUSPENDED;
1225 mutex_unlock(&rdev->pm.mutex);
1227 cancel_delayed_work_sync(&rdev->pm.dynpm_idle_work);
1230 static void radeon_pm_suspend_dpm(struct radeon_device *rdev)
1232 mutex_lock(&rdev->pm.mutex);
1234 radeon_dpm_disable(rdev);
1236 rdev->pm.dpm.current_ps = rdev->pm.dpm.requested_ps = rdev->pm.dpm.boot_ps;
1237 rdev->pm.dpm_enabled = false;
1238 mutex_unlock(&rdev->pm.mutex);
1241 void radeon_pm_suspend(struct radeon_device *rdev)
1243 if (rdev->pm.pm_method == PM_METHOD_DPM)
1244 radeon_pm_suspend_dpm(rdev);
1246 radeon_pm_suspend_old(rdev);
1249 static void radeon_pm_resume_old(struct radeon_device *rdev)
1252 if ((rdev->family >= CHIP_BARTS) &&
1253 (rdev->family <= CHIP_CAYMAN) &&
1254 rdev->mc_fw) {
1255 if (rdev->pm.default_vddc)
1256 radeon_atom_set_voltage(rdev, rdev->pm.default_vddc,
1258 if (rdev->pm.default_vddci)
1259 radeon_atom_set_voltage(rdev, rdev->pm.default_vddci,
1261 if (rdev->pm.default_sclk)
1262 radeon_set_engine_clock(rdev, rdev->pm.default_sclk);
1263 if (rdev->pm.default_mclk)
1264 radeon_set_memory_clock(rdev, rdev->pm.default_mclk);
1267 mutex_lock(&rdev->pm.mutex);
1268 rdev->pm.current_power_state_index = rdev->pm.default_power_state_index;
1269 rdev->pm.current_clock_mode_index = 0;
1270 rdev->pm.current_sclk = rdev->pm.default_sclk;
1271 rdev->pm.current_mclk = rdev->pm.default_mclk;
1272 if (rdev->pm.power_state) {
1273 rdev->pm.current_vddc = rdev->pm.power_state[rdev->pm.default_power_state_index].clock_info[0].voltage.voltage;
1274 rdev->pm.current_vddci = rdev->pm.power_state[rdev->pm.default_power_state_index].clock_info[0].voltage.vddci;
1276 if (rdev->pm.pm_method == PM_METHOD_DYNPM
1277 && rdev->pm.dynpm_state == DYNPM_STATE_SUSPENDED) {
1278 rdev->pm.dynpm_state = DYNPM_STATE_ACTIVE;
1279 schedule_delayed_work(&rdev->pm.dynpm_idle_work,
1282 mutex_unlock(&rdev->pm.mutex);
1283 radeon_pm_compute_clocks(rdev);
1286 static void radeon_pm_resume_dpm(struct radeon_device *rdev)
1291 mutex_lock(&rdev->pm.mutex);
1292 rdev->pm.dpm.current_ps = rdev->pm.dpm.requested_ps = rdev->pm.dpm.boot_ps;
1293 radeon_dpm_setup_asic(rdev);
1294 ret = radeon_dpm_enable(rdev);
1295 mutex_unlock(&rdev->pm.mutex);
1298 rdev->pm.dpm_enabled = true;
1303 if ((rdev->family >= CHIP_BARTS) &&
1304 (rdev->family <= CHIP_CAYMAN) &&
1305 rdev->mc_fw) {
1306 if (rdev->pm.default_vddc)
1307 radeon_atom_set_voltage(rdev, rdev->pm.default_vddc,
1309 if (rdev->pm.default_vddci)
1310 radeon_atom_set_voltage(rdev, rdev->pm.default_vddci,
1312 if (rdev->pm.default_sclk)
1313 radeon_set_engine_clock(rdev, rdev->pm.default_sclk);
1314 if (rdev->pm.default_mclk)
1315 radeon_set_memory_clock(rdev, rdev->pm.default_mclk);
1319 void radeon_pm_resume(struct radeon_device *rdev)
1321 if (rdev->pm.pm_method == PM_METHOD_DPM)
1322 radeon_pm_resume_dpm(rdev);
1324 radeon_pm_resume_old(rdev);
1327 static int radeon_pm_init_old(struct radeon_device *rdev)
1331 rdev->pm.profile = PM_PROFILE_DEFAULT;
1332 rdev->pm.dynpm_state = DYNPM_STATE_DISABLED;
1333 rdev->pm.dynpm_planned_action = DYNPM_ACTION_NONE;
1334 rdev->pm.dynpm_can_upclock = true;
1335 rdev->pm.dynpm_can_downclock = true;
1336 rdev->pm.default_sclk = rdev->clock.default_sclk;
1337 rdev->pm.default_mclk = rdev->clock.default_mclk;
1338 rdev->pm.current_sclk = rdev->clock.default_sclk;
1339 rdev->pm.current_mclk = rdev->clock.default_mclk;
1340 rdev->pm.int_thermal_type = THERMAL_TYPE_NONE;
1342 if (rdev->bios) {
1343 if (rdev->is_atom_bios)
1344 radeon_atombios_get_power_modes(rdev);
1346 radeon_combios_get_power_modes(rdev);
1347 radeon_pm_print_states(rdev);
1348 radeon_pm_init_profile(rdev);
1350 if ((rdev->family >= CHIP_BARTS) &&
1351 (rdev->family <= CHIP_CAYMAN) &&
1352 rdev->mc_fw) {
1353 if (rdev->pm.default_vddc)
1354 radeon_atom_set_voltage(rdev, rdev->pm.default_vddc,
1356 if (rdev->pm.default_vddci)
1357 radeon_atom_set_voltage(rdev, rdev->pm.default_vddci,
1359 if (rdev->pm.default_sclk)
1360 radeon_set_engine_clock(rdev, rdev->pm.default_sclk);
1361 if (rdev->pm.default_mclk)
1362 radeon_set_memory_clock(rdev, rdev->pm.default_mclk);
1367 ret = radeon_hwmon_init(rdev);
1371 INIT_DELAYED_WORK(&rdev->pm.dynpm_idle_work, radeon_dynpm_idle_work_handler);
1373 if (rdev->pm.num_power_states > 1) {
1374 if (radeon_debugfs_pm_init(rdev)) {
1384 static void radeon_dpm_print_power_states(struct radeon_device *rdev)
1388 for (i = 0; i < rdev->pm.dpm.num_ps; i++) {
1390 radeon_dpm_print_power_state(rdev, &rdev->pm.dpm.ps[i]);
1394 static int radeon_pm_init_dpm(struct radeon_device *rdev)
1399 rdev->pm.dpm.state = POWER_STATE_TYPE_BALANCED;
1400 rdev->pm.dpm.user_state = POWER_STATE_TYPE_BALANCED;
1401 rdev->pm.dpm.forced_level = RADEON_DPM_FORCED_LEVEL_AUTO;
1402 rdev->pm.default_sclk = rdev->clock.default_sclk;
1403 rdev->pm.default_mclk = rdev->clock.default_mclk;
1404 rdev->pm.current_sclk = rdev->clock.default_sclk;
1405 rdev->pm.current_mclk = rdev->clock.default_mclk;
1406 rdev->pm.int_thermal_type = THERMAL_TYPE_NONE;
1408 if (rdev->bios && rdev->is_atom_bios)
1409 radeon_atombios_get_power_modes(rdev);
1414 ret = radeon_hwmon_init(rdev);
1418 INIT_WORK(&rdev->pm.dpm.thermal.work, radeon_dpm_thermal_work_handler);
1419 mutex_lock(&rdev->pm.mutex);
1420 radeon_dpm_init(rdev);
1421 rdev->pm.dpm.current_ps = rdev->pm.dpm.requested_ps = rdev->pm.dpm.boot_ps;
1423 radeon_dpm_print_power_states(rdev);
1424 radeon_dpm_setup_asic(rdev);
1425 ret = radeon_dpm_enable(rdev);
1426 mutex_unlock(&rdev->pm.mutex);
1429 rdev->pm.dpm_enabled = true;
1431 if (radeon_debugfs_pm_init(rdev)) {
1440 rdev->pm.dpm_enabled = false;
1441 if ((rdev->family >= CHIP_BARTS) &&
1442 (rdev->family <= CHIP_CAYMAN) &&
1443 rdev->mc_fw) {
1444 if (rdev->pm.default_vddc)
1445 radeon_atom_set_voltage(rdev, rdev->pm.default_vddc,
1447 if (rdev->pm.default_vddci)
1448 radeon_atom_set_voltage(rdev, rdev->pm.default_vddci,
1450 if (rdev->pm.default_sclk)
1451 radeon_set_engine_clock(rdev, rdev->pm.default_sclk);
1452 if (rdev->pm.default_mclk)
1453 radeon_set_memory_clock(rdev, rdev->pm.default_mclk);
1475 int radeon_pm_init(struct radeon_device *rdev)
1482 if (rdev->pdev->vendor == p->chip_vendor &&
1483 rdev->pdev->device == p->chip_device &&
1484 rdev->pdev->subsystem_vendor == p->subsys_vendor &&
1485 rdev->pdev->subsystem_device == p->subsys_device) {
1493 switch (rdev->family) {
1503 if (!rdev->rlc_fw)
1504 rdev->pm.pm_method = PM_METHOD_PROFILE;
1505 else if ((rdev->family >= CHIP_RV770) &&
1506 (!(rdev->flags & RADEON_IS_IGP)) &&
1507 (!rdev->smc_fw))
1508 rdev->pm.pm_method = PM_METHOD_PROFILE;
1510 rdev->pm.pm_method = PM_METHOD_DPM;
1512 rdev->pm.pm_method = PM_METHOD_PROFILE;
1541 if (!rdev->rlc_fw)
1542 rdev->pm.pm_method = PM_METHOD_PROFILE;
1543 else if ((rdev->family >= CHIP_RV770) &&
1544 (!(rdev->flags & RADEON_IS_IGP)) &&
1545 (!rdev->smc_fw))
1546 rdev->pm.pm_method = PM_METHOD_PROFILE;
1548 rdev->pm.pm_method = PM_METHOD_PROFILE;
1550 rdev->pm.pm_method = PM_METHOD_PROFILE;
1552 rdev->pm.pm_method = PM_METHOD_DPM;
1556 rdev->pm.pm_method = PM_METHOD_PROFILE;
1560 if (rdev->pm.pm_method == PM_METHOD_DPM)
1561 return radeon_pm_init_dpm(rdev);
1563 return radeon_pm_init_old(rdev);
1566 int radeon_pm_late_init(struct radeon_device *rdev)
1570 if (rdev->pm.pm_method == PM_METHOD_DPM) {
1571 if (rdev->pm.dpm_enabled) {
1572 if (!rdev->pm.sysfs_initialized) {
1573 ret = device_create_file(rdev->dev, &dev_attr_power_dpm_state);
1576 ret = device_create_file(rdev->dev, &dev_attr_power_dpm_force_performance_level);
1580 ret = device_create_file(rdev->dev, &dev_attr_power_profile);
1583 ret = device_create_file(rdev->dev, &dev_attr_power_method);
1586 rdev->pm.sysfs_initialized = true;
1589 mutex_lock(&rdev->pm.mutex);
1590 ret = radeon_dpm_late_enable(rdev);
1591 mutex_unlock(&rdev->pm.mutex);
1593 rdev->pm.dpm_enabled = false;
1599 radeon_pm_compute_clocks(rdev);
1603 if ((rdev->pm.num_power_states > 1) &&
1604 (!rdev->pm.sysfs_initialized)) {
1606 ret = device_create_file(rdev->dev, &dev_attr_power_profile);
1609 ret = device_create_file(rdev->dev, &dev_attr_power_method);
1613 rdev->pm.sysfs_initialized = true;
1619 static void radeon_pm_fini_old(struct radeon_device *rdev)
1621 if (rdev->pm.num_power_states > 1) {
1622 mutex_lock(&rdev->pm.mutex);
1623 if (rdev->pm.pm_method == PM_METHOD_PROFILE) {
1624 rdev->pm.profile = PM_PROFILE_DEFAULT;
1625 radeon_pm_update_profile(rdev);
1626 radeon_pm_set_clocks(rdev);
1627 } else if (rdev->pm.pm_method == PM_METHOD_DYNPM) {
1629 rdev->pm.dynpm_state = DYNPM_STATE_DISABLED;
1630 rdev->pm.dynpm_planned_action = DYNPM_ACTION_DEFAULT;
1631 radeon_pm_set_clocks(rdev);
1633 mutex_unlock(&rdev->pm.mutex);
1635 cancel_delayed_work_sync(&rdev->pm.dynpm_idle_work);
1637 device_remove_file(rdev->dev, &dev_attr_power_profile);
1638 device_remove_file(rdev->dev, &dev_attr_power_method);
1641 radeon_hwmon_fini(rdev);
1642 kfree(rdev->pm.power_state);
1645 static void radeon_pm_fini_dpm(struct radeon_device *rdev)
1647 if (rdev->pm.num_power_states > 1) {
1648 mutex_lock(&rdev->pm.mutex);
1649 radeon_dpm_disable(rdev);
1650 mutex_unlock(&rdev->pm.mutex);
1652 device_remove_file(rdev->dev, &dev_attr_power_dpm_state);
1653 device_remove_file(rdev->dev, &dev_attr_power_dpm_force_performance_level);
1655 device_remove_file(rdev->dev, &dev_attr_power_profile);
1656 device_remove_file(rdev->dev, &dev_attr_power_method);
1658 radeon_dpm_fini(rdev);
1660 radeon_hwmon_fini(rdev);
1661 kfree(rdev->pm.power_state);
1664 void radeon_pm_fini(struct radeon_device *rdev)
1666 if (rdev->pm.pm_method == PM_METHOD_DPM)
1667 radeon_pm_fini_dpm(rdev);
1669 radeon_pm_fini_old(rdev);
1672 static void radeon_pm_compute_clocks_old(struct radeon_device *rdev)
1674 struct drm_device *ddev = rdev->ddev;
1678 if (rdev->pm.num_power_states < 2)
1681 mutex_lock(&rdev->pm.mutex);
1683 rdev->pm.active_crtcs = 0;
1684 rdev->pm.active_crtc_count = 0;
1685 if (rdev->num_crtc && rdev->mode_info.mode_config_initialized) {
1690 rdev->pm.active_crtcs |= (1 << radeon_crtc->crtc_id);
1691 rdev->pm.active_crtc_count++;
1696 if (rdev->pm.pm_method == PM_METHOD_PROFILE) {
1697 radeon_pm_update_profile(rdev);
1698 radeon_pm_set_clocks(rdev);
1699 } else if (rdev->pm.pm_method == PM_METHOD_DYNPM) {
1700 if (rdev->pm.dynpm_state != DYNPM_STATE_DISABLED) {
1701 if (rdev->pm.active_crtc_count > 1) {
1702 if (rdev->pm.dynpm_state == DYNPM_STATE_ACTIVE) {
1703 cancel_delayed_work(&rdev->pm.dynpm_idle_work);
1705 rdev->pm.dynpm_state = DYNPM_STATE_PAUSED;
1706 rdev->pm.dynpm_planned_action = DYNPM_ACTION_DEFAULT;
1707 radeon_pm_get_dynpm_state(rdev);
1708 radeon_pm_set_clocks(rdev);
1712 } else if (rdev->pm.active_crtc_count == 1) {
1715 if (rdev->pm.dynpm_state == DYNPM_STATE_MINIMUM) {
1716 rdev->pm.dynpm_state = DYNPM_STATE_ACTIVE;
1717 rdev->pm.dynpm_planned_action = DYNPM_ACTION_UPCLOCK;
1718 radeon_pm_get_dynpm_state(rdev);
1719 radeon_pm_set_clocks(rdev);
1721 schedule_delayed_work(&rdev->pm.dynpm_idle_work,
1723 } else if (rdev->pm.dynpm_state == DYNPM_STATE_PAUSED) {
1724 rdev->pm.dynpm_state = DYNPM_STATE_ACTIVE;
1725 schedule_delayed_work(&rdev->pm.dynpm_idle_work,
1730 if (rdev->pm.dynpm_state != DYNPM_STATE_MINIMUM) {
1731 cancel_delayed_work(&rdev->pm.dynpm_idle_work);
1733 rdev->pm.dynpm_state = DYNPM_STATE_MINIMUM;
1734 rdev->pm.dynpm_planned_action = DYNPM_ACTION_MINIMUM;
1735 radeon_pm_get_dynpm_state(rdev);
1736 radeon_pm_set_clocks(rdev);
1742 mutex_unlock(&rdev->pm.mutex);
1745 static void radeon_pm_compute_clocks_dpm(struct radeon_device *rdev)
1747 struct drm_device *ddev = rdev->ddev;
1752 if (!rdev->pm.dpm_enabled)
1755 mutex_lock(&rdev->pm.mutex);
1758 rdev->pm.dpm.new_active_crtcs = 0;
1759 rdev->pm.dpm.new_active_crtc_count = 0;
1760 rdev->pm.dpm.high_pixelclock_count = 0;
1761 if (rdev->num_crtc && rdev->mode_info.mode_config_initialized) {
1766 rdev->pm.dpm.new_active_crtcs |= (1 << radeon_crtc->crtc_id);
1767 rdev->pm.dpm.new_active_crtc_count++;
1773 rdev->pm.dpm.high_pixelclock_count++;
1780 rdev->pm.dpm.ac_power = true;
1782 rdev->pm.dpm.ac_power = false;
1784 radeon_dpm_change_power_state_locked(rdev);
1786 mutex_unlock(&rdev->pm.mutex);
1790 void radeon_pm_compute_clocks(struct radeon_device *rdev)
1792 if (rdev->pm.pm_method == PM_METHOD_DPM)
1793 radeon_pm_compute_clocks_dpm(rdev);
1795 radeon_pm_compute_clocks_old(rdev);
1798 static bool radeon_pm_in_vbl(struct radeon_device *rdev)
1806 for (crtc = 0; (crtc < rdev->num_crtc) && in_vbl; crtc++) {
1807 if (rdev->pm.active_crtcs & (1 << crtc)) {
1808 vbl_status = radeon_get_crtc_scanoutpos(rdev->ddev,
1812 &rdev->mode_info.crtcs[crtc]->base.hwmode);
1822 static bool radeon_pm_debug_check_in_vbl(struct radeon_device *rdev, bool finish)
1825 bool in_vbl = radeon_pm_in_vbl(rdev);
1835 struct radeon_device *rdev;
1837 rdev = container_of(work, struct radeon_device,
1840 resched = ttm_bo_lock_delayed_workqueue(&rdev->mman.bdev);
1841 mutex_lock(&rdev->pm.mutex);
1842 if (rdev->pm.dynpm_state == DYNPM_STATE_ACTIVE) {
1847 struct radeon_ring *ring = &rdev->ring[i];
1850 not_processed += radeon_fence_count_emitted(rdev, i);
1857 if (rdev->pm.dynpm_planned_action == DYNPM_ACTION_DOWNCLOCK) {
1858 rdev->pm.dynpm_planned_action = DYNPM_ACTION_NONE;
1859 } else if (rdev->pm.dynpm_planned_action == DYNPM_ACTION_NONE &&
1860 rdev->pm.dynpm_can_upclock) {
1861 rdev->pm.dynpm_planned_action =
1863 rdev->pm.dynpm_action_timeout = jiffies +
1867 if (rdev->pm.dynpm_planned_action == DYNPM_ACTION_UPCLOCK) {
1868 rdev->pm.dynpm_planned_action = DYNPM_ACTION_NONE;
1869 } else if (rdev->pm.dynpm_planned_action == DYNPM_ACTION_NONE &&
1870 rdev->pm.dynpm_can_downclock) {
1871 rdev->pm.dynpm_planned_action =
1873 rdev->pm.dynpm_action_timeout = jiffies +
1881 if (rdev->pm.dynpm_planned_action != DYNPM_ACTION_NONE &&
1882 jiffies > rdev->pm.dynpm_action_timeout) {
1883 radeon_pm_get_dynpm_state(rdev);
1884 radeon_pm_set_clocks(rdev);
1887 schedule_delayed_work(&rdev->pm.dynpm_idle_work,
1890 mutex_unlock(&rdev->pm.mutex);
1891 ttm_bo_unlock_delayed_workqueue(&rdev->mman.bdev, resched);
1903 struct radeon_device *rdev = dev->dev_private;
1904 struct drm_device *ddev = rdev->ddev;
1906 if ((rdev->flags & RADEON_IS_PX) &&
1909 } else if (rdev->pm.dpm_enabled) {
1910 mutex_lock(&rdev->pm.mutex);
1911 if (rdev->asic->dpm.debugfs_print_current_performance_level)
1912 radeon_dpm_debugfs_print_current_performance_level(rdev, m);
1915 mutex_unlock(&rdev->pm.mutex);
1917 seq_printf(m, "default engine clock: %u0 kHz\n", rdev->pm.default_sclk);
1919 if ((rdev->family >= CHIP_PALM) && (rdev->flags & RADEON_IS_IGP))
1920 seq_printf(m, "current engine clock: %u0 kHz\n", rdev->pm.current_sclk);
1922 seq_printf(m, "current engine clock: %u0 kHz\n", radeon_get_engine_clock(rdev));
1923 seq_printf(m, "default memory clock: %u0 kHz\n", rdev->pm.default_mclk);
1924 if (rdev->asic->pm.get_memory_clock)
1925 seq_printf(m, "current memory clock: %u0 kHz\n", radeon_get_memory_clock(rdev));
1926 if (rdev->pm.current_vddc)
1927 seq_printf(m, "voltage: %u mV\n", rdev->pm.current_vddc);
1928 if (rdev->asic->pm.get_pcie_lanes)
1929 seq_printf(m, "PCIE lanes: %d\n", radeon_get_pcie_lanes(rdev));
1940 static int radeon_debugfs_pm_init(struct radeon_device *rdev)
1943 return radeon_debugfs_add_files(rdev, radeon_pm_info_list, ARRAY_SIZE(radeon_pm_info_list));