Lines Matching refs:rbo
101 void radeon_ttm_placement_from_domain(struct radeon_bo *rbo, u32 domain)
105 rbo->placement.placement = rbo->placements;
106 rbo->placement.busy_placement = rbo->placements;
111 if ((rbo->flags & RADEON_GEM_NO_CPU_ACCESS) &&
112 rbo->rdev->mc.visible_vram_size < rbo->rdev->mc.real_vram_size) {
113 rbo->placements[c].fpfn =
114 rbo->rdev->mc.visible_vram_size >> PAGE_SHIFT;
115 rbo->placements[c].mem_type = TTM_PL_VRAM;
116 rbo->placements[c++].flags = TTM_PL_FLAG_WC |
120 rbo->placements[c].fpfn = 0;
121 rbo->placements[c].mem_type = TTM_PL_VRAM;
122 rbo->placements[c++].flags = TTM_PL_FLAG_WC |
127 if (rbo->flags & RADEON_GEM_GTT_UC) {
128 rbo->placements[c].fpfn = 0;
129 rbo->placements[c].mem_type = TTM_PL_TT;
130 rbo->placements[c++].flags = TTM_PL_FLAG_UNCACHED;
132 } else if ((rbo->flags & RADEON_GEM_GTT_WC) ||
133 (rbo->rdev->flags & RADEON_IS_AGP)) {
134 rbo->placements[c].fpfn = 0;
135 rbo->placements[c].mem_type = TTM_PL_TT;
136 rbo->placements[c++].flags = TTM_PL_FLAG_WC |
139 rbo->placements[c].fpfn = 0;
140 rbo->placements[c].mem_type = TTM_PL_TT;
141 rbo->placements[c++].flags = TTM_PL_FLAG_CACHED;
146 if (rbo->flags & RADEON_GEM_GTT_UC) {
147 rbo->placements[c].fpfn = 0;
148 rbo->placements[c].mem_type = TTM_PL_SYSTEM;
149 rbo->placements[c++].flags = TTM_PL_FLAG_UNCACHED;
151 } else if ((rbo->flags & RADEON_GEM_GTT_WC) ||
152 rbo->rdev->flags & RADEON_IS_AGP) {
153 rbo->placements[c].fpfn = 0;
154 rbo->placements[c].mem_type = TTM_PL_SYSTEM;
155 rbo->placements[c++].flags = TTM_PL_FLAG_WC |
158 rbo->placements[c].fpfn = 0;
159 rbo->placements[c].mem_type = TTM_PL_SYSTEM;
160 rbo->placements[c++].flags = TTM_PL_FLAG_CACHED;
164 rbo->placements[c].fpfn = 0;
165 rbo->placements[c].mem_type = TTM_PL_SYSTEM;
166 rbo->placements[c++].flags = TTM_PL_MASK_CACHING;
169 rbo->placement.num_placement = c;
170 rbo->placement.num_busy_placement = c;
173 if ((rbo->flags & RADEON_GEM_CPU_ACCESS) &&
174 (rbo->placements[i].mem_type == TTM_PL_VRAM) &&
175 !rbo->placements[i].fpfn)
176 rbo->placements[i].lpfn =
177 rbo->rdev->mc.visible_vram_size >> PAGE_SHIFT;
179 rbo->placements[i].lpfn = 0;
780 struct radeon_bo *rbo;
785 rbo = container_of(bo, struct radeon_bo, tbo);
786 radeon_bo_check_tiling(rbo, 0, 1);
787 radeon_vm_bo_invalidate(rbo->rdev, rbo);
793 radeon_update_memory_usage(rbo, bo->mem.mem_type, -1);
794 radeon_update_memory_usage(rbo, new_mem->mem_type, 1);
801 struct radeon_bo *rbo;
807 rbo = container_of(bo, struct radeon_bo, tbo);
808 radeon_bo_check_tiling(rbo, 0, 0);
809 rdev = rbo->rdev;
819 if (rbo->pin_count > 0)
823 radeon_ttm_placement_from_domain(rbo, RADEON_GEM_DOMAIN_VRAM);
825 for (i = 0; i < rbo->placement.num_placement; i++) {
827 if ((rbo->placements[i].mem_type == TTM_PL_VRAM) &&
828 (!rbo->placements[i].lpfn || rbo->placements[i].lpfn > lpfn))
829 rbo->placements[i].lpfn = lpfn;
831 r = ttm_bo_validate(bo, &rbo->placement, &ctx);
833 radeon_ttm_placement_from_domain(rbo, RADEON_GEM_DOMAIN_GTT);
834 return ttm_bo_validate(bo, &rbo->placement, &ctx);