Lines Matching refs:bo
46 static void radeon_bo_clear_surface_reg(struct radeon_bo *bo);
53 static void radeon_update_memory_usage(struct radeon_bo *bo,
56 struct radeon_device *rdev = bo->rdev;
57 u64 size = (u64)bo->tbo.num_pages << PAGE_SHIFT;
77 struct radeon_bo *bo;
79 bo = container_of(tbo, struct radeon_bo, tbo);
81 radeon_update_memory_usage(bo, bo->tbo.mem.mem_type, -1);
83 mutex_lock(&bo->rdev->gem.mutex);
84 list_del_init(&bo->list);
85 mutex_unlock(&bo->rdev->gem.mutex);
86 radeon_bo_clear_surface_reg(bo);
87 WARN_ON_ONCE(!list_empty(&bo->va));
88 if (bo->tbo.base.import_attach)
89 drm_prime_gem_destroy(&bo->tbo.base, bo->tbo.sg);
90 drm_gem_object_release(&bo->tbo.base);
91 kfree(bo);
94 bool radeon_ttm_bo_is_radeon_bo(struct ttm_buffer_object *bo)
96 if (bo->destroy == &radeon_ttm_bo_destroy)
189 struct radeon_bo *bo;
209 bo = kzalloc(sizeof(struct radeon_bo), GFP_KERNEL);
210 if (bo == NULL)
212 drm_gem_private_object_init(rdev->ddev, &bo->tbo.base, size);
213 bo->rdev = rdev;
214 bo->surface_reg = -1;
215 INIT_LIST_HEAD(&bo->list);
216 INIT_LIST_HEAD(&bo->va);
217 bo->initial_domain = domain & (RADEON_GEM_DOMAIN_VRAM |
221 bo->flags = flags;
224 bo->flags &= ~(RADEON_GEM_GTT_WC | RADEON_GEM_GTT_UC);
230 bo->flags &= ~(RADEON_GEM_GTT_WC | RADEON_GEM_GTT_UC);
236 bo->flags &= ~(RADEON_GEM_GTT_WC | RADEON_GEM_GTT_UC);
247 if (bo->flags & RADEON_GEM_GTT_WC)
250 bo->flags &= ~(RADEON_GEM_GTT_WC | RADEON_GEM_GTT_UC);
256 bo->flags &= ~RADEON_GEM_GTT_WC;
259 radeon_ttm_placement_from_domain(bo, domain);
262 r = ttm_bo_init(&rdev->mman.bdev, &bo->tbo, size, type,
263 &bo->placement, page_align, !kernel, acc_size,
269 *bo_ptr = bo;
271 trace_radeon_bo_create(bo);
276 int radeon_bo_kmap(struct radeon_bo *bo, void **ptr)
281 if (bo->kptr) {
283 *ptr = bo->kptr;
287 r = ttm_bo_kmap(&bo->tbo, 0, bo->tbo.num_pages, &bo->kmap);
291 bo->kptr = ttm_kmap_obj_virtual(&bo->kmap, &is_iomem);
293 *ptr = bo->kptr;
295 radeon_bo_check_tiling(bo, 0, 0);
299 void radeon_bo_kunmap(struct radeon_bo *bo)
301 if (bo->kptr == NULL)
303 bo->kptr = NULL;
304 radeon_bo_check_tiling(bo, 0, 0);
305 ttm_bo_kunmap(&bo->kmap);
308 struct radeon_bo *radeon_bo_ref(struct radeon_bo *bo)
310 if (bo == NULL)
313 ttm_bo_get(&bo->tbo);
314 return bo;
317 void radeon_bo_unref(struct radeon_bo **bo)
321 if ((*bo) == NULL)
323 tbo = &((*bo)->tbo);
325 *bo = NULL;
328 int radeon_bo_pin_restricted(struct radeon_bo *bo, u32 domain, u64 max_offset,
334 if (radeon_ttm_tt_has_userptr(bo->rdev, bo->tbo.ttm))
337 if (bo->pin_count) {
338 bo->pin_count++;
340 *gpu_addr = radeon_bo_gpu_offset(bo);
346 domain_start = bo->rdev->mc.vram_start;
348 domain_start = bo->rdev->mc.gtt_start;
350 (radeon_bo_gpu_offset(bo) - domain_start));
355 if (bo->prime_shared_count && domain == RADEON_GEM_DOMAIN_VRAM) {
360 radeon_ttm_placement_from_domain(bo, domain);
361 for (i = 0; i < bo->placement.num_placement; i++) {
363 if ((bo->placements[i].mem_type == TTM_PL_VRAM) &&
364 !(bo->flags & RADEON_GEM_NO_CPU_ACCESS) &&
365 (!max_offset || max_offset > bo->rdev->mc.visible_vram_size))
366 bo->placements[i].lpfn =
367 bo->rdev->mc.visible_vram_size >> PAGE_SHIFT;
369 bo->placements[i].lpfn = max_offset >> PAGE_SHIFT;
371 bo->placements[i].flags |= TTM_PL_FLAG_NO_EVICT;
374 r = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx);
376 bo->pin_count = 1;
378 *gpu_addr = radeon_bo_gpu_offset(bo);
380 bo->rdev->vram_pin_size += radeon_bo_size(bo);
382 bo->rdev->gart_pin_size += radeon_bo_size(bo);
384 dev_err(bo->rdev->dev, "%p pin failed\n", bo);
389 int radeon_bo_pin(struct radeon_bo *bo, u32 domain, u64 *gpu_addr)
391 return radeon_bo_pin_restricted(bo, domain, 0, gpu_addr);
394 int radeon_bo_unpin(struct radeon_bo *bo)
399 if (!bo->pin_count) {
400 dev_warn(bo->rdev->dev, "%p unpin not necessary\n", bo);
403 bo->pin_count--;
404 if (bo->pin_count)
406 for (i = 0; i < bo->placement.num_placement; i++) {
407 bo->placements[i].lpfn = 0;
408 bo->placements[i].flags &= ~TTM_PL_FLAG_NO_EVICT;
410 r = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx);
412 if (bo->tbo.mem.mem_type == TTM_PL_VRAM)
413 bo->rdev->vram_pin_size -= radeon_bo_size(bo);
415 bo->rdev->gart_pin_size -= radeon_bo_size(bo);
417 dev_err(bo->rdev->dev, "%p validate failed for unpin\n", bo);
437 struct radeon_bo *bo, *n;
443 list_for_each_entry_safe(bo, n, &rdev->gem.objects, list) {
445 &bo->tbo.base, bo, (unsigned long)bo->tbo.base.size,
446 *((unsigned long *)&bo->tbo.base.refcount));
447 mutex_lock(&bo->rdev->gem.mutex);
448 list_del_init(&bo->list);
449 mutex_unlock(&bo->rdev->gem.mutex);
450 /* this should unref the ttm bo */
451 drm_gem_object_put(&bo->tbo.base);
551 struct radeon_bo *bo = lobj->robj;
552 if (!bo->pin_count) {
556 radeon_mem_type_to_domain(bo->tbo.mem.mem_type);
562 * any size, because it doesn't take the current "bo"
574 radeon_ttm_placement_from_domain(bo, domain);
576 radeon_uvd_force_into_uvd_segment(bo, allowed);
579 r = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx);
593 lobj->gpu_offset = radeon_bo_gpu_offset(bo);
594 lobj->tiling_flags = bo->tiling_flags;
605 int radeon_bo_get_surface_reg(struct radeon_bo *bo)
607 struct radeon_device *rdev = bo->rdev;
613 dma_resv_assert_held(bo->tbo.base.resv);
615 if (!bo->tiling_flags)
618 if (bo->surface_reg >= 0) {
619 reg = &rdev->surface_regs[bo->surface_reg];
620 i = bo->surface_reg;
628 if (!reg->bo)
631 old_object = reg->bo;
642 old_object = reg->bo;
650 bo->surface_reg = i;
651 reg->bo = bo;
654 radeon_set_surface_reg(rdev, i, bo->tiling_flags, bo->pitch,
655 bo->tbo.mem.start << PAGE_SHIFT,
656 bo->tbo.num_pages << PAGE_SHIFT);
660 static void radeon_bo_clear_surface_reg(struct radeon_bo *bo)
662 struct radeon_device *rdev = bo->rdev;
665 if (bo->surface_reg == -1)
668 reg = &rdev->surface_regs[bo->surface_reg];
669 radeon_clear_surface_reg(rdev, bo->surface_reg);
671 reg->bo = NULL;
672 bo->surface_reg = -1;
675 int radeon_bo_set_tiling_flags(struct radeon_bo *bo,
678 struct radeon_device *rdev = bo->rdev;
726 r = radeon_bo_reserve(bo, false);
729 bo->tiling_flags = tiling_flags;
730 bo->pitch = pitch;
731 radeon_bo_unreserve(bo);
735 void radeon_bo_get_tiling_flags(struct radeon_bo *bo,
739 dma_resv_assert_held(bo->tbo.base.resv);
742 *tiling_flags = bo->tiling_flags;
744 *pitch = bo->pitch;
747 int radeon_bo_check_tiling(struct radeon_bo *bo, bool has_moved,
751 dma_resv_assert_held(bo->tbo.base.resv);
753 if (!(bo->tiling_flags & RADEON_TILING_SURFACE))
757 radeon_bo_clear_surface_reg(bo);
761 if (bo->tbo.mem.mem_type != TTM_PL_VRAM) {
765 if (bo->surface_reg >= 0)
766 radeon_bo_clear_surface_reg(bo);
770 if ((bo->surface_reg >= 0) && !has_moved)
773 return radeon_bo_get_surface_reg(bo);
776 void radeon_bo_move_notify(struct ttm_buffer_object *bo,
782 if (!radeon_ttm_bo_is_radeon_bo(bo))
785 rbo = container_of(bo, struct radeon_bo, tbo);
793 radeon_update_memory_usage(rbo, bo->mem.mem_type, -1);
797 int radeon_bo_fault_reserve_notify(struct ttm_buffer_object *bo)
805 if (!radeon_ttm_bo_is_radeon_bo(bo))
807 rbo = container_of(bo, struct radeon_bo, tbo);
810 if (bo->mem.mem_type != TTM_PL_VRAM)
813 size = bo->mem.num_pages << PAGE_SHIFT;
814 offset = bo->mem.start << PAGE_SHIFT;
831 r = ttm_bo_validate(bo, &rbo->placement, &ctx);
834 return ttm_bo_validate(bo, &rbo->placement, &ctx);
839 offset = bo->mem.start << PAGE_SHIFT;
847 int radeon_bo_wait(struct radeon_bo *bo, u32 *mem_type, bool no_wait)
851 r = ttm_bo_reserve(&bo->tbo, true, no_wait, NULL);
855 *mem_type = bo->tbo.mem.mem_type;
857 r = ttm_bo_wait(&bo->tbo, true, no_wait);
858 ttm_bo_unreserve(&bo->tbo);
865 * @bo: buffer object in question
870 void radeon_bo_fence(struct radeon_bo *bo, struct radeon_fence *fence,
873 struct dma_resv *resv = bo->tbo.base.resv;