Lines Matching defs:value
184 * @value: value
191 uint32_t *value)
196 if (*value == 1) {
200 } else if (*value == 0) {
205 *value = *owner == applier ? 1 : 0;
229 uint32_t *value, value_tmp, *value_ptr, value_size;
234 value_ptr = (uint32_t *)((unsigned long)info->value);
235 value = &value_tmp;
240 *value = dev->pdev->device;
243 *value = rdev->num_gb_pipes;
246 *value = rdev->num_z_pipes;
251 *value = false;
253 *value = rdev->accel_working;
256 if (copy_from_user(value, value_ptr, sizeof(uint32_t))) {
262 if (crtc && crtc->base.id == *value) {
264 *value = radeon_crtc->crtc_id;
270 DRM_DEBUG_KMS("unknown crtc id %d\n", *value);
278 *value = 3;
280 *value = 2;
282 *value = 0;
285 *value = rdev->accel_working;
290 *value = rdev->config.cik.tile_config;
292 *value = rdev->config.si.tile_config;
294 *value = rdev->config.cayman.tile_config;
296 *value = rdev->config.evergreen.tile_config;
298 *value = rdev->config.rv770.tile_config;
300 *value = rdev->config.r600.tile_config;
307 /* The "value" here is both an input and output parameter.
308 * If the input value is 1, filp requests hyper-z access.
309 * If the input value is 0, filp revokes its hyper-z access.
311 * When returning, the value is 1 if filp owns hyper-z access,
313 if (copy_from_user(value, value_ptr, sizeof(uint32_t))) {
317 if (*value >= 2) {
318 DRM_DEBUG_KMS("WANT_HYPERZ: invalid value %d\n", *value);
321 radeon_set_filp_rights(dev, &rdev->hyperz_filp, filp, value);
325 if (copy_from_user(value, value_ptr, sizeof(uint32_t))) {
329 if (*value >= 2) {
330 DRM_DEBUG_KMS("WANT_CMASK: invalid value %d\n", *value);
333 radeon_set_filp_rights(dev, &rdev->cmask_filp, filp, value);
336 /* return clock value in KHz */
338 *value = radeon_get_xclk(rdev) * 10;
340 *value = rdev->clock.spll.reference_freq * 10;
344 *value = rdev->config.cik.max_backends_per_se *
347 *value = rdev->config.si.max_backends_per_se *
350 *value = rdev->config.cayman.max_backends_per_se *
353 *value = rdev->config.evergreen.max_backends;
355 *value = rdev->config.rv770.max_backends;
357 *value = rdev->config.r600.max_backends;
364 *value = rdev->config.cik.max_tile_pipes;
366 *value = rdev->config.si.max_tile_pipes;
368 *value = rdev->config.cayman.max_tile_pipes;
370 *value = rdev->config.evergreen.max_tile_pipes;
372 *value = rdev->config.rv770.max_tile_pipes;
374 *value = rdev->config.r600.max_tile_pipes;
380 *value = 1;
384 *value = rdev->config.cik.backend_map;
386 *value = rdev->config.si.backend_map;
388 *value = rdev->config.cayman.backend_map;
390 *value = rdev->config.evergreen.backend_map;
392 *value = rdev->config.rv770.backend_map;
394 *value = rdev->config.r600.backend_map;
403 *value = RADEON_VA_RESERVED_SIZE;
409 *value = RADEON_IB_VM_MAX_SIZE;
413 *value = rdev->config.cik.max_cu_per_sh;
415 *value = rdev->config.si.max_cu_per_sh;
417 *value = rdev->config.cayman.max_pipes_per_simd;
419 *value = rdev->config.evergreen.max_pipes;
421 *value = rdev->config.rv770.max_pipes;
423 *value = rdev->config.r600.max_pipes;
433 value = (uint32_t*)&value64;
439 *value = rdev->config.cik.max_shader_engines;
441 *value = rdev->config.si.max_shader_engines;
443 *value = rdev->config.cayman.max_shader_engines;
445 *value = rdev->config.evergreen.num_ses;
447 *value = 1;
451 *value = rdev->config.cik.max_sh_per_se;
453 *value = rdev->config.si.max_sh_per_se;
458 *value = rdev->fastfb_working;
461 if (copy_from_user(value, value_ptr, sizeof(uint32_t))) {
465 switch (*value) {
468 *value = rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready;
471 *value = rdev->ring[R600_RING_TYPE_DMA_INDEX].ready;
472 *value |= rdev->ring[CAYMAN_RING_TYPE_DMA1_INDEX].ready;
475 *value = rdev->ring[R600_RING_TYPE_UVD_INDEX].ready;
478 *value = rdev->ring[TN_RING_TYPE_VCE1_INDEX].ready;
486 value = rdev->config.cik.tile_mode_array;
489 value = rdev->config.si.tile_mode_array;
498 value = rdev->config.cik.macrotile_mode_array;
506 *value = 1;
510 *value = rdev->config.cik.backend_enable_mask;
512 *value = rdev->config.si.backend_enable_mask;
521 *value = rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.sclk * 10;
523 *value = rdev->pm.default_sclk * 10;
526 *value = rdev->vce.fw_version;
529 *value = rdev->vce.fb_version;
532 value = (uint32_t*)&value64;
537 value = (uint32_t*)&value64;
542 value = (uint32_t*)&value64;
548 *value = rdev->config.cik.active_cus;
550 *value = rdev->config.si.active_cus;
552 *value = rdev->config.cayman.active_simds;
554 *value = rdev->config.evergreen.active_simds;
556 *value = rdev->config.rv770.active_simds;
558 *value = rdev->config.r600.active_simds;
560 *value = 1;
565 *value = radeon_get_temperature(rdev);
567 *value = 0;
572 *value = radeon_dpm_get_current_sclk(rdev) / 100;
574 *value = rdev->pm.current_sclk / 100;
579 *value = radeon_dpm_get_current_mclk(rdev) / 100;
581 *value = rdev->pm.current_mclk / 100;
584 if (copy_from_user(value, value_ptr, sizeof(uint32_t))) {
588 if (radeon_get_allowed_info_register(rdev, *value, value))
592 *value = true;
595 *value = atomic_read(&rdev->gpu_reset_counter);
601 if (copy_to_user(value_ptr, (char*)value, value_size)) {
816 /* Fallback to use value as is. */