Lines Matching defs:rdev
63 struct radeon_device *rdev = dev->dev_private;
65 if (rdev == NULL)
68 if (rdev->rmmio == NULL)
76 radeon_acpi_fini(rdev);
78 radeon_modeset_fini(rdev);
79 radeon_device_fini(rdev);
87 kfree(rdev);
106 struct radeon_device *rdev;
109 rdev = kzalloc(sizeof(struct radeon_device), GFP_KERNEL);
110 if (rdev == NULL) {
113 dev->dev_private = (void *)rdev;
136 r = radeon_device_init(rdev, dev, dev->pdev, flags);
146 r = radeon_modeset_init(rdev);
154 acpi_status = radeon_acpi_init(rdev);
193 struct radeon_device *rdev = dev->dev_private;
195 mutex_lock(&rdev->gem.mutex);
206 mutex_unlock(&rdev->gem.mutex);
215 * @rdev: radeon device pointer
226 struct radeon_device *rdev = dev->dev_private;
228 struct radeon_mode_info *minfo = &rdev->mode_info;
243 *value = rdev->num_gb_pipes;
246 *value = rdev->num_z_pipes;
250 if ((rdev->family >= CHIP_CEDAR) && (rdev->family <= CHIP_HEMLOCK))
253 *value = rdev->accel_working;
260 for (i = 0, found = 0; i < rdev->num_crtc; i++) {
275 if (rdev->family == CHIP_HAWAII) {
276 if (rdev->accel_working) {
277 if (rdev->new_fw)
285 *value = rdev->accel_working;
289 if (rdev->family >= CHIP_BONAIRE)
290 *value = rdev->config.cik.tile_config;
291 else if (rdev->family >= CHIP_TAHITI)
292 *value = rdev->config.si.tile_config;
293 else if (rdev->family >= CHIP_CAYMAN)
294 *value = rdev->config.cayman.tile_config;
295 else if (rdev->family >= CHIP_CEDAR)
296 *value = rdev->config.evergreen.tile_config;
297 else if (rdev->family >= CHIP_RV770)
298 *value = rdev->config.rv770.tile_config;
299 else if (rdev->family >= CHIP_R600)
300 *value = rdev->config.r600.tile_config;
321 radeon_set_filp_rights(dev, &rdev->hyperz_filp, filp, value);
333 radeon_set_filp_rights(dev, &rdev->cmask_filp, filp, value);
337 if (rdev->asic->get_xclk)
338 *value = radeon_get_xclk(rdev) * 10;
340 *value = rdev->clock.spll.reference_freq * 10;
343 if (rdev->family >= CHIP_BONAIRE)
344 *value = rdev->config.cik.max_backends_per_se *
345 rdev->config.cik.max_shader_engines;
346 else if (rdev->family >= CHIP_TAHITI)
347 *value = rdev->config.si.max_backends_per_se *
348 rdev->config.si.max_shader_engines;
349 else if (rdev->family >= CHIP_CAYMAN)
350 *value = rdev->config.cayman.max_backends_per_se *
351 rdev->config.cayman.max_shader_engines;
352 else if (rdev->family >= CHIP_CEDAR)
353 *value = rdev->config.evergreen.max_backends;
354 else if (rdev->family >= CHIP_RV770)
355 *value = rdev->config.rv770.max_backends;
356 else if (rdev->family >= CHIP_R600)
357 *value = rdev->config.r600.max_backends;
363 if (rdev->family >= CHIP_BONAIRE)
364 *value = rdev->config.cik.max_tile_pipes;
365 else if (rdev->family >= CHIP_TAHITI)
366 *value = rdev->config.si.max_tile_pipes;
367 else if (rdev->family >= CHIP_CAYMAN)
368 *value = rdev->config.cayman.max_tile_pipes;
369 else if (rdev->family >= CHIP_CEDAR)
370 *value = rdev->config.evergreen.max_tile_pipes;
371 else if (rdev->family >= CHIP_RV770)
372 *value = rdev->config.rv770.max_tile_pipes;
373 else if (rdev->family >= CHIP_R600)
374 *value = rdev->config.r600.max_tile_pipes;
383 if (rdev->family >= CHIP_BONAIRE)
384 *value = rdev->config.cik.backend_map;
385 else if (rdev->family >= CHIP_TAHITI)
386 *value = rdev->config.si.backend_map;
387 else if (rdev->family >= CHIP_CAYMAN)
388 *value = rdev->config.cayman.backend_map;
389 else if (rdev->family >= CHIP_CEDAR)
390 *value = rdev->config.evergreen.backend_map;
391 else if (rdev->family >= CHIP_RV770)
392 *value = rdev->config.rv770.backend_map;
393 else if (rdev->family >= CHIP_R600)
394 *value = rdev->config.r600.backend_map;
401 if (rdev->family < CHIP_CAYMAN)
407 if (rdev->family < CHIP_CAYMAN)
412 if (rdev->family >= CHIP_BONAIRE)
413 *value = rdev->config.cik.max_cu_per_sh;
414 else if (rdev->family >= CHIP_TAHITI)
415 *value = rdev->config.si.max_cu_per_sh;
416 else if (rdev->family >= CHIP_CAYMAN)
417 *value = rdev->config.cayman.max_pipes_per_simd;
418 else if (rdev->family >= CHIP_CEDAR)
419 *value = rdev->config.evergreen.max_pipes;
420 else if (rdev->family >= CHIP_RV770)
421 *value = rdev->config.rv770.max_pipes;
422 else if (rdev->family >= CHIP_R600)
423 *value = rdev->config.r600.max_pipes;
429 if (rdev->family < CHIP_R600) {
435 value64 = radeon_get_gpu_clock_counter(rdev);
438 if (rdev->family >= CHIP_BONAIRE)
439 *value = rdev->config.cik.max_shader_engines;
440 else if (rdev->family >= CHIP_TAHITI)
441 *value = rdev->config.si.max_shader_engines;
442 else if (rdev->family >= CHIP_CAYMAN)
443 *value = rdev->config.cayman.max_shader_engines;
444 else if (rdev->family >= CHIP_CEDAR)
445 *value = rdev->config.evergreen.num_ses;
450 if (rdev->family >= CHIP_BONAIRE)
451 *value = rdev->config.cik.max_sh_per_se;
452 else if (rdev->family >= CHIP_TAHITI)
453 *value = rdev->config.si.max_sh_per_se;
458 *value = rdev->fastfb_working;
468 *value = rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready;
471 *value = rdev->ring[R600_RING_TYPE_DMA_INDEX].ready;
472 *value |= rdev->ring[CAYMAN_RING_TYPE_DMA1_INDEX].ready;
475 *value = rdev->ring[R600_RING_TYPE_UVD_INDEX].ready;
478 *value = rdev->ring[TN_RING_TYPE_VCE1_INDEX].ready;
485 if (rdev->family >= CHIP_BONAIRE) {
486 value = rdev->config.cik.tile_mode_array;
488 } else if (rdev->family >= CHIP_TAHITI) {
489 value = rdev->config.si.tile_mode_array;
497 if (rdev->family >= CHIP_BONAIRE) {
498 value = rdev->config.cik.macrotile_mode_array;
509 if (rdev->family >= CHIP_BONAIRE) {
510 *value = rdev->config.cik.backend_enable_mask;
511 } else if (rdev->family >= CHIP_TAHITI) {
512 *value = rdev->config.si.backend_enable_mask;
519 if ((rdev->pm.pm_method == PM_METHOD_DPM) &&
520 rdev->pm.dpm_enabled)
521 *value = rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.sclk * 10;
523 *value = rdev->pm.default_sclk * 10;
526 *value = rdev->vce.fw_version;
529 *value = rdev->vce.fb_version;
534 value64 = atomic64_read(&rdev->num_bytes_moved);
539 value64 = atomic64_read(&rdev->vram_usage);
544 value64 = atomic64_read(&rdev->gtt_usage);
547 if (rdev->family >= CHIP_BONAIRE)
548 *value = rdev->config.cik.active_cus;
549 else if (rdev->family >= CHIP_TAHITI)
550 *value = rdev->config.si.active_cus;
551 else if (rdev->family >= CHIP_CAYMAN)
552 *value = rdev->config.cayman.active_simds;
553 else if (rdev->family >= CHIP_CEDAR)
554 *value = rdev->config.evergreen.active_simds;
555 else if (rdev->family >= CHIP_RV770)
556 *value = rdev->config.rv770.active_simds;
557 else if (rdev->family >= CHIP_R600)
558 *value = rdev->config.r600.active_simds;
564 if (rdev->asic->pm.get_temperature)
565 *value = radeon_get_temperature(rdev);
571 if (rdev->pm.dpm_enabled)
572 *value = radeon_dpm_get_current_sclk(rdev) / 100;
574 *value = rdev->pm.current_sclk / 100;
578 if (rdev->pm.dpm_enabled)
579 *value = radeon_dpm_get_current_mclk(rdev) / 100;
581 *value = rdev->pm.current_mclk / 100;
588 if (radeon_get_allowed_info_register(rdev, *value, value))
595 *value = atomic_read(&rdev->gpu_reset_counter);
636 struct radeon_device *rdev = dev->dev_private;
650 if (rdev->family >= CHIP_CAYMAN) {
658 if (rdev->accel_working) {
660 r = radeon_vm_init(rdev, vm);
664 r = radeon_bo_reserve(rdev->ring_tmp_bo.bo, false);
670 vm->ib_bo_va = radeon_vm_bo_add(rdev, vm,
671 rdev->ring_tmp_bo.bo);
677 r = radeon_vm_bo_set_addr(rdev, vm->ib_bo_va,
692 radeon_vm_fini(rdev, vm);
714 struct radeon_device *rdev = dev->dev_private;
718 mutex_lock(&rdev->gem.mutex);
719 if (rdev->hyperz_filp == file_priv)
720 rdev->hyperz_filp = NULL;
721 if (rdev->cmask_filp == file_priv)
722 rdev->cmask_filp = NULL;
723 mutex_unlock(&rdev->gem.mutex);
725 radeon_uvd_free_handles(rdev, file_priv);
726 radeon_vce_free_handles(rdev, file_priv);
729 if (rdev->family >= CHIP_CAYMAN && file_priv->driver_priv) {
734 if (rdev->accel_working) {
735 r = radeon_bo_reserve(rdev->ring_tmp_bo.bo, false);
738 radeon_vm_bo_rmv(rdev, vm->ib_bo_va);
739 radeon_bo_unreserve(rdev->ring_tmp_bo.bo);
741 radeon_vm_fini(rdev, vm);
768 struct radeon_device *rdev = dev->dev_private;
770 if (pipe >= rdev->num_crtc) {
783 if (rdev->mode_info.crtcs[pipe]) {
788 count = radeon_get_vblank_counter(rdev, pipe);
796 &rdev->mode_info.crtcs[pipe]->base.hwmode);
797 } while (count != radeon_get_vblank_counter(rdev, pipe));
817 count = radeon_get_vblank_counter(rdev, pipe);
836 struct radeon_device *rdev = dev->dev_private;
840 if (pipe >= rdev->num_crtc) {
845 spin_lock_irqsave(&rdev->irq.lock, irqflags);
846 rdev->irq.crtc_vblank_int[pipe] = true;
847 r = radeon_irq_set(rdev);
848 spin_unlock_irqrestore(&rdev->irq.lock, irqflags);
863 struct radeon_device *rdev = dev->dev_private;
866 if (pipe >= rdev->num_crtc) {
871 spin_lock_irqsave(&rdev->irq.lock, irqflags);
872 rdev->irq.crtc_vblank_int[pipe] = false;
873 radeon_irq_set(rdev);
874 spin_unlock_irqrestore(&rdev->irq.lock, irqflags);