Lines Matching defs:tmp
339 u32 tmp, reg;
354 tmp = RREG32(RADEON_BIOS_6_SCRATCH);
355 WREG32(RADEON_BIOS_6_SCRATCH, tmp | ATOM_S6_HW_I2C_BUSY_STATE);
482 tmp = RREG32(i2c_cntl_0);
483 if (tmp & RADEON_I2C_GO)
485 tmp = RREG32(i2c_cntl_0);
486 if (tmp & RADEON_I2C_DONE)
489 DRM_DEBUG("i2c write error 0x%08x\n", tmp);
490 WREG32(i2c_cntl_0, tmp | RADEON_I2C_ABORT);
514 tmp = RREG32(i2c_cntl_0);
515 if (tmp & RADEON_I2C_GO)
517 tmp = RREG32(i2c_cntl_0);
518 if (tmp & RADEON_I2C_DONE)
521 DRM_DEBUG("i2c read error 0x%08x\n", tmp);
522 WREG32(i2c_cntl_0, tmp | RADEON_I2C_ABORT);
542 tmp = RREG32(i2c_cntl_0);
543 if (tmp & RADEON_I2C_GO)
545 tmp = RREG32(i2c_cntl_0);
546 if (tmp & RADEON_I2C_DONE)
549 DRM_DEBUG("i2c write error 0x%08x\n", tmp);
550 WREG32(i2c_cntl_0, tmp | RADEON_I2C_ABORT);
568 tmp = RREG32(RADEON_BIOS_6_SCRATCH);
569 tmp &= ~ATOM_S6_HW_I2C_BUSY_STATE;
570 WREG32(RADEON_BIOS_6_SCRATCH, tmp);
591 u32 tmp, reg;
601 tmp = RREG32(rec->mask_clk_reg);
602 tmp &= ~rec->mask_clk_mask;
603 WREG32(rec->mask_clk_reg, tmp);
604 tmp = RREG32(rec->mask_clk_reg);
606 tmp = RREG32(rec->mask_data_reg);
607 tmp &= ~rec->mask_data_mask;
608 WREG32(rec->mask_data_reg, tmp);
609 tmp = RREG32(rec->mask_data_reg);
612 tmp = RREG32(rec->a_clk_reg);
613 tmp &= ~rec->a_clk_mask;
614 WREG32(rec->a_clk_reg, tmp);
615 tmp = RREG32(rec->a_clk_reg);
617 tmp = RREG32(rec->a_data_reg);
618 tmp &= ~rec->a_data_mask;
619 WREG32(rec->a_data_reg, tmp);
620 tmp = RREG32(rec->a_data_reg);
623 tmp = RREG32(rec->en_clk_reg);
624 tmp &= ~rec->en_clk_mask;
625 WREG32(rec->en_clk_reg, tmp);
626 tmp = RREG32(rec->en_clk_reg);
628 tmp = RREG32(rec->en_data_reg);
629 tmp &= ~rec->en_data_mask;
630 WREG32(rec->en_data_reg, tmp);
631 tmp = RREG32(rec->en_data_reg);
634 tmp = RREG32(RADEON_BIOS_6_SCRATCH);
635 WREG32(RADEON_BIOS_6_SCRATCH, tmp | ATOM_S6_HW_I2C_BUSY_STATE);
690 tmp = RREG32(AVIVO_DC_I2C_STATUS1);
691 if (tmp & AVIVO_DC_I2C_GO)
693 tmp = RREG32(AVIVO_DC_I2C_STATUS1);
694 if (tmp & AVIVO_DC_I2C_DONE)
697 DRM_DEBUG("i2c write error 0x%08x\n", tmp);
732 tmp = RREG32(AVIVO_DC_I2C_STATUS1);
733 if (tmp & AVIVO_DC_I2C_GO)
735 tmp = RREG32(AVIVO_DC_I2C_STATUS1);
736 if (tmp & AVIVO_DC_I2C_DONE)
739 DRM_DEBUG("i2c read error 0x%08x\n", tmp);
775 tmp = RREG32(AVIVO_DC_I2C_STATUS1);
776 if (tmp & AVIVO_DC_I2C_GO)
778 tmp = RREG32(AVIVO_DC_I2C_STATUS1);
779 if (tmp & AVIVO_DC_I2C_DONE)
782 DRM_DEBUG("i2c write error 0x%08x\n", tmp);
805 tmp = RREG32(RADEON_BIOS_6_SCRATCH);
806 tmp &= ~ATOM_S6_HW_I2C_BUSY_STATE;
807 WREG32(RADEON_BIOS_6_SCRATCH, tmp);