Lines Matching refs:args
226 struct drm_radeon_gem_info *args = data;
231 args->vram_size = (u64)man->size << PAGE_SHIFT;
232 args->vram_visible = rdev->mc.visible_vram_size;
233 args->vram_visible -= rdev->vram_pin_size;
234 args->gart_size = rdev->mc.gtt_size;
235 args->gart_size -= rdev->gart_pin_size;
260 struct drm_radeon_gem_create *args = data;
267 args->size = roundup(args->size, PAGE_SIZE);
268 r = radeon_gem_object_create(rdev, args->size, args->alignment,
269 args->initial_domain, args->flags,
284 args->handle = handle;
294 struct drm_radeon_gem_userptr *args = data;
300 args->addr = untagged_addr(args->addr);
302 if (offset_in_page(args->addr | args->size))
306 if (args->flags & ~(RADEON_GEM_USERPTR_READONLY |
311 if (args->flags & RADEON_GEM_USERPTR_READONLY) {
316 } else if (!(args->flags & RADEON_GEM_USERPTR_ANONONLY) ||
317 !(args->flags & RADEON_GEM_USERPTR_REGISTER)) {
327 r = radeon_gem_object_create(rdev, args->size, 0,
334 r = radeon_ttm_tt_set_userptr(rdev, bo->tbo.ttm, args->addr, args->flags);
338 if (args->flags & RADEON_GEM_USERPTR_REGISTER) {
339 r = radeon_mn_register(bo, args->addr);
344 if (args->flags & RADEON_GEM_USERPTR_VALIDATE) {
366 args->handle = handle;
386 struct drm_radeon_gem_set_domain *args = data;
395 gobj = drm_gem_object_lookup(filp, args->handle);
401 r = radeon_gem_set_domain(gobj, args->read_domains, args->write_domain);
433 struct drm_radeon_gem_mmap *args = data;
435 return radeon_mode_dumb_mmap(filp, dev, args->handle, &args->addr_ptr);
441 struct drm_radeon_gem_busy *args = data;
447 gobj = drm_gem_object_lookup(filp, args->handle);
460 args->domain = radeon_mem_type_to_domain(cur_placement);
469 struct drm_radeon_gem_wait_idle *args = data;
476 gobj = drm_gem_object_lookup(filp, args->handle);
501 struct drm_radeon_gem_set_tiling *args = data;
506 DRM_DEBUG("%d \n", args->handle);
507 gobj = drm_gem_object_lookup(filp, args->handle);
511 r = radeon_bo_set_tiling_flags(robj, args->tiling_flags, args->pitch);
519 struct drm_radeon_gem_get_tiling *args = data;
525 gobj = drm_gem_object_lookup(filp, args->handle);
532 radeon_bo_get_tiling_flags(rbo, &args->tiling_flags, &args->pitch);
604 struct drm_radeon_gem_va *args = data;
614 args->operation = RADEON_VA_RESULT_ERROR;
623 if (args->vm_id) {
624 args->operation = RADEON_VA_RESULT_ERROR;
628 if (args->offset < RADEON_VA_RESERVED_SIZE) {
631 (unsigned long)args->offset,
633 args->operation = RADEON_VA_RESULT_ERROR;
642 if ((args->flags & invalid_flags)) {
644 args->flags, invalid_flags);
645 args->operation = RADEON_VA_RESULT_ERROR;
649 switch (args->operation) {
655 args->operation);
656 args->operation = RADEON_VA_RESULT_ERROR;
660 gobj = drm_gem_object_lookup(filp, args->handle);
662 args->operation = RADEON_VA_RESULT_ERROR;
668 args->operation = RADEON_VA_RESULT_ERROR;
674 args->operation = RADEON_VA_RESULT_ERROR;
680 switch (args->operation) {
683 args->operation = RADEON_VA_RESULT_VA_EXIST;
684 args->offset = bo_va->it.start * RADEON_GPU_PAGE_SIZE;
688 r = radeon_vm_bo_set_addr(rdev, bo_va, args->offset, args->flags);
698 args->operation = RADEON_VA_RESULT_OK;
700 args->operation = RADEON_VA_RESULT_ERROR;
710 struct drm_radeon_gem_op *args = data;
715 gobj = drm_gem_object_lookup(filp, args->handle);
729 switch (args->op) {
731 args->value = robj->initial_domain;
734 robj->initial_domain = args->value & (RADEON_GEM_DOMAIN_VRAM |
750 struct drm_mode_create_dumb *args)
757 args->pitch = radeon_align_pitch(rdev, args->width,
758 DIV_ROUND_UP(args->bpp, 8), 0);
759 args->size = args->pitch * args->height;
760 args->size = ALIGN(args->size, PAGE_SIZE);
762 r = radeon_gem_object_create(rdev, args->size, 0,
774 args->handle = handle;