Lines Matching defs:rdev
56 struct radeon_device *rdev = dev->dev_private;
94 struct radeon_device *rdev = dev->dev_private;
128 struct radeon_device *rdev = dev->dev_private;
187 if (ASIC_IS_DCE8(rdev)) {
200 struct radeon_device *rdev = dev->dev_private;
227 struct radeon_device *rdev = dev->dev_private;
232 if (ASIC_IS_DCE5(rdev))
234 else if (ASIC_IS_DCE4(rdev))
236 else if (ASIC_IS_AVIVO(rdev))
288 void radeon_crtc_handle_vblank(struct radeon_device *rdev, int crtc_id)
290 struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id];
308 if ((radeon_use_pflipirq == 2) && ASIC_IS_DCE4(rdev))
311 spin_lock_irqsave(&rdev->ddev->event_lock, flags);
317 spin_unlock_irqrestore(&rdev->ddev->event_lock, flags);
321 update_pending = radeon_page_flip_pending(rdev, crtc_id);
343 radeon_get_crtc_scanoutpos(rdev->ddev, crtc_id,
346 &rdev->mode_info.crtcs[crtc_id]->base.hwmode)) &&
347 ((vpos >= 0 && hpos < 0) || (hpos >= 0 && !ASIC_IS_AVIVO(rdev)))) {
356 spin_unlock_irqrestore(&rdev->ddev->event_lock, flags);
358 radeon_crtc_handle_flip(rdev, crtc_id);
364 * @rdev: radeon device pointer
369 void radeon_crtc_handle_flip(struct radeon_device *rdev, int crtc_id)
371 struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id];
379 spin_lock_irqsave(&rdev->ddev->event_lock, flags);
386 spin_unlock_irqrestore(&rdev->ddev->event_lock, flags);
398 spin_unlock_irqrestore(&rdev->ddev->event_lock, flags);
401 radeon_irq_kms_pflip_irq_put(rdev, work->crtc_id);
416 struct radeon_device *rdev = work->rdev;
417 struct drm_device *dev = rdev->ddev;
418 struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[work->crtc_id];
425 down_read(&rdev->exclusive_lock);
430 if (fence && fence->rdev == rdev) {
433 up_read(&rdev->exclusive_lock);
435 r = radeon_gpu_reset(rdev);
437 down_read(&rdev->exclusive_lock);
465 (!ASIC_IS_AVIVO(rdev) ||
474 radeon_irq_kms_pflip_irq_get(rdev, radeon_crtc->crtc_id);
477 radeon_page_flip(rdev, radeon_crtc->crtc_id, work->base, work->async);
481 up_read(&rdev->exclusive_lock);
492 struct radeon_device *rdev = dev->dev_private;
509 work->rdev = rdev;
535 ASIC_IS_AVIVO(rdev) ? 0 : 1 << 27, &base);
546 if (!ASIC_IS_AVIVO(rdev)) {
552 if (ASIC_IS_R300(rdev)) {
627 struct radeon_device *rdev;
651 rdev = dev->dev_private;
654 if (active && !rdev->have_disp_power_ref) {
655 rdev->have_disp_power_ref = true;
660 if (!active && rdev->have_disp_power_ref) {
662 rdev->have_disp_power_ref = false;
685 struct radeon_device *rdev = dev->dev_private;
702 rdev->mode_info.crtcs[index] = radeon_crtc;
704 if (rdev->family >= CHIP_BONAIRE) {
720 if (rdev->is_atom_bios && (ASIC_IS_AVIVO(rdev) || radeon_r4xx_atom))
854 struct radeon_device *rdev = dev->dev_private;
857 if (rdev->bios) {
858 if (rdev->is_atom_bios) {
868 if (!ASIC_IS_AVIVO(rdev))
1408 static int radeon_modeset_create_props(struct radeon_device *rdev)
1412 if (rdev->is_atom_bios) {
1413 rdev->mode_info.coherent_mode_property =
1414 drm_property_create_range(rdev->ddev, 0 , "coherent", 0, 1);
1415 if (!rdev->mode_info.coherent_mode_property)
1419 if (!ASIC_IS_AVIVO(rdev)) {
1421 rdev->mode_info.tmds_pll_property =
1422 drm_property_create_enum(rdev->ddev, 0,
1427 rdev->mode_info.load_detect_property =
1428 drm_property_create_range(rdev->ddev, 0, "load detection", 0, 1);
1429 if (!rdev->mode_info.load_detect_property)
1432 drm_mode_create_scaling_mode_property(rdev->ddev);
1435 rdev->mode_info.tv_std_property =
1436 drm_property_create_enum(rdev->ddev, 0,
1441 rdev->mode_info.underscan_property =
1442 drm_property_create_enum(rdev->ddev, 0,
1446 rdev->mode_info.underscan_hborder_property =
1447 drm_property_create_range(rdev->ddev, 0,
1449 if (!rdev->mode_info.underscan_hborder_property)
1452 rdev->mode_info.underscan_vborder_property =
1453 drm_property_create_range(rdev->ddev, 0,
1455 if (!rdev->mode_info.underscan_vborder_property)
1459 rdev->mode_info.audio_property =
1460 drm_property_create_enum(rdev->ddev, 0,
1465 rdev->mode_info.dither_property =
1466 drm_property_create_enum(rdev->ddev, 0,
1471 rdev->mode_info.output_csc_property =
1472 drm_property_create_enum(rdev->ddev, 0,
1479 void radeon_update_display_priority(struct radeon_device *rdev)
1489 if ((ASIC_IS_R300(rdev) || (rdev->family == CHIP_RV515)) &&
1490 !(rdev->flags & RADEON_IS_IGP))
1491 rdev->disp_priority = 2;
1493 rdev->disp_priority = 0;
1495 rdev->disp_priority = radeon_disp_priority;
1502 static void radeon_afmt_init(struct radeon_device *rdev)
1507 rdev->mode_info.afmt[i] = NULL;
1509 if (ASIC_IS_NODCE(rdev)) {
1511 } else if (ASIC_IS_DCE4(rdev)) {
1527 if (ASIC_IS_DCE8(rdev))
1529 else if (ASIC_IS_DCE6(rdev))
1531 else if (ASIC_IS_DCE5(rdev))
1533 else if (ASIC_IS_DCE41(rdev))
1540 rdev->mode_info.afmt[i] = kzalloc(sizeof(struct radeon_afmt), GFP_KERNEL);
1541 if (rdev->mode_info.afmt[i]) {
1542 rdev->mode_info.afmt[i]->offset = eg_offsets[i];
1543 rdev->mode_info.afmt[i]->id = i;
1546 } else if (ASIC_IS_DCE3(rdev)) {
1548 rdev->mode_info.afmt[0] = kzalloc(sizeof(struct radeon_afmt), GFP_KERNEL);
1549 if (rdev->mode_info.afmt[0]) {
1550 rdev->mode_info.afmt[0]->offset = DCE3_HDMI_OFFSET0;
1551 rdev->mode_info.afmt[0]->id = 0;
1553 rdev->mode_info.afmt[1] = kzalloc(sizeof(struct radeon_afmt), GFP_KERNEL);
1554 if (rdev->mode_info.afmt[1]) {
1555 rdev->mode_info.afmt[1]->offset = DCE3_HDMI_OFFSET1;
1556 rdev->mode_info.afmt[1]->id = 1;
1558 } else if (ASIC_IS_DCE2(rdev)) {
1560 rdev->mode_info.afmt[0] = kzalloc(sizeof(struct radeon_afmt), GFP_KERNEL);
1561 if (rdev->mode_info.afmt[0]) {
1562 rdev->mode_info.afmt[0]->offset = DCE2_HDMI_OFFSET0;
1563 rdev->mode_info.afmt[0]->id = 0;
1566 if (rdev->family >= CHIP_R600) {
1567 rdev->mode_info.afmt[1] = kzalloc(sizeof(struct radeon_afmt), GFP_KERNEL);
1568 if (rdev->mode_info.afmt[1]) {
1569 rdev->mode_info.afmt[1]->offset = DCE2_HDMI_OFFSET1;
1570 rdev->mode_info.afmt[1]->id = 1;
1576 static void radeon_afmt_fini(struct radeon_device *rdev)
1581 kfree(rdev->mode_info.afmt[i]);
1582 rdev->mode_info.afmt[i] = NULL;
1586 int radeon_modeset_init(struct radeon_device *rdev)
1591 drm_mode_config_init(rdev->ddev);
1592 rdev->mode_info.mode_config_initialized = true;
1594 rdev->ddev->mode_config.funcs = &radeon_mode_funcs;
1596 if (radeon_use_pflipirq == 2 && rdev->family >= CHIP_R600)
1597 rdev->ddev->mode_config.async_page_flip = true;
1599 if (ASIC_IS_DCE5(rdev)) {
1600 rdev->ddev->mode_config.max_width = 16384;
1601 rdev->ddev->mode_config.max_height = 16384;
1602 } else if (ASIC_IS_AVIVO(rdev)) {
1603 rdev->ddev->mode_config.max_width = 8192;
1604 rdev->ddev->mode_config.max_height = 8192;
1606 rdev->ddev->mode_config.max_width = 4096;
1607 rdev->ddev->mode_config.max_height = 4096;
1610 rdev->ddev->mode_config.preferred_depth = 24;
1611 rdev->ddev->mode_config.prefer_shadow = 1;
1613 rdev->ddev->mode_config.fb_base = rdev->mc.aper_base;
1615 ret = radeon_modeset_create_props(rdev);
1621 radeon_i2c_init(rdev);
1624 if (!rdev->is_atom_bios) {
1626 radeon_combios_check_hardcoded_edid(rdev);
1630 for (i = 0; i < rdev->num_crtc; i++) {
1631 radeon_crtc_init(rdev->ddev, i);
1635 ret = radeon_setup_enc_conn(rdev->ddev);
1641 if (rdev->is_atom_bios) {
1642 radeon_atom_encoder_init(rdev);
1643 radeon_atom_disp_eng_pll_init(rdev);
1647 radeon_hpd_init(rdev);
1650 radeon_afmt_init(rdev);
1652 radeon_fbdev_init(rdev);
1653 drm_kms_helper_poll_init(rdev->ddev);
1656 ret = radeon_pm_late_init(rdev);
1661 void radeon_modeset_fini(struct radeon_device *rdev)
1663 if (rdev->mode_info.mode_config_initialized) {
1664 drm_kms_helper_poll_fini(rdev->ddev);
1665 radeon_hpd_fini(rdev);
1666 drm_helper_force_disable_all(rdev->ddev);
1667 radeon_fbdev_fini(rdev);
1668 radeon_afmt_fini(rdev);
1669 drm_mode_config_cleanup(rdev->ddev);
1670 rdev->mode_info.mode_config_initialized = false;
1673 kfree(rdev->mode_info.bios_hardcoded_edid);
1676 radeon_i2c_fini(rdev);
1696 struct radeon_device *rdev = dev->dev_private;
1733 if (ASIC_IS_AVIVO(rdev) &&
1828 struct radeon_device *rdev = dev->dev_private;
1836 if (ASIC_IS_DCE4(rdev)) {
1879 } else if (ASIC_IS_AVIVO(rdev)) {
1958 vbl_start -= rdev->mode_info.crtcs[pipe]->lb_vblank_lead_lines;