Lines Matching refs:rdev
159 struct radeon_device *rdev = dev->dev_private;
161 if (rdev->flags & RADEON_IS_PX)
166 static void radeon_device_handle_px_quirks(struct radeon_device *rdev)
172 if (rdev->pdev->vendor == p->chip_vendor &&
173 rdev->pdev->device == p->chip_device &&
174 rdev->pdev->subsystem_vendor == p->subsys_vendor &&
175 rdev->pdev->subsystem_device == p->subsys_device) {
176 rdev->px_quirk_flags = p->px_quirk_flags;
182 if (rdev->px_quirk_flags & RADEON_PX_QUIRK_DISABLE_PX)
183 rdev->flags &= ~RADEON_IS_PX;
188 rdev->flags &= ~RADEON_IS_PX;
194 * @rdev: radeon_device pointer
201 void radeon_program_register_sequence(struct radeon_device *rdev,
227 void radeon_pci_config_reset(struct radeon_device *rdev)
229 pci_write_config_dword(rdev->pdev, 0x7c, RADEON_ASIC_RESET_DATA);
235 * @rdev: radeon_device pointer
239 void radeon_surface_init(struct radeon_device *rdev)
242 if (rdev->family < CHIP_R600) {
246 if (rdev->surface_regs[i].bo)
247 radeon_bo_get_surface_reg(rdev->surface_regs[i].bo);
249 radeon_clear_surface_reg(rdev, i);
262 * @rdev: radeon_device pointer
266 void radeon_scratch_init(struct radeon_device *rdev)
271 if (rdev->family < CHIP_R300) {
272 rdev->scratch.num_reg = 5;
274 rdev->scratch.num_reg = 7;
276 rdev->scratch.reg_base = RADEON_SCRATCH_REG0;
277 for (i = 0; i < rdev->scratch.num_reg; i++) {
278 rdev->scratch.free[i] = true;
279 rdev->scratch.reg[i] = rdev->scratch.reg_base + (i * 4);
286 * @rdev: radeon_device pointer
292 int radeon_scratch_get(struct radeon_device *rdev, uint32_t *reg)
296 for (i = 0; i < rdev->scratch.num_reg; i++) {
297 if (rdev->scratch.free[i]) {
298 rdev->scratch.free[i] = false;
299 *reg = rdev->scratch.reg[i];
309 * @rdev: radeon_device pointer
314 void radeon_scratch_free(struct radeon_device *rdev, uint32_t reg)
318 for (i = 0; i < rdev->scratch.num_reg; i++) {
319 if (rdev->scratch.reg[i] == reg) {
320 rdev->scratch.free[i] = true;
332 * @rdev: radeon_device pointer
337 static int radeon_doorbell_init(struct radeon_device *rdev)
340 rdev->doorbell.base = pci_resource_start(rdev->pdev, 2);
341 rdev->doorbell.size = pci_resource_len(rdev->pdev, 2);
343 rdev->doorbell.num_doorbells = min_t(u32, rdev->doorbell.size / sizeof(u32), RADEON_MAX_DOORBELLS);
344 if (rdev->doorbell.num_doorbells == 0)
347 rdev->doorbell.ptr = ioremap(rdev->doorbell.base, rdev->doorbell.num_doorbells * sizeof(u32));
348 if (rdev->doorbell.ptr == NULL) {
351 DRM_INFO("doorbell mmio base: 0x%08X\n", (uint32_t)rdev->doorbell.base);
352 DRM_INFO("doorbell mmio size: %u\n", (unsigned)rdev->doorbell.size);
354 memset(&rdev->doorbell.used, 0, sizeof(rdev->doorbell.used));
362 * @rdev: radeon_device pointer
366 static void radeon_doorbell_fini(struct radeon_device *rdev)
368 iounmap(rdev->doorbell.ptr);
369 rdev->doorbell.ptr = NULL;
375 * @rdev: radeon_device pointer
381 int radeon_doorbell_get(struct radeon_device *rdev, u32 *doorbell)
383 unsigned long offset = find_first_zero_bit(rdev->doorbell.used, rdev->doorbell.num_doorbells);
384 if (offset < rdev->doorbell.num_doorbells) {
385 __set_bit(offset, rdev->doorbell.used);
396 * @rdev: radeon_device pointer
401 void radeon_doorbell_free(struct radeon_device *rdev, u32 doorbell)
403 if (doorbell < rdev->doorbell.num_doorbells)
404 __clear_bit(doorbell, rdev->doorbell.used);
417 * @rdev: radeon_device pointer
421 void radeon_wb_disable(struct radeon_device *rdev)
423 rdev->wb.enabled = false;
429 * @rdev: radeon_device pointer
434 void radeon_wb_fini(struct radeon_device *rdev)
436 radeon_wb_disable(rdev);
437 if (rdev->wb.wb_obj) {
438 if (!radeon_bo_reserve(rdev->wb.wb_obj, false)) {
439 radeon_bo_kunmap(rdev->wb.wb_obj);
440 radeon_bo_unpin(rdev->wb.wb_obj);
441 radeon_bo_unreserve(rdev->wb.wb_obj);
443 radeon_bo_unref(&rdev->wb.wb_obj);
444 rdev->wb.wb = NULL;
445 rdev->wb.wb_obj = NULL;
452 * @rdev: radeon_device pointer
458 int radeon_wb_init(struct radeon_device *rdev)
462 if (rdev->wb.wb_obj == NULL) {
463 r = radeon_bo_create(rdev, RADEON_GPU_PAGE_SIZE, PAGE_SIZE, true,
465 &rdev->wb.wb_obj);
467 dev_warn(rdev->dev, "(%d) create WB bo failed\n", r);
470 r = radeon_bo_reserve(rdev->wb.wb_obj, false);
472 radeon_wb_fini(rdev);
475 r = radeon_bo_pin(rdev->wb.wb_obj, RADEON_GEM_DOMAIN_GTT,
476 &rdev->wb.gpu_addr);
478 radeon_bo_unreserve(rdev->wb.wb_obj);
479 dev_warn(rdev->dev, "(%d) pin WB bo failed\n", r);
480 radeon_wb_fini(rdev);
483 r = radeon_bo_kmap(rdev->wb.wb_obj, (void **)&rdev->wb.wb);
484 radeon_bo_unreserve(rdev->wb.wb_obj);
486 dev_warn(rdev->dev, "(%d) map WB bo failed\n", r);
487 radeon_wb_fini(rdev);
493 memset((char *)rdev->wb.wb, 0, RADEON_GPU_PAGE_SIZE);
495 rdev->wb.use_event = false;
498 rdev->wb.enabled = false;
500 if (rdev->flags & RADEON_IS_AGP) {
502 rdev->wb.enabled = false;
503 } else if (rdev->family < CHIP_R300) {
505 rdev->wb.enabled = false;
507 rdev->wb.enabled = true;
509 if (rdev->family >= CHIP_R600) {
510 rdev->wb.use_event = true;
515 if (rdev->family >= CHIP_PALM) {
516 rdev->wb.enabled = true;
517 rdev->wb.use_event = true;
520 dev_info(rdev->dev, "WB %sabled\n", rdev->wb.enabled ? "en" : "dis");
527 * @rdev: radeon device structure holding all necessary informations
566 void radeon_vram_location(struct radeon_device *rdev, struct radeon_mc *mc, u64 base)
571 if (mc->mc_vram_size > (rdev->mc.mc_mask - base + 1)) {
572 dev_warn(rdev->dev, "limiting VRAM to PCI aperture size\n");
577 if (rdev->flags & RADEON_IS_AGP && mc->vram_end > mc->gtt_start && mc->vram_start <= mc->gtt_end) {
578 dev_warn(rdev->dev, "limiting VRAM to PCI aperture size\n");
585 dev_info(rdev->dev, "VRAM: %lluM 0x%016llX - 0x%016llX (%lluM used)\n",
592 * @rdev: radeon device structure holding all necessary informations
602 void radeon_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc)
606 size_af = ((rdev->mc.mc_mask - mc->vram_end) + mc->gtt_base_align) & ~mc->gtt_base_align;
610 dev_warn(rdev->dev, "limiting GTT\n");
616 dev_warn(rdev->dev, "limiting GTT\n");
622 dev_info(rdev->dev, "GTT: %lluM 0x%016llX - 0x%016llX\n",
649 * @rdev: radeon_device pointer
655 bool radeon_card_posted(struct radeon_device *rdev)
660 if (rdev->family >= CHIP_BONAIRE &&
666 (rdev->pdev->subsystem_vendor == PCI_VENDOR_ID_APPLE) &&
667 (rdev->family < CHIP_R600))
670 if (ASIC_IS_NODCE(rdev))
674 if (ASIC_IS_DCE4(rdev)) {
677 if (rdev->num_crtc >= 4) {
681 if (rdev->num_crtc >= 6) {
687 } else if (ASIC_IS_AVIVO(rdev)) {
703 if (rdev->family >= CHIP_R600)
718 * @rdev: radeon_device pointer
723 void radeon_update_bandwidth_info(struct radeon_device *rdev)
726 u32 sclk = rdev->pm.current_sclk;
727 u32 mclk = rdev->pm.current_mclk;
731 rdev->pm.sclk.full = dfixed_const(sclk);
732 rdev->pm.sclk.full = dfixed_div(rdev->pm.sclk, a);
733 rdev->pm.mclk.full = dfixed_const(mclk);
734 rdev->pm.mclk.full = dfixed_div(rdev->pm.mclk, a);
736 if (rdev->flags & RADEON_IS_IGP) {
739 rdev->pm.core_bandwidth.full = dfixed_div(rdev->pm.sclk, a);
746 * @rdev: radeon_device pointer
752 bool radeon_boot_test_post_card(struct radeon_device *rdev)
754 if (radeon_card_posted(rdev))
757 if (rdev->bios) {
759 if (rdev->is_atom_bios)
760 atom_asic_init(rdev->mode_info.atom_context);
762 radeon_combios_asic_init(rdev->ddev);
765 dev_err(rdev->dev, "Card not posted and no BIOS - ignoring\n");
773 * @rdev: radeon_device pointer
780 int radeon_dummy_page_init(struct radeon_device *rdev)
782 if (rdev->dummy_page.page)
784 rdev->dummy_page.page = alloc_page(GFP_DMA32 | GFP_KERNEL | __GFP_ZERO);
785 if (rdev->dummy_page.page == NULL)
787 rdev->dummy_page.addr = pci_map_page(rdev->pdev, rdev->dummy_page.page,
789 if (pci_dma_mapping_error(rdev->pdev, rdev->dummy_page.addr)) {
790 dev_err(&rdev->pdev->dev, "Failed to DMA MAP the dummy page\n");
791 __free_page(rdev->dummy_page.page);
792 rdev->dummy_page.page = NULL;
795 rdev->dummy_page.entry = radeon_gart_get_page_entry(rdev->dummy_page.addr,
803 * @rdev: radeon_device pointer
807 void radeon_dummy_page_fini(struct radeon_device *rdev)
809 if (rdev->dummy_page.page == NULL)
811 pci_unmap_page(rdev->pdev, rdev->dummy_page.addr,
813 __free_page(rdev->dummy_page.page);
814 rdev->dummy_page.page = NULL;
838 struct radeon_device *rdev = info->dev->dev_private;
841 r = rdev->pll_rreg(rdev, reg);
856 struct radeon_device *rdev = info->dev->dev_private;
858 rdev->pll_wreg(rdev, reg, val);
872 struct radeon_device *rdev = info->dev->dev_private;
875 r = rdev->mc_rreg(rdev, reg);
890 struct radeon_device *rdev = info->dev->dev_private;
892 rdev->mc_wreg(rdev, reg, val);
906 struct radeon_device *rdev = info->dev->dev_private;
922 struct radeon_device *rdev = info->dev->dev_private;
940 struct radeon_device *rdev = info->dev->dev_private;
956 struct radeon_device *rdev = info->dev->dev_private;
966 * @rdev: radeon_device pointer
973 int radeon_atombios_init(struct radeon_device *rdev)
981 rdev->mode_info.atom_card_info = atom_card_info;
982 atom_card_info->dev = rdev->ddev;
986 if (rdev->rio_mem) {
999 rdev->mode_info.atom_context = atom_parse(atom_card_info, rdev->bios);
1000 if (!rdev->mode_info.atom_context) {
1001 radeon_atombios_fini(rdev);
1005 mutex_init(&rdev->mode_info.atom_context->mutex);
1006 mutex_init(&rdev->mode_info.atom_context->scratch_mutex);
1007 radeon_atom_initialize_bios_scratch_regs(rdev->ddev);
1008 atom_allocate_fb_scratch(rdev->mode_info.atom_context);
1015 * @rdev: radeon_device pointer
1021 void radeon_atombios_fini(struct radeon_device *rdev)
1023 if (rdev->mode_info.atom_context) {
1024 kfree(rdev->mode_info.atom_context->scratch);
1025 kfree(rdev->mode_info.atom_context->iio);
1027 kfree(rdev->mode_info.atom_context);
1028 rdev->mode_info.atom_context = NULL;
1029 kfree(rdev->mode_info.atom_card_info);
1030 rdev->mode_info.atom_card_info = NULL;
1043 * @rdev: radeon_device pointer
1049 int radeon_combios_init(struct radeon_device *rdev)
1051 radeon_combios_initialize_bios_scratch_regs(rdev->ddev);
1058 * @rdev: radeon_device pointer
1063 void radeon_combios_fini(struct radeon_device *rdev)
1079 struct radeon_device *rdev = cookie;
1080 radeon_vga_set_state(rdev, state);
1120 * @rdev: radeon_device pointer
1125 static void radeon_check_arguments(struct radeon_device *rdev)
1129 dev_warn(rdev->dev, "vram limit (%d) must be a power of 2\n",
1135 radeon_gart_size = radeon_gart_size_auto(rdev->family);
1139 dev_warn(rdev->dev, "gart size (%d) too small\n",
1141 radeon_gart_size = radeon_gart_size_auto(rdev->family);
1143 dev_warn(rdev->dev, "gart size (%d) must be a power of 2\n",
1145 radeon_gart_size = radeon_gart_size_auto(rdev->family);
1147 rdev->mc.gtt_size = (uint64_t)radeon_gart_size << 20;
1159 dev_warn(rdev->dev, "invalid AGP mode %d (valid mode: "
1166 dev_warn(rdev->dev, "VM size (%d) must be a power of 2\n",
1172 dev_warn(rdev->dev, "VM size (%d) too small, min is 1GB\n",
1181 dev_warn(rdev->dev, "VM size (%d) too large, max is 1TB\n",
1202 dev_warn(rdev->dev, "VM page table size (%d) too small\n",
1209 dev_warn(rdev->dev, "VM page table size (%d) too large\n",
1279 * @rdev: radeon_device pointer
1288 int radeon_device_init(struct radeon_device *rdev,
1297 rdev->shutdown = false;
1298 rdev->dev = &pdev->dev;
1299 rdev->ddev = ddev;
1300 rdev->pdev = pdev;
1301 rdev->flags = flags;
1302 rdev->family = flags & RADEON_FAMILY_MASK;
1303 rdev->is_atom_bios = false;
1304 rdev->usec_timeout = RADEON_MAX_USEC_TIMEOUT;
1305 rdev->mc.gtt_size = 512 * 1024 * 1024;
1306 rdev->accel_working = false;
1309 rdev->ring[i].idx = i;
1311 rdev->fence_context = dma_fence_context_alloc(RADEON_NUM_RINGS);
1314 radeon_family_name[rdev->family], pdev->vendor, pdev->device,
1319 mutex_init(&rdev->ring_lock);
1320 mutex_init(&rdev->dc_hw_i2c_mutex);
1321 atomic_set(&rdev->ih.lock, 0);
1322 mutex_init(&rdev->gem.mutex);
1323 mutex_init(&rdev->pm.mutex);
1324 mutex_init(&rdev->gpu_clock_mutex);
1325 mutex_init(&rdev->srbm_mutex);
1326 init_rwsem(&rdev->pm.mclk_lock);
1327 init_rwsem(&rdev->exclusive_lock);
1328 init_waitqueue_head(&rdev->irq.vblank_queue);
1329 r = radeon_gem_init(rdev);
1333 radeon_check_arguments(rdev);
1337 rdev->vm_manager.max_pfn = radeon_vm_size << 18;
1340 r = radeon_asic_init(rdev);
1347 if ((rdev->family >= CHIP_RS400) &&
1348 (rdev->flags & RADEON_IS_IGP)) {
1349 rdev->flags &= ~RADEON_IS_AGP;
1352 if (rdev->flags & RADEON_IS_AGP && radeon_agpmode == -1) {
1353 radeon_agp_disable(rdev);
1360 if (rdev->family >= CHIP_CAYMAN)
1361 rdev->mc.mc_mask = 0xffffffffffULL; /* 40 bit MC */
1362 else if (rdev->family >= CHIP_CEDAR)
1363 rdev->mc.mc_mask = 0xfffffffffULL; /* 36 bit MC */
1365 rdev->mc.mc_mask = 0xffffffffULL; /* 32 bit MC */
1374 if (rdev->flags & RADEON_IS_AGP)
1376 if ((rdev->flags & RADEON_IS_PCI) &&
1377 (rdev->family <= CHIP_RS740))
1380 if (rdev->family == CHIP_CEDAR)
1384 r = dma_set_mask_and_coherent(&rdev->pdev->dev, DMA_BIT_MASK(dma_bits));
1389 rdev->need_swiotlb = drm_need_swiotlb(dma_bits);
1393 spin_lock_init(&rdev->mmio_idx_lock);
1394 spin_lock_init(&rdev->smc_idx_lock);
1395 spin_lock_init(&rdev->pll_idx_lock);
1396 spin_lock_init(&rdev->mc_idx_lock);
1397 spin_lock_init(&rdev->pcie_idx_lock);
1398 spin_lock_init(&rdev->pciep_idx_lock);
1399 spin_lock_init(&rdev->pif_idx_lock);
1400 spin_lock_init(&rdev->cg_idx_lock);
1401 spin_lock_init(&rdev->uvd_idx_lock);
1402 spin_lock_init(&rdev->rcu_idx_lock);
1403 spin_lock_init(&rdev->didt_idx_lock);
1404 spin_lock_init(&rdev->end_idx_lock);
1405 if (rdev->family >= CHIP_BONAIRE) {
1406 rdev->rmmio_base = pci_resource_start(rdev->pdev, 5);
1407 rdev->rmmio_size = pci_resource_len(rdev->pdev, 5);
1409 rdev->rmmio_base = pci_resource_start(rdev->pdev, 2);
1410 rdev->rmmio_size = pci_resource_len(rdev->pdev, 2);
1412 rdev->rmmio = ioremap(rdev->rmmio_base, rdev->rmmio_size);
1413 if (rdev->rmmio == NULL)
1417 if (rdev->family >= CHIP_BONAIRE)
1418 radeon_doorbell_init(rdev);
1422 if (pci_resource_flags(rdev->pdev, i) & IORESOURCE_IO) {
1423 rdev->rio_mem_size = pci_resource_len(rdev->pdev, i);
1424 rdev->rio_mem = pci_iomap(rdev->pdev, i, rdev->rio_mem_size);
1428 if (rdev->rio_mem == NULL)
1431 if (rdev->flags & RADEON_IS_PX)
1432 radeon_device_handle_px_quirks(rdev);
1437 vga_client_register(rdev->pdev, rdev, NULL, radeon_vga_set_decode);
1439 if (rdev->flags & RADEON_IS_PX)
1441 if (!pci_is_thunderbolt_attached(rdev->pdev))
1442 vga_switcheroo_register_client(rdev->pdev,
1445 vga_switcheroo_init_domain_pm_ops(rdev->dev, &rdev->vga_pm_domain);
1447 r = radeon_init(rdev);
1451 r = radeon_gem_debugfs_init(rdev);
1456 r = radeon_mst_debugfs_init(rdev);
1461 if (rdev->flags & RADEON_IS_AGP && !rdev->accel_working) {
1465 radeon_asic_reset(rdev);
1466 radeon_fini(rdev);
1467 radeon_agp_disable(rdev);
1468 r = radeon_init(rdev);
1473 r = radeon_ib_ring_tests(rdev);
1482 if (rdev->pm.dpm_enabled &&
1483 (rdev->pm.pm_method == PM_METHOD_DPM) &&
1484 (rdev->family == CHIP_TURKS) &&
1485 (rdev->flags & RADEON_IS_MOBILITY)) {
1486 mutex_lock(&rdev->pm.mutex);
1487 radeon_dpm_disable(rdev);
1488 radeon_dpm_enable(rdev);
1489 mutex_unlock(&rdev->pm.mutex);
1493 if (rdev->accel_working)
1494 radeon_test_moves(rdev);
1499 if (rdev->accel_working)
1500 radeon_test_syncing(rdev);
1505 if (rdev->accel_working)
1506 radeon_benchmark(rdev, radeon_benchmarking);
1517 vga_switcheroo_fini_domain_pm_ops(rdev->dev);
1524 * @rdev: radeon_device pointer
1529 void radeon_device_fini(struct radeon_device *rdev)
1532 rdev->shutdown = true;
1534 radeon_bo_evict_vram(rdev);
1535 radeon_fini(rdev);
1536 if (!pci_is_thunderbolt_attached(rdev->pdev))
1537 vga_switcheroo_unregister_client(rdev->pdev);
1538 if (rdev->flags & RADEON_IS_PX)
1539 vga_switcheroo_fini_domain_pm_ops(rdev->dev);
1540 vga_client_register(rdev->pdev, NULL, NULL, NULL);
1541 if (rdev->rio_mem)
1542 pci_iounmap(rdev->pdev, rdev->rio_mem);
1543 rdev->rio_mem = NULL;
1544 iounmap(rdev->rmmio);
1545 rdev->rmmio = NULL;
1546 if (rdev->family >= CHIP_BONAIRE)
1547 radeon_doorbell_fini(rdev);
1567 struct radeon_device *rdev;
1576 rdev = dev->dev_private;
1610 if (!radeon_fbdev_robj_is_fb(rdev, robj)) {
1619 radeon_bo_evict_vram(rdev);
1623 r = radeon_fence_wait_empty(rdev, i);
1626 radeon_fence_driver_force_completion(rdev, i);
1629 flush_delayed_work(&rdev->fence_drv[i].lockup_work);
1633 radeon_save_bios_scratch_regs(rdev);
1635 radeon_suspend(rdev);
1636 radeon_hpd_fini(rdev);
1641 radeon_bo_evict_vram(rdev);
1643 radeon_agp_suspend(rdev);
1646 if (freeze && rdev->family >= CHIP_CEDAR && !(rdev->flags & RADEON_IS_IGP)) {
1647 rdev->asic->asic_reset(rdev, true);
1657 radeon_fbdev_set_suspend(rdev, 1);
1675 struct radeon_device *rdev = dev->dev_private;
1695 radeon_agp_resume(rdev);
1696 radeon_resume(rdev);
1698 r = radeon_ib_ring_tests(rdev);
1702 if ((rdev->pm.pm_method == PM_METHOD_DPM) && rdev->pm.dpm_enabled) {
1704 r = radeon_pm_late_init(rdev);
1706 rdev->pm.dpm_enabled = false;
1711 radeon_pm_resume(rdev);
1714 radeon_restore_bios_scratch_regs(rdev);
1727 ASIC_IS_AVIVO(rdev) ?
1738 if (rdev->is_atom_bios) {
1739 radeon_atom_encoder_init(rdev);
1740 radeon_atom_disp_eng_pll_init(rdev);
1742 if (rdev->mode_info.bl_encoder) {
1743 u8 bl_level = radeon_get_backlight_level(rdev,
1744 rdev->mode_info.bl_encoder);
1745 radeon_set_backlight_level(rdev, rdev->mode_info.bl_encoder,
1750 radeon_hpd_init(rdev);
1765 if ((rdev->pm.pm_method == PM_METHOD_DPM) && rdev->pm.dpm_enabled)
1766 radeon_pm_compute_clocks(rdev);
1769 radeon_fbdev_set_suspend(rdev, 0);
1779 * @rdev: radeon device pointer
1784 int radeon_gpu_reset(struct radeon_device *rdev)
1794 down_write(&rdev->exclusive_lock);
1796 if (!rdev->needs_reset) {
1797 up_write(&rdev->exclusive_lock);
1801 atomic_inc(&rdev->gpu_reset_counter);
1803 radeon_save_bios_scratch_regs(rdev);
1805 resched = ttm_bo_lock_delayed_workqueue(&rdev->mman.bdev);
1806 radeon_suspend(rdev);
1807 radeon_hpd_fini(rdev);
1810 ring_sizes[i] = radeon_ring_backup(rdev, &rdev->ring[i],
1814 dev_info(rdev->dev, "Saved %d dwords of commands "
1819 r = radeon_asic_reset(rdev);
1821 dev_info(rdev->dev, "GPU reset succeeded, trying to resume\n");
1822 radeon_resume(rdev);
1825 radeon_restore_bios_scratch_regs(rdev);
1829 radeon_ring_restore(rdev, &rdev->ring[i],
1832 radeon_fence_driver_force_completion(rdev, i);
1837 if ((rdev->pm.pm_method == PM_METHOD_DPM) && rdev->pm.dpm_enabled) {
1839 r = radeon_pm_late_init(rdev);
1841 rdev->pm.dpm_enabled = false;
1846 radeon_pm_resume(rdev);
1850 if (rdev->is_atom_bios) {
1851 radeon_atom_encoder_init(rdev);
1852 radeon_atom_disp_eng_pll_init(rdev);
1854 if (rdev->mode_info.bl_encoder) {
1855 u8 bl_level = radeon_get_backlight_level(rdev,
1856 rdev->mode_info.bl_encoder);
1857 radeon_set_backlight_level(rdev, rdev->mode_info.bl_encoder,
1862 radeon_hpd_init(rdev);
1864 ttm_bo_unlock_delayed_workqueue(&rdev->mman.bdev, resched);
1866 rdev->in_reset = true;
1867 rdev->needs_reset = false;
1869 downgrade_write(&rdev->exclusive_lock);
1871 drm_helper_resume_force_mode(rdev->ddev);
1874 if ((rdev->pm.pm_method == PM_METHOD_DPM) && rdev->pm.dpm_enabled)
1875 radeon_pm_compute_clocks(rdev);
1878 r = radeon_ib_ring_tests(rdev);
1883 dev_info(rdev->dev, "GPU reset failed\n");
1886 rdev->needs_reset = r == -EAGAIN;
1887 rdev->in_reset = false;
1889 up_read(&rdev->exclusive_lock);
1897 int radeon_debugfs_add_files(struct radeon_device *rdev,
1903 for (i = 0; i < rdev->debugfs_count; i++) {
1904 if (rdev->debugfs[i].files == files) {
1910 i = rdev->debugfs_count + 1;
1917 rdev->debugfs[rdev->debugfs_count].files = files;
1918 rdev->debugfs[rdev->debugfs_count].num_files = nfiles;
1919 rdev->debugfs_count = i;
1922 rdev->ddev->primary->debugfs_root,
1923 rdev->ddev->primary);