Lines Matching refs:lvds
1107 struct radeon_encoder_lvds *lvds = NULL;
1112 lvds = kzalloc(sizeof(struct radeon_encoder_lvds), GFP_KERNEL);
1114 if (!lvds)
1121 lvds->panel_pwr_delay = 200;
1122 lvds->panel_vcc_delay = 2000;
1124 lvds->lvds_gen_cntl = RREG32(RADEON_LVDS_GEN_CNTL);
1125 lvds->panel_digon_delay = (lvds_ss_gen_cntl >> RADEON_LVDS_PWRSEQ_DELAY1_SHIFT) & 0xf;
1126 lvds->panel_blon_delay = (lvds_ss_gen_cntl >> RADEON_LVDS_PWRSEQ_DELAY2_SHIFT) & 0xf;
1129 lvds->native_mode.vdisplay =
1133 lvds->native_mode.vdisplay =
1137 lvds->native_mode.hdisplay =
1141 lvds->native_mode.hdisplay =
1144 if ((lvds->native_mode.hdisplay < 640) ||
1145 (lvds->native_mode.vdisplay < 480)) {
1146 lvds->native_mode.hdisplay = 640;
1147 lvds->native_mode.vdisplay = 480;
1153 lvds->use_bios_dividers = false;
1155 lvds->panel_ref_divider =
1157 lvds->panel_post_divider = (ppll_val >> 16) & 0x7;
1158 lvds->panel_fb_divider = ppll_val & 0x7ff;
1160 if ((lvds->panel_ref_divider != 0) &&
1161 (lvds->panel_fb_divider > 3))
1162 lvds->use_bios_dividers = true;
1164 lvds->panel_vcc_delay = 200;
1167 DRM_INFO("Panel Size %dx%d\n", lvds->native_mode.hdisplay,
1168 lvds->native_mode.vdisplay);
1170 return lvds;
1182 struct radeon_encoder_lvds *lvds = NULL;
1187 lvds = kzalloc(sizeof(struct radeon_encoder_lvds), GFP_KERNEL);
1189 if (!lvds)
1198 lvds->native_mode.hdisplay = RBIOS16(lcd_info + 0x19);
1199 lvds->native_mode.vdisplay = RBIOS16(lcd_info + 0x1b);
1201 DRM_INFO("Panel Size %dx%d\n", lvds->native_mode.hdisplay,
1202 lvds->native_mode.vdisplay);
1204 lvds->panel_vcc_delay = RBIOS16(lcd_info + 0x2c);
1205 lvds->panel_vcc_delay = min_t(u16, lvds->panel_vcc_delay, 2000);
1207 lvds->panel_pwr_delay = RBIOS8(lcd_info + 0x24);
1208 lvds->panel_digon_delay = RBIOS16(lcd_info + 0x38) & 0xf;
1209 lvds->panel_blon_delay = (RBIOS16(lcd_info + 0x38) >> 4) & 0xf;
1211 lvds->panel_ref_divider = RBIOS16(lcd_info + 0x2e);
1212 lvds->panel_post_divider = RBIOS8(lcd_info + 0x30);
1213 lvds->panel_fb_divider = RBIOS16(lcd_info + 0x31);
1214 if ((lvds->panel_ref_divider != 0) &&
1215 (lvds->panel_fb_divider > 3))
1216 lvds->use_bios_dividers = true;
1219 lvds->lvds_gen_cntl = 0xff00;
1221 lvds->lvds_gen_cntl |= RADEON_LVDS_PANEL_FORMAT;
1224 lvds->lvds_gen_cntl |= RADEON_LVDS_PANEL_TYPE;
1228 lvds->lvds_gen_cntl |= RADEON_LVDS_NO_FM;
1231 lvds->lvds_gen_cntl |= RADEON_LVDS_2_GREY;
1234 lvds->lvds_gen_cntl |= RADEON_LVDS_4_GREY;
1241 lvds->lvds_gen_cntl |= RADEON_LVDS_FP_POL_LOW;
1244 lvds->lvds_gen_cntl |= RADEON_LVDS_LP_POL_LOW;
1247 lvds->lvds_gen_cntl |= RADEON_LVDS_DTM_POL_LOW;
1250 lvds->lvds_gen_cntl |= RADEON_LVDS_BL_CLK_SEL;
1252 lvds->lvds_gen_cntl |= (panel_setup & 0xf0000000);
1259 if ((RBIOS16(tmp) == lvds->native_mode.hdisplay) &&
1260 (RBIOS16(tmp + 2) == lvds->native_mode.vdisplay)) {
1263 if (hss > lvds->native_mode.hdisplay)
1266 lvds->native_mode.htotal = lvds->native_mode.hdisplay +
1268 lvds->native_mode.hsync_start = lvds->native_mode.hdisplay +
1270 lvds->native_mode.hsync_end = lvds->native_mode.hsync_start +
1273 lvds->native_mode.vtotal = lvds->native_mode.vdisplay +
1275 lvds->native_mode.vsync_start = lvds->native_mode.vdisplay +
1277 lvds->native_mode.vsync_end = lvds->native_mode.vsync_start +
1280 lvds->native_mode.clock = RBIOS16(tmp + 9) * 10;
1281 lvds->native_mode.flags = 0;
1283 drm_mode_set_crtcinfo(&lvds->native_mode, CRTC_INTERLACE_HALVE_V);
1289 lvds = radeon_legacy_get_lvds_info_from_regs(rdev);
1292 if (lvds)
1293 encoder->native_mode = lvds->native_mode;
1294 return lvds;