Lines Matching defs:rdev
143 void r600_dpm_print_ps_status(struct radeon_device *rdev,
147 if (rps == rdev->pm.dpm.current_ps)
149 if (rps == rdev->pm.dpm.requested_ps)
151 if (rps == rdev->pm.dpm.boot_ps)
156 u32 r600_dpm_get_vblank_time(struct radeon_device *rdev)
158 struct drm_device *dev = rdev->ddev;
164 if (rdev->num_crtc && rdev->mode_info.mode_config_initialized) {
183 u32 r600_dpm_get_vrefresh(struct radeon_device *rdev)
185 struct drm_device *dev = rdev->ddev;
190 if (rdev->num_crtc && rdev->mode_info.mode_config_initialized) {
242 void r600_gfx_clockgating_enable(struct radeon_device *rdev, bool enable)
253 for (i = 0; i < rdev->usec_timeout; i++) {
266 void r600_dynamicpm_enable(struct radeon_device *rdev, bool enable)
274 void r600_enable_thermal_protection(struct radeon_device *rdev, bool enable)
282 void r600_enable_acpi_pm(struct radeon_device *rdev)
287 void r600_enable_dynamic_pcie_gen2(struct radeon_device *rdev, bool enable)
295 bool r600_dynamicpm_enabled(struct radeon_device *rdev)
303 void r600_enable_sclk_control(struct radeon_device *rdev, bool enable)
311 void r600_enable_mclk_control(struct radeon_device *rdev, bool enable)
319 void r600_enable_spll_bypass(struct radeon_device *rdev, bool enable)
327 void r600_wait_for_spll_change(struct radeon_device *rdev)
331 for (i = 0; i < rdev->usec_timeout; i++) {
338 void r600_set_bsp(struct radeon_device *rdev, u32 u, u32 p)
343 void r600_set_at(struct radeon_device *rdev,
351 void r600_set_tc(struct radeon_device *rdev,
357 void r600_select_td(struct radeon_device *rdev,
370 void r600_set_vrc(struct radeon_device *rdev, u32 vrv)
375 void r600_set_tpu(struct radeon_device *rdev, u32 u)
380 void r600_set_tpc(struct radeon_device *rdev, u32 c)
385 void r600_set_sstu(struct radeon_device *rdev, u32 u)
390 void r600_set_sst(struct radeon_device *rdev, u32 t)
395 void r600_set_git(struct radeon_device *rdev, u32 t)
400 void r600_set_fctu(struct radeon_device *rdev, u32 u)
405 void r600_set_fct(struct radeon_device *rdev, u32 t)
410 void r600_set_ctxcgtt3d_rphc(struct radeon_device *rdev, u32 p)
415 void r600_set_ctxcgtt3d_rsdc(struct radeon_device *rdev, u32 s)
420 void r600_set_vddc3d_oorsu(struct radeon_device *rdev, u32 u)
425 void r600_set_vddc3d_oorphc(struct radeon_device *rdev, u32 p)
430 void r600_set_vddc3d_oorsdc(struct radeon_device *rdev, u32 s)
435 void r600_set_mpll_lock_time(struct radeon_device *rdev, u32 lock_time)
440 void r600_set_mpll_reset_time(struct radeon_device *rdev, u32 reset_time)
445 void r600_engine_clock_entry_enable(struct radeon_device *rdev,
456 void r600_engine_clock_entry_enable_pulse_skipping(struct radeon_device *rdev,
467 void r600_engine_clock_entry_enable_post_divider(struct radeon_device *rdev,
478 void r600_engine_clock_entry_set_post_divider(struct radeon_device *rdev,
485 void r600_engine_clock_entry_set_reference_divider(struct radeon_device *rdev,
492 void r600_engine_clock_entry_set_feedback_divider(struct radeon_device *rdev,
499 void r600_engine_clock_entry_set_step_time(struct radeon_device *rdev,
506 void r600_vid_rt_set_ssu(struct radeon_device *rdev, u32 u)
511 void r600_vid_rt_set_vru(struct radeon_device *rdev, u32 u)
516 void r600_vid_rt_set_vrt(struct radeon_device *rdev, u32 rt)
521 void r600_voltage_control_enable_pins(struct radeon_device *rdev,
529 void r600_voltage_control_program_voltages(struct radeon_device *rdev,
543 void r600_voltage_control_deactivate_static_control(struct radeon_device *rdev,
561 void r600_power_level_enable(struct radeon_device *rdev,
574 void r600_power_level_set_voltage_index(struct radeon_device *rdev,
583 void r600_power_level_set_mem_clock_index(struct radeon_device *rdev,
592 void r600_power_level_set_eng_clock_index(struct radeon_device *rdev,
601 void r600_power_level_set_watermark_id(struct radeon_device *rdev,
613 void r600_power_level_set_pcie_gen2(struct radeon_device *rdev,
624 enum r600_power_level r600_power_level_get_current_index(struct radeon_device *rdev)
633 enum r600_power_level r600_power_level_get_target_index(struct radeon_device *rdev)
642 void r600_power_level_set_enter_index(struct radeon_device *rdev,
649 void r600_wait_for_power_level_unequal(struct radeon_device *rdev,
654 for (i = 0; i < rdev->usec_timeout; i++) {
655 if (r600_power_level_get_target_index(rdev) != index)
660 for (i = 0; i < rdev->usec_timeout; i++) {
661 if (r600_power_level_get_current_index(rdev) != index)
667 void r600_wait_for_power_level(struct radeon_device *rdev,
672 for (i = 0; i < rdev->usec_timeout; i++) {
673 if (r600_power_level_get_target_index(rdev) == index)
678 for (i = 0; i < rdev->usec_timeout; i++) {
679 if (r600_power_level_get_current_index(rdev) == index)
685 void r600_start_dpm(struct radeon_device *rdev)
687 r600_enable_sclk_control(rdev, false);
688 r600_enable_mclk_control(rdev, false);
690 r600_dynamicpm_enable(rdev, true);
692 radeon_wait_for_vblank(rdev, 0);
693 radeon_wait_for_vblank(rdev, 1);
695 r600_enable_spll_bypass(rdev, true);
696 r600_wait_for_spll_change(rdev);
697 r600_enable_spll_bypass(rdev, false);
698 r600_wait_for_spll_change(rdev);
700 r600_enable_spll_bypass(rdev, true);
701 r600_wait_for_spll_change(rdev);
702 r600_enable_spll_bypass(rdev, false);
703 r600_wait_for_spll_change(rdev);
705 r600_enable_sclk_control(rdev, true);
706 r600_enable_mclk_control(rdev, true);
709 void r600_stop_dpm(struct radeon_device *rdev)
711 r600_dynamicpm_enable(rdev, false);
714 int r600_dpm_pre_set_power_state(struct radeon_device *rdev)
719 void r600_dpm_post_set_power_state(struct radeon_device *rdev)
739 static int r600_set_thermal_temperature_range(struct radeon_device *rdev,
758 rdev->pm.dpm.thermal.min_temp = low_temp;
759 rdev->pm.dpm.thermal.max_temp = high_temp;
787 int r600_dpm_late_enable(struct radeon_device *rdev)
791 if (rdev->irq.installed &&
792 r600_is_internal_thermal_sensor(rdev->pm.int_thermal_type)) {
793 ret = r600_set_thermal_temperature_range(rdev, R600_TEMP_RANGE_MIN, R600_TEMP_RANGE_MAX);
796 rdev->irq.dpm_thermal = true;
797 radeon_irq_set(rdev);
845 int r600_get_platform_caps(struct radeon_device *rdev)
847 struct radeon_mode_info *mode_info = &rdev->mode_info;
858 rdev->pm.dpm.platform_caps = le32_to_cpu(power_info->pplib.ulPlatformCaps);
859 rdev->pm.dpm.backbias_response_time = le16_to_cpu(power_info->pplib.usBackbiasTime);
860 rdev->pm.dpm.voltage_response_time = le16_to_cpu(power_info->pplib.usVoltageTime);
873 int r600_parse_extended_power_table(struct radeon_device *rdev)
875 struct radeon_mode_info *mode_info = &rdev->mode_info;
895 rdev->pm.dpm.fan.t_hyst = fan_info->fan.ucTHyst;
896 rdev->pm.dpm.fan.t_min = le16_to_cpu(fan_info->fan.usTMin);
897 rdev->pm.dpm.fan.t_med = le16_to_cpu(fan_info->fan.usTMed);
898 rdev->pm.dpm.fan.t_high = le16_to_cpu(fan_info->fan.usTHigh);
899 rdev->pm.dpm.fan.pwm_min = le16_to_cpu(fan_info->fan.usPWMMin);
900 rdev->pm.dpm.fan.pwm_med = le16_to_cpu(fan_info->fan.usPWMMed);
901 rdev->pm.dpm.fan.pwm_high = le16_to_cpu(fan_info->fan.usPWMHigh);
903 rdev->pm.dpm.fan.t_max = le16_to_cpu(fan_info->fan2.usTMax);
905 rdev->pm.dpm.fan.t_max = 10900;
906 rdev->pm.dpm.fan.cycle_delay = 100000;
908 rdev->pm.dpm.fan.control_mode = fan_info->fan3.ucFanControlMode;
909 rdev->pm.dpm.fan.default_max_fan_pwm =
911 rdev->pm.dpm.fan.default_fan_output_sensitivity = 4836;
912 rdev->pm.dpm.fan.fan_output_sensitivity =
915 rdev->pm.dpm.fan.ucode_fan_control = true;
926 ret = r600_parse_clk_voltage_dep_table(&rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk,
935 ret = r600_parse_clk_voltage_dep_table(&rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk,
938 kfree(rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries);
946 ret = r600_parse_clk_voltage_dep_table(&rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk,
949 kfree(rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries);
950 kfree(rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk.entries);
958 ret = r600_parse_clk_voltage_dep_table(&rdev->pm.dpm.dyn_state.mvdd_dependency_on_mclk,
961 kfree(rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries);
962 kfree(rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk.entries);
963 kfree(rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk.entries);
973 rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc.sclk =
976 rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc.mclk =
979 rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc.vddc =
981 rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc.vddci =
992 rdev->pm.dpm.dyn_state.phase_shedding_limits_table.entries =
996 if (!rdev->pm.dpm.dyn_state.phase_shedding_limits_table.entries) {
997 r600_free_extended_power_table(rdev);
1003 rdev->pm.dpm.dyn_state.phase_shedding_limits_table.entries[i].sclk =
1005 rdev->pm.dpm.dyn_state.phase_shedding_limits_table.entries[i].mclk =
1007 rdev->pm.dpm.dyn_state.phase_shedding_limits_table.entries[i].voltage =
1012 rdev->pm.dpm.dyn_state.phase_shedding_limits_table.count =
1020 rdev->pm.dpm.tdp_limit = le32_to_cpu(power_info->pplib5.ulTDPLimit);
1021 rdev->pm.dpm.near_tdp_limit = le32_to_cpu(power_info->pplib5.ulNearTDPLimit);
1022 rdev->pm.dpm.near_tdp_limit_adjusted = rdev->pm.dpm.near_tdp_limit;
1023 rdev->pm.dpm.tdp_od_limit = le16_to_cpu(power_info->pplib5.usTDPODLimit);
1024 if (rdev->pm.dpm.tdp_od_limit)
1025 rdev->pm.dpm.power_control = true;
1027 rdev->pm.dpm.power_control = false;
1028 rdev->pm.dpm.tdp_adjustment = 0;
1029 rdev->pm.dpm.sq_ramping_threshold = le32_to_cpu(power_info->pplib5.ulSQRampingThreshold);
1030 rdev->pm.dpm.cac_leakage = le32_to_cpu(power_info->pplib5.ulCACLeakage);
1031 rdev->pm.dpm.load_line_slope = le16_to_cpu(power_info->pplib5.usLoadLineSlope);
1039 rdev->pm.dpm.dyn_state.cac_leakage_table.entries = kzalloc(size, GFP_KERNEL);
1040 if (!rdev->pm.dpm.dyn_state.cac_leakage_table.entries) {
1041 r600_free_extended_power_table(rdev);
1046 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_EVV) {
1047 rdev->pm.dpm.dyn_state.cac_leakage_table.entries[i].vddc1 =
1049 rdev->pm.dpm.dyn_state.cac_leakage_table.entries[i].vddc2 =
1051 rdev->pm.dpm.dyn_state.cac_leakage_table.entries[i].vddc3 =
1054 rdev->pm.dpm.dyn_state.cac_leakage_table.entries[i].vddc =
1056 rdev->pm.dpm.dyn_state.cac_leakage_table.entries[i].leakage =
1062 rdev->pm.dpm.dyn_state.cac_leakage_table.count = cac_table->ucNumEntries;
1093 rdev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table.entries =
1095 if (!rdev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table.entries) {
1096 r600_free_extended_power_table(rdev);
1099 rdev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table.count =
1107 rdev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table.entries[i].evclk =
1109 rdev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table.entries[i].ecclk =
1111 rdev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table.entries[i].v =
1122 rdev->pm.dpm.vce_states[i].evclk =
1124 rdev->pm.dpm.vce_states[i].ecclk =
1126 rdev->pm.dpm.vce_states[i].clk_idx =
1128 rdev->pm.dpm.vce_states[i].pstate =
1147 rdev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.entries =
1149 if (!rdev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.entries) {
1150 r600_free_extended_power_table(rdev);
1153 rdev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.count =
1160 rdev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.entries[i].vclk =
1162 rdev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.entries[i].dclk =
1164 rdev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.entries[i].v =
1179 rdev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table.entries =
1181 if (!rdev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table.entries) {
1182 r600_free_extended_power_table(rdev);
1185 rdev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table.count =
1189 rdev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table.entries[i].clk =
1191 rdev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table.entries[i].v =
1202 rdev->pm.dpm.dyn_state.ppm_table =
1204 if (!rdev->pm.dpm.dyn_state.ppm_table) {
1205 r600_free_extended_power_table(rdev);
1208 rdev->pm.dpm.dyn_state.ppm_table->ppm_design = ppm->ucPpmDesign;
1209 rdev->pm.dpm.dyn_state.ppm_table->cpu_core_number =
1211 rdev->pm.dpm.dyn_state.ppm_table->platform_tdp =
1213 rdev->pm.dpm.dyn_state.ppm_table->small_ac_platform_tdp =
1215 rdev->pm.dpm.dyn_state.ppm_table->platform_tdc =
1217 rdev->pm.dpm.dyn_state.ppm_table->small_ac_platform_tdc =
1219 rdev->pm.dpm.dyn_state.ppm_table->apu_tdp =
1221 rdev->pm.dpm.dyn_state.ppm_table->dgpu_tdp =
1223 rdev->pm.dpm.dyn_state.ppm_table->dgpu_ulv_power =
1225 rdev->pm.dpm.dyn_state.ppm_table->tj_max =
1237 rdev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table.entries =
1239 if (!rdev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table.entries) {
1240 r600_free_extended_power_table(rdev);
1243 rdev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table.count =
1247 rdev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table.entries[i].clk =
1249 rdev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table.entries[i].v =
1260 rdev->pm.dpm.dyn_state.cac_tdp_table =
1262 if (!rdev->pm.dpm.dyn_state.cac_tdp_table) {
1263 r600_free_extended_power_table(rdev);
1270 rdev->pm.dpm.dyn_state.cac_tdp_table->maximum_power_delivery_limit =
1277 rdev->pm.dpm.dyn_state.cac_tdp_table->maximum_power_delivery_limit = 255;
1280 rdev->pm.dpm.dyn_state.cac_tdp_table->tdp = le16_to_cpu(pt->usTDP);
1281 rdev->pm.dpm.dyn_state.cac_tdp_table->configurable_tdp =
1283 rdev->pm.dpm.dyn_state.cac_tdp_table->tdc = le16_to_cpu(pt->usTDC);
1284 rdev->pm.dpm.dyn_state.cac_tdp_table->battery_power_limit =
1286 rdev->pm.dpm.dyn_state.cac_tdp_table->small_power_limit =
1288 rdev->pm.dpm.dyn_state.cac_tdp_table->low_cac_leakage =
1290 rdev->pm.dpm.dyn_state.cac_tdp_table->high_cac_leakage =
1298 void r600_free_extended_power_table(struct radeon_device *rdev)
1300 struct radeon_dpm_dynamic_state *dyn_state = &rdev->pm.dpm.dyn_state;
1316 enum radeon_pcie_gen r600_get_pcie_gen_support(struct radeon_device *rdev,
1339 u16 r600_get_pcie_lane_support(struct radeon_device *rdev,