Lines Matching refs:ring
35 * to the 3D engine (ring buffer, IBs, etc.), but the
47 * @ring: radeon ring pointer
52 struct radeon_ring *ring)
57 rptr = rdev->wb.wb[ring->rptr_offs/4];
68 * @ring: radeon ring pointer
73 struct radeon_ring *ring)
82 * @ring: radeon ring pointer
87 struct radeon_ring *ring)
89 WREG32(DMA_RB_WPTR, (ring->wptr << 2) & 0x3fffc);
109 rdev->ring[R600_RING_TYPE_DMA_INDEX].ready = false;
117 * Set up the DMA ring buffer and enable it. (r6xx-evergreen).
122 struct radeon_ring *ring = &rdev->ring[R600_RING_TYPE_DMA_INDEX];
130 /* Set ring buffer size in dwords */
131 rb_bufsz = order_base_2(ring->ring_size / 4);
138 /* Initialize the ring buffer's read and write pointers */
151 WREG32(DMA_RB_BASE, ring->gpu_addr >> 8);
167 ring->wptr = 0;
168 WREG32(DMA_RB_WPTR, ring->wptr << 2);
172 ring->ready = true;
174 r = radeon_ring_test(rdev, R600_RING_TYPE_DMA_INDEX, ring);
176 ring->ready = false;
191 * Stop the async dma engine and free the ring (r6xx-evergreen).
196 radeon_ring_fini(rdev, &rdev->ring[R600_RING_TYPE_DMA_INDEX]);
203 * @ring: radeon_ring structure holding ring information
208 bool r600_dma_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring)
213 radeon_ring_lockup_update(rdev, ring);
216 return radeon_ring_test_lockup(rdev, ring);
224 * @ring: radeon_ring structure holding ring information
231 struct radeon_ring *ring)
239 if (ring->idx == R600_RING_TYPE_DMA_INDEX)
249 r = radeon_ring_lock(rdev, ring, 4);
251 DRM_ERROR("radeon: dma failed to lock ring %d (%d).\n", ring->idx, r);
254 radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_WRITE, 0, 0, 1));
255 radeon_ring_write(ring, lower_32_bits(gpu_addr));
256 radeon_ring_write(ring, upper_32_bits(gpu_addr) & 0xff);
257 radeon_ring_write(ring, 0xDEADBEEF);
258 radeon_ring_unlock_commit(rdev, ring, false);
268 DRM_INFO("ring test on %d succeeded in %d usecs\n", ring->idx, i);
270 DRM_ERROR("radeon: ring %d test failed (0x%08X)\n",
271 ring->idx, tmp);
278 * r600_dma_fence_ring_emit - emit a fence on the DMA ring
283 * Add a DMA fence packet to the ring to write
290 struct radeon_ring *ring = &rdev->ring[fence->ring];
291 u64 addr = rdev->fence_drv[fence->ring].gpu_addr;
294 radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_FENCE, 0, 0, 0));
295 radeon_ring_write(ring, addr & 0xfffffffc);
296 radeon_ring_write(ring, (upper_32_bits(addr) & 0xff));
297 radeon_ring_write(ring, lower_32_bits(fence->seq));
299 radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_TRAP, 0, 0, 0));
303 * r600_dma_semaphore_ring_emit - emit a semaphore on the dma ring
306 * @ring: radeon_ring structure holding ring information
310 * Add a DMA semaphore packet to the ring wait on or signal
314 struct radeon_ring *ring,
321 radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_SEMAPHORE, 0, s, 0));
322 radeon_ring_write(ring, addr & 0xfffffffc);
323 radeon_ring_write(ring, upper_32_bits(addr) & 0xff);
332 * @ring: radeon_ring structure holding ring information
334 * Test a simple IB in the DMA ring (r6xx-SI).
337 int r600_dma_ib_test(struct radeon_device *rdev, struct radeon_ring *ring)
346 if (ring->idx == R600_RING_TYPE_DMA_INDEX)
353 r = radeon_ib_get(rdev, ring->idx, &ib, NULL, 256);
388 DRM_INFO("ib test on ring %d succeeded in %u usecs\n", ib.fence->ring, i);
403 * Schedule an IB in the DMA ring (r6xx-r7xx).
407 struct radeon_ring *ring = &rdev->ring[ib->ring];
410 u32 next_rptr = ring->wptr + 4;
414 radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_WRITE, 0, 0, 1));
415 radeon_ring_write(ring, ring->next_rptr_gpu_addr & 0xfffffffc);
416 radeon_ring_write(ring, upper_32_bits(ring->next_rptr_gpu_addr) & 0xff);
417 radeon_ring_write(ring, next_rptr);
420 /* The indirect buffer packet must end on an 8 DW boundary in the DMA ring.
423 while ((ring->wptr & 7) != 5)
424 radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_NOP, 0, 0, 0));
425 radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_INDIRECT_BUFFER, 0, 0, 0));
426 radeon_ring_write(ring, (ib->gpu_addr & 0xFFFFFFE0));
427 radeon_ring_write(ring, (ib->length_dw << 16) | (upper_32_bits(ib->gpu_addr) & 0xFF));
452 struct radeon_ring *ring = &rdev->ring[ring_index];
461 r = radeon_ring_lock(rdev, ring, num_loops * 4 + 8);
469 radeon_sync_rings(rdev, &sync, ring->idx);
476 radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_COPY, 0, 0, cur_size_in_dw));
477 radeon_ring_write(ring, dst_offset & 0xfffffffc);
478 radeon_ring_write(ring, src_offset & 0xfffffffc);
479 radeon_ring_write(ring, (((upper_32_bits(dst_offset) & 0xff) << 16) |
485 r = radeon_fence_emit(rdev, &fence, ring->idx);
487 radeon_ring_unlock_undo(rdev, ring);
492 radeon_ring_unlock_commit(rdev, ring, false);