Lines Matching refs:track
44 /* value we track */
300 static void r600_cs_track_init(struct r600_cs_track *track)
305 track->sq_config = DX9_CONSTS;
307 track->cb_color_base_last[i] = 0;
308 track->cb_color_size[i] = 0;
309 track->cb_color_size_idx[i] = 0;
310 track->cb_color_info[i] = 0;
311 track->cb_color_view[i] = 0xFFFFFFFF;
312 track->cb_color_bo[i] = NULL;
313 track->cb_color_bo_offset[i] = 0xFFFFFFFF;
314 track->cb_color_bo_mc[i] = 0xFFFFFFFF;
315 track->cb_color_frag_bo[i] = NULL;
316 track->cb_color_frag_offset[i] = 0xFFFFFFFF;
317 track->cb_color_tile_bo[i] = NULL;
318 track->cb_color_tile_offset[i] = 0xFFFFFFFF;
319 track->cb_color_mask[i] = 0xFFFFFFFF;
321 track->is_resolve = false;
322 track->nsamples = 16;
323 track->log_nsamples = 4;
324 track->cb_target_mask = 0xFFFFFFFF;
325 track->cb_shader_mask = 0xFFFFFFFF;
326 track->cb_dirty = true;
327 track->db_bo = NULL;
328 track->db_bo_mc = 0xFFFFFFFF;
330 track->db_depth_info = 7 | (1 << 25);
331 track->db_depth_view = 0xFFFFC000;
332 track->db_depth_size = 0xFFFFFFFF;
333 track->db_depth_size_idx = 0;
334 track->db_depth_control = 0xFFFFFFFF;
335 track->db_dirty = true;
336 track->htile_bo = NULL;
337 track->htile_offset = 0xFFFFFFFF;
338 track->htile_surface = 0;
341 track->vgt_strmout_size[i] = 0;
342 track->vgt_strmout_bo[i] = NULL;
343 track->vgt_strmout_bo_offset[i] = 0xFFFFFFFF;
344 track->vgt_strmout_bo_mc[i] = 0xFFFFFFFF;
346 track->streamout_dirty = true;
347 track->sx_misc_kill_all_prims = false;
352 struct r600_cs_track *track = p->track;
361 unsigned nsamples = track->is_resolve && i == 1 ? 1 : track->nsamples;
363 format = G_0280A0_FORMAT(track->cb_color_info[i]);
367 i, track->cb_color_info[i]);
371 pitch = (G_028060_PITCH_TILE_MAX(track->cb_color_size[i]) + 1) * 8;
372 slice_tile_max = G_028060_SLICE_TILE_MAX(track->cb_color_size[i]) + 1;
377 array_mode = G_0280A0_ARRAY_MODE(track->cb_color_info[i]);
379 base_offset = track->cb_color_bo_mc[i] + track->cb_color_bo_offset[i];
381 array_check.group_size = track->group_size;
382 array_check.nbanks = track->nbanks;
383 array_check.npipes = track->npipes;
389 G_0280A0_ARRAY_MODE(track->cb_color_info[i]), i,
390 track->cb_color_info[i]);
407 G_0280A0_ARRAY_MODE(track->cb_color_info[i]), i,
408 track->cb_color_info[i]);
435 tmp += track->cb_color_view[i] & 0xFF;
439 tmp += G_028080_SLICE_MAX(track->cb_color_view[i]) * tmp;
442 if ((tmp + track->cb_color_bo_offset[i]) > radeon_bo_size(track->cb_color_bo[i])) {
453 track->cb_color_bo_offset[i], tmp,
454 radeon_bo_size(track->cb_color_bo[i]),
467 ib[track->cb_color_size_idx[i]] = tmp;
470 switch (G_0280A0_TILE_MODE(track->cb_color_info[i])) {
474 if (track->nsamples > 1) {
475 uint32_t tile_max = G_028100_FMASK_TILE_MAX(track->cb_color_mask[i]);
478 uint32_t bytes = track->nsamples * track->log_nsamples * 8 * (tile_max + 1);
480 if (bytes + track->cb_color_frag_offset[i] >
481 radeon_bo_size(track->cb_color_frag_bo[i])) {
485 track->cb_color_frag_offset[i],
486 radeon_bo_size(track->cb_color_frag_bo[i]));
493 uint32_t block_max = G_028100_CMASK_BLOCK_MAX(track->cb_color_mask[i]);
498 if (bytes + track->cb_color_tile_offset[i] >
499 radeon_bo_size(track->cb_color_tile_bo[i])) {
503 track->cb_color_tile_offset[i],
504 radeon_bo_size(track->cb_color_tile_bo[i]));
518 struct r600_cs_track *track = p->track;
529 if (track->db_bo == NULL) {
533 switch (G_028010_FORMAT(track->db_depth_info)) {
548 dev_warn(p->dev, "z/stencil with invalid format %d\n", G_028010_FORMAT(track->db_depth_info));
551 if ((track->db_depth_size & 0xFFFFFC00) == 0xFFFFFC00) {
552 if (!track->db_depth_size_idx) {
556 tmp = radeon_bo_size(track->db_bo) - track->db_offset;
560 track->db_depth_size, bpe, track->db_offset,
561 radeon_bo_size(track->db_bo));
564 ib[track->db_depth_size_idx] = S_028000_SLICE_TILE_MAX(tmp - 1) | (track->db_depth_size & 0x3FF);
567 pitch = (G_028000_PITCH_TILE_MAX(track->db_depth_size) + 1) * 8;
568 slice_tile_max = G_028000_SLICE_TILE_MAX(track->db_depth_size) + 1;
573 base_offset = track->db_bo_mc + track->db_offset;
574 array_mode = G_028010_ARRAY_MODE(track->db_depth_info);
576 array_check.group_size = track->group_size;
577 array_check.nbanks = track->nbanks;
578 array_check.npipes = track->npipes;
579 array_check.nsamples = track->nsamples;
584 G_028010_ARRAY_MODE(track->db_depth_info),
585 track->db_depth_info);
597 G_028010_ARRAY_MODE(track->db_depth_info),
598 track->db_depth_info);
618 ntiles = G_028000_SLICE_TILE_MAX(track->db_depth_size) + 1;
619 nviews = G_028004_SLICE_MAX(track->db_depth_view) + 1;
620 tmp = ntiles * bpe * 64 * nviews * track->nsamples;
621 if ((tmp + track->db_offset) > radeon_bo_size(track->db_bo)) {
624 track->db_depth_size, ntiles, nviews, bpe, tmp + track->db_offset,
625 radeon_bo_size(track->db_bo));
631 if (G_028010_TILE_SURFACE_ENABLE(track->db_depth_info)) {
635 if (track->htile_bo == NULL) {
637 __func__, __LINE__, track->db_depth_info);
640 if ((track->db_depth_size & 0xFFFFFC00) == 0xFFFFFC00) {
642 __func__, __LINE__, track->db_depth_size);
648 if (G_028D24_LINEAR(track->htile_surface)) {
652 nby = round_up(nby, track->npipes * 8);
658 switch (track->npipes) {
681 __func__, __LINE__, track->npipes);
689 size = roundup(nbx * nby * 4, track->npipes * (2 << 10));
690 size += track->htile_offset;
692 if (size > radeon_bo_size(track->htile_bo)) {
694 __func__, __LINE__, radeon_bo_size(track->htile_bo),
700 track->db_dirty = false;
706 struct r600_cs_track *track = p->track;
715 if (track->streamout_dirty && track->vgt_strmout_en) {
717 if (track->vgt_strmout_buffer_en & (1 << i)) {
718 if (track->vgt_strmout_bo[i]) {
719 u64 offset = (u64)track->vgt_strmout_bo_offset[i] +
720 (u64)track->vgt_strmout_size[i];
721 if (offset > radeon_bo_size(track->vgt_strmout_bo[i])) {
724 radeon_bo_size(track->vgt_strmout_bo[i]));
733 track->streamout_dirty = false;
736 if (track->sx_misc_kill_all_prims)
742 if (track->cb_dirty) {
743 tmp = track->cb_target_mask;
746 if (track->is_resolve) {
751 u32 format = G_0280A0_FORMAT(track->cb_color_info[i]);
756 if (track->cb_color_bo[i] == NULL) {
758 __func__, __LINE__, track->cb_target_mask, track->cb_shader_mask, i);
767 track->cb_dirty = false;
771 if (track->db_dirty &&
772 G_028010_FORMAT(track->db_depth_info) != V_028010_DEPTH_INVALID &&
773 (G_028800_STENCIL_ENABLE(track->db_depth_control) ||
774 G_028800_Z_ENABLE(track->db_depth_control))) {
969 struct r600_cs_track *track = (struct r600_cs_track *)p->track;
1024 track->sq_config = radeon_get_ib_value(p, idx);
1027 track->db_depth_control = radeon_get_ib_value(p, idx);
1028 track->db_dirty = true;
1039 track->db_depth_info = radeon_get_ib_value(p, idx);
1041 track->db_depth_info &= C_028010_ARRAY_MODE;
1044 track->db_depth_info |= S_028010_ARRAY_MODE(V_028010_ARRAY_2D_TILED_THIN1);
1047 track->db_depth_info |= S_028010_ARRAY_MODE(V_028010_ARRAY_1D_TILED_THIN1);
1050 track->db_depth_info = radeon_get_ib_value(p, idx);
1052 track->db_dirty = true;
1055 track->db_depth_view = radeon_get_ib_value(p, idx);
1056 track->db_dirty = true;
1059 track->db_depth_size = radeon_get_ib_value(p, idx);
1060 track->db_depth_size_idx = idx;
1061 track->db_dirty = true;
1064 track->vgt_strmout_en = radeon_get_ib_value(p, idx);
1065 track->streamout_dirty = true;
1068 track->vgt_strmout_buffer_en = radeon_get_ib_value(p, idx);
1069 track->streamout_dirty = true;
1082 track->vgt_strmout_bo_offset[tmp] = radeon_get_ib_value(p, idx) << 8;
1084 track->vgt_strmout_bo[tmp] = reloc->robj;
1085 track->vgt_strmout_bo_mc[tmp] = reloc->gpu_offset;
1086 track->streamout_dirty = true;
1094 track->vgt_strmout_size[tmp] = radeon_get_ib_value(p, idx) * 4;
1095 track->streamout_dirty = true;
1107 track->cb_target_mask = radeon_get_ib_value(p, idx);
1108 track->cb_dirty = true;
1111 track->cb_shader_mask = radeon_get_ib_value(p, idx);
1115 track->log_nsamples = tmp;
1116 track->nsamples = 1 << tmp;
1117 track->cb_dirty = true;
1121 track->is_resolve = tmp == V_028808_SPECIAL_RESOLVE_BOX;
1122 track->cb_dirty = true;
1140 track->cb_color_info[tmp] = radeon_get_ib_value(p, idx);
1143 track->cb_color_info[tmp] |= S_0280A0_ARRAY_MODE(V_0280A0_ARRAY_2D_TILED_THIN1);
1146 track->cb_color_info[tmp] |= S_0280A0_ARRAY_MODE(V_0280A0_ARRAY_1D_TILED_THIN1);
1150 track->cb_color_info[tmp] = radeon_get_ib_value(p, idx);
1152 track->cb_dirty = true;
1163 track->cb_color_view[tmp] = radeon_get_ib_value(p, idx);
1164 track->cb_dirty = true;
1175 track->cb_color_size[tmp] = radeon_get_ib_value(p, idx);
1176 track->cb_color_size_idx[tmp] = idx;
1177 track->cb_dirty = true;
1198 if (!track->cb_color_base_last[tmp]) {
1202 track->cb_color_frag_bo[tmp] = track->cb_color_bo[tmp];
1203 track->cb_color_frag_offset[tmp] = track->cb_color_bo_offset[tmp];
1204 ib[idx] = track->cb_color_base_last[tmp];
1211 track->cb_color_frag_bo[tmp] = reloc->robj;
1212 track->cb_color_frag_offset[tmp] = (u64)ib[idx] << 8;
1215 if (G_0280A0_TILE_MODE(track->cb_color_info[tmp])) {
1216 track->cb_dirty = true;
1229 if (!track->cb_color_base_last[tmp]) {
1233 track->cb_color_tile_bo[tmp] = track->cb_color_bo[tmp];
1234 track->cb_color_tile_offset[tmp] = track->cb_color_bo_offset[tmp];
1235 ib[idx] = track->cb_color_base_last[tmp];
1242 track->cb_color_tile_bo[tmp] = reloc->robj;
1243 track->cb_color_tile_offset[tmp] = (u64)ib[idx] << 8;
1246 if (G_0280A0_TILE_MODE(track->cb_color_info[tmp])) {
1247 track->cb_dirty = true;
1259 track->cb_color_mask[tmp] = radeon_get_ib_value(p, idx);
1260 if (G_0280A0_TILE_MODE(track->cb_color_info[tmp])) {
1261 track->cb_dirty = true;
1279 track->cb_color_bo_offset[tmp] = (u64)radeon_get_ib_value(p, idx) << 8;
1281 track->cb_color_base_last[tmp] = ib[idx];
1282 track->cb_color_bo[tmp] = reloc->robj;
1283 track->cb_color_bo_mc[tmp] = reloc->gpu_offset;
1284 track->cb_dirty = true;
1293 track->db_offset = radeon_get_ib_value(p, idx) << 8;
1295 track->db_bo = reloc->robj;
1296 track->db_bo_mc = reloc->gpu_offset;
1297 track->db_dirty = true;
1306 track->htile_offset = (u64)radeon_get_ib_value(p, idx) << 8;
1308 track->htile_bo = reloc->robj;
1309 track->db_dirty = true;
1312 track->htile_surface = radeon_get_ib_value(p, idx);
1315 track->db_dirty = true;
1388 track->sx_misc_kill_all_prims = (radeon_get_ib_value(p, idx) & 0x1) != 0;
1474 struct r600_cs_track *track = p->track;
1514 array_check.group_size = track->group_size;
1515 array_check.nbanks = track->nbanks;
1516 array_check.npipes = track->npipes;
1628 struct r600_cs_track *track;
1636 track = (struct r600_cs_track *)p->track;
2022 if (track->sq_config & DX9_CONSTS) {
2100 if (reloc->robj != track->vgt_strmout_bo[idx_value]) {
2106 if (offset != track->vgt_strmout_bo_offset[idx_value]) {
2108 offset, track->vgt_strmout_bo_offset[idx_value]);
2269 struct r600_cs_track *track;
2272 if (p->track == NULL) {
2274 track = kzalloc(sizeof(*track), GFP_KERNEL);
2275 if (track == NULL)
2277 r600_cs_track_init(track);
2279 track->npipes = p->rdev->config.r600.tiling_npipes;
2280 track->nbanks = p->rdev->config.r600.tiling_nbanks;
2281 track->group_size = p->rdev->config.r600.tiling_group_size;
2283 track->npipes = p->rdev->config.rv770.tiling_npipes;
2284 track->nbanks = p->rdev->config.rv770.tiling_nbanks;
2285 track->group_size = p->rdev->config.rv770.tiling_group_size;
2287 p->track = track;
2292 kfree(p->track);
2293 p->track = NULL;
2308 kfree(p->track);
2309 p->track = NULL;
2313 kfree(p->track);
2314 p->track = NULL;
2324 kfree(p->track);
2325 p->track = NULL;