Lines Matching defs:tmp
353 u32 slice_tile_max, tmp;
429 tmp = r600_fmt_get_nblocksy(format, height) * r600_fmt_get_nblocksx(format, pitch) *
435 tmp += track->cb_color_view[i] & 0xFF;
439 tmp += G_028080_SLICE_MAX(track->cb_color_view[i]) * tmp;
442 if ((tmp + track->cb_color_bo_offset[i]) > radeon_bo_size(track->cb_color_bo[i])) {
453 track->cb_color_bo_offset[i], tmp,
462 tmp = (height * pitch) >> 6;
463 if (tmp < slice_tile_max)
464 slice_tile_max = tmp;
465 tmp = S_028060_PITCH_TILE_MAX((pitch / 8) - 1) |
467 ib[track->cb_color_size_idx[i]] = tmp;
519 u32 nviews, bpe, ntiles, slice_tile_max, tmp;
556 tmp = radeon_bo_size(track->db_bo) - track->db_offset;
557 tmp = (tmp / bpe) >> 6;
558 if (!tmp) {
564 ib[track->db_depth_size_idx] = S_028000_SLICE_TILE_MAX(tmp - 1) | (track->db_depth_size & 0x3FF);
620 tmp = ntiles * bpe * 64 * nviews * track->nsamples;
621 if ((tmp + track->db_offset) > radeon_bo_size(track->db_bo)) {
624 track->db_depth_size, ntiles, nviews, bpe, tmp + track->db_offset,
707 u32 tmp;
743 tmp = track->cb_target_mask;
747 tmp |= 0xff;
754 (tmp >> (i * 4)) & 0xF) {
971 u32 m, i, tmp, *ib;
1006 /*tmp =radeon_get_ib_value(p, idx);
1081 tmp = (reg - VGT_STRMOUT_BUFFER_BASE_0) / 16;
1082 track->vgt_strmout_bo_offset[tmp] = radeon_get_ib_value(p, idx) << 8;
1084 track->vgt_strmout_bo[tmp] = reloc->robj;
1085 track->vgt_strmout_bo_mc[tmp] = reloc->gpu_offset;
1092 tmp = (reg - VGT_STRMOUT_BUFFER_SIZE_0) / 16;
1094 track->vgt_strmout_size[tmp] = radeon_get_ib_value(p, idx) * 4;
1114 tmp = G_028C04_MSAA_NUM_SAMPLES(radeon_get_ib_value(p, idx));
1115 track->log_nsamples = tmp;
1116 track->nsamples = 1 << tmp;
1120 tmp = G_028808_SPECIAL_OP(radeon_get_ib_value(p, idx));
1121 track->is_resolve = tmp == V_028808_SPECIAL_RESOLVE_BOX;
1139 tmp = (reg - R_0280A0_CB_COLOR0_INFO) / 4;
1140 track->cb_color_info[tmp] = radeon_get_ib_value(p, idx);
1143 track->cb_color_info[tmp] |= S_0280A0_ARRAY_MODE(V_0280A0_ARRAY_2D_TILED_THIN1);
1146 track->cb_color_info[tmp] |= S_0280A0_ARRAY_MODE(V_0280A0_ARRAY_1D_TILED_THIN1);
1149 tmp = (reg - R_0280A0_CB_COLOR0_INFO) / 4;
1150 track->cb_color_info[tmp] = radeon_get_ib_value(p, idx);
1162 tmp = (reg - R_028080_CB_COLOR0_VIEW) / 4;
1163 track->cb_color_view[tmp] = radeon_get_ib_value(p, idx);
1174 tmp = (reg - R_028060_CB_COLOR0_SIZE) / 4;
1175 track->cb_color_size[tmp] = radeon_get_ib_value(p, idx);
1176 track->cb_color_size_idx[tmp] = idx;
1196 tmp = (reg - R_0280E0_CB_COLOR0_FRAG) / 4;
1198 if (!track->cb_color_base_last[tmp]) {
1202 track->cb_color_frag_bo[tmp] = track->cb_color_bo[tmp];
1203 track->cb_color_frag_offset[tmp] = track->cb_color_bo_offset[tmp];
1204 ib[idx] = track->cb_color_base_last[tmp];
1211 track->cb_color_frag_bo[tmp] = reloc->robj;
1212 track->cb_color_frag_offset[tmp] = (u64)ib[idx] << 8;
1215 if (G_0280A0_TILE_MODE(track->cb_color_info[tmp])) {
1227 tmp = (reg - R_0280C0_CB_COLOR0_TILE) / 4;
1229 if (!track->cb_color_base_last[tmp]) {
1233 track->cb_color_tile_bo[tmp] = track->cb_color_bo[tmp];
1234 track->cb_color_tile_offset[tmp] = track->cb_color_bo_offset[tmp];
1235 ib[idx] = track->cb_color_base_last[tmp];
1242 track->cb_color_tile_bo[tmp] = reloc->robj;
1243 track->cb_color_tile_offset[tmp] = (u64)ib[idx] << 8;
1246 if (G_0280A0_TILE_MODE(track->cb_color_info[tmp])) {
1258 tmp = (reg - R_028100_CB_COLOR0_MASK) / 4;
1259 track->cb_color_mask[tmp] = radeon_get_ib_value(p, idx);
1260 if (G_0280A0_TILE_MODE(track->cb_color_info[tmp])) {
1278 tmp = (reg - CB_COLOR0_BASE) / 4;
1279 track->cb_color_bo_offset[tmp] = (u64)radeon_get_ib_value(p, idx) << 8;
1281 track->cb_color_base_last[tmp] = ib[idx];
1282 track->cb_color_bo[tmp] = reloc->robj;
1283 track->cb_color_bo_mc[tmp] = reloc->gpu_offset;
1645 int tmp;
1653 tmp = radeon_get_ib_value(p, idx + 1);
1654 pred_op = (tmp >> 16) & 0x7;
1673 ((u64)(tmp & 0xff) << 32);
1676 ib[idx + 1] = (tmp & 0xffffff00) | (upper_32_bits(offset) & 0xff);
1778 u64 offset, tmp;
1801 tmp = radeon_get_ib_value(p, idx) +
1804 offset = reloc->gpu_offset + tmp;
1806 if ((tmp + size) > radeon_bo_size(reloc->robj)) {
1808 tmp + size, radeon_bo_size(reloc->robj));
1831 tmp = radeon_get_ib_value(p, idx+2) +
1834 offset = reloc->gpu_offset + tmp;
1836 if ((tmp + size) > radeon_bo_size(reloc->robj)) {
1838 tmp + size, radeon_bo_size(reloc->robj));