Lines Matching defs:offset
423 dev_warn(p->dev, "%s offset[%d] 0x%llx 0x%llx, %d not aligned\n", __func__, i,
428 /* check offset */
451 dev_warn(p->dev, "%s offset[%d] %d %llu %d %lu too big (%d %d) (%d %d %d)\n",
483 "(tile_max=%u, bytes=%u, offset=%llu, bo_size=%lu)\n",
501 "(block_max=%u, bytes=%u, offset=%llu, bo_size=%lu)\n",
613 dev_warn(p->dev, "%s offset 0x%llx, 0x%llx, %d not aligned\n", __func__,
719 u64 offset = (u64)track->vgt_strmout_bo_offset[i] +
721 if (offset > radeon_bo_size(track->vgt_strmout_bo[i])) {
723 i, offset,
1181 * 0 offset. In order to avoid breaking old userspace
1412 unsigned offset, i, level;
1424 for(i = 0, offset = 0, level = blevel; i < nlevels; i++, level++) {
1446 offset = round_up(offset, base_align);
1448 offset += size;
1450 *mipmap_size = offset;
1568 dev_warn(p->dev, "%s:%d tex base offset (0x%llx, 0x%llx, %d) invalid\n",
1573 dev_warn(p->dev, "%s:%d tex mip offset (0x%llx, 0x%llx, %d) invalid\n",
1591 /* using get ib will give us the offset into the texture bo */
1600 /* using get ib will give us the offset into the mipmap bo */
1646 uint64_t offset;
1671 offset = reloc->gpu_offset +
1675 ib[idx + 0] = offset;
1676 ib[idx + 1] = (tmp & 0xffffff00) | (upper_32_bits(offset) & 0xff);
1701 uint64_t offset;
1712 offset = reloc->gpu_offset +
1716 ib[idx+0] = offset;
1717 ib[idx+1] = upper_32_bits(offset) & 0xff;
1756 uint64_t offset;
1764 offset = reloc->gpu_offset +
1768 ib[idx+1] = (ib[idx+1] & 0x3) | (offset & 0xfffffff0);
1769 ib[idx+2] = upper_32_bits(offset) & 0xff;
1778 u64 offset, tmp;
1804 offset = reloc->gpu_offset + tmp;
1812 ib[idx] = offset;
1813 ib[idx+1] = (ib[idx+1] & 0xffffff00) | (upper_32_bits(offset) & 0xff);
1834 offset = reloc->gpu_offset + tmp;
1842 ib[idx+2] = offset;
1843 ib[idx+3] = upper_32_bits(offset) & 0xff;
1869 uint64_t offset;
1876 offset = reloc->gpu_offset +
1880 ib[idx+1] = offset & 0xfffffff8;
1881 ib[idx+2] = upper_32_bits(offset) & 0xff;
1886 uint64_t offset;
1898 offset = reloc->gpu_offset +
1902 ib[idx+1] = offset & 0xfffffffc;
1903 ib[idx+2] = (ib[idx+2] & 0xffffff00) | (upper_32_bits(offset) & 0xff);
1953 u32 size, offset, base_offset, mip_offset;
1998 offset = radeon_get_ib_value(p, idx+1+(i*7)+0);
2000 if (p->rdev && (size + offset) > radeon_bo_size(reloc->robj)) {
2003 size + offset, radeon_bo_size(reloc->robj));
2004 ib[idx+1+(i*7)+1] = radeon_bo_size(reloc->robj) - offset;
2007 offset64 = reloc->gpu_offset + offset;
2092 u64 offset;
2105 offset = radeon_get_ib_value(p, idx+1) << 8;
2106 if (offset != track->vgt_strmout_bo_offset[idx_value]) {
2107 DRM_ERROR("bad STRMOUT_BASE_UPDATE, bo offset does not match: 0x%llx, 0x%x\n",
2108 offset, track->vgt_strmout_bo_offset[idx_value]);
2112 if ((offset + 4) > radeon_bo_size(reloc->robj)) {
2114 offset + 4, radeon_bo_size(reloc->robj));
2137 u64 offset;
2143 offset = radeon_get_ib_value(p, idx+1);
2144 offset += ((u64)(radeon_get_ib_value(p, idx+2) & 0xff)) << 32;
2145 if ((offset + 4) > radeon_bo_size(reloc->robj)) {
2147 offset + 4, radeon_bo_size(reloc->robj));
2150 offset += reloc->gpu_offset;
2151 ib[idx+1] = offset;
2152 ib[idx+2] = upper_32_bits(offset) & 0xff;
2156 u64 offset;
2162 offset = radeon_get_ib_value(p, idx+3);
2163 offset += ((u64)(radeon_get_ib_value(p, idx+4) & 0xff)) << 32;
2164 if ((offset + 4) > radeon_bo_size(reloc->robj)) {
2166 offset + 4, radeon_bo_size(reloc->robj));
2169 offset += reloc->gpu_offset;
2170 ib[idx+3] = offset;
2171 ib[idx+4] = upper_32_bits(offset) & 0xff;
2176 u64 offset;
2187 offset = radeon_get_ib_value(p, idx+0);
2188 offset += ((u64)(radeon_get_ib_value(p, idx+1) & 0xff)) << 32UL;
2189 if (offset & 0x7) {
2193 if ((offset + 8) > radeon_bo_size(reloc->robj)) {
2195 offset + 8, radeon_bo_size(reloc->robj));
2198 offset += reloc->gpu_offset;
2199 ib[idx+0] = offset;
2200 ib[idx+1] = upper_32_bits(offset) & 0xff;
2209 u64 offset;
2216 offset = radeon_get_ib_value(p, idx+1);
2217 offset += ((u64)(radeon_get_ib_value(p, idx+2) & 0xff)) << 32;
2218 if ((offset + 4) > radeon_bo_size(reloc->robj)) {
2220 offset + 4, radeon_bo_size(reloc->robj));
2223 offset += reloc->gpu_offset;
2224 ib[idx+1] = offset;
2225 ib[idx+2] = upper_32_bits(offset) & 0xff;
2233 u64 offset;
2240 offset = radeon_get_ib_value(p, idx+3);
2241 offset += ((u64)(radeon_get_ib_value(p, idx+4) & 0xff)) << 32;
2242 if ((offset + 4) > radeon_bo_size(reloc->robj)) {
2244 offset + 4, radeon_bo_size(reloc->robj));
2247 offset += reloc->gpu_offset;
2248 ib[idx+3] = offset;
2249 ib[idx+4] = upper_32_bits(offset) & 0xff;
2338 * GPU offset using the provided start.