Lines Matching refs:rdev
106 int r600_debugfs_mc_info_init(struct radeon_device *rdev);
109 int r600_mc_wait_for_idle(struct radeon_device *rdev);
110 static void r600_gpu_init(struct radeon_device *rdev);
111 void r600_fini(struct radeon_device *rdev);
112 void r600_irq_disable(struct radeon_device *rdev);
113 static void r600_pcie_gen2_enable(struct radeon_device *rdev);
114 extern int evergreen_rlc_resume(struct radeon_device *rdev);
115 extern void rv770_set_clk_bypass_mode(struct radeon_device *rdev);
120 u32 r600_rcu_rreg(struct radeon_device *rdev, u32 reg)
125 spin_lock_irqsave(&rdev->rcu_idx_lock, flags);
128 spin_unlock_irqrestore(&rdev->rcu_idx_lock, flags);
132 void r600_rcu_wreg(struct radeon_device *rdev, u32 reg, u32 v)
136 spin_lock_irqsave(&rdev->rcu_idx_lock, flags);
139 spin_unlock_irqrestore(&rdev->rcu_idx_lock, flags);
142 u32 r600_uvd_ctx_rreg(struct radeon_device *rdev, u32 reg)
147 spin_lock_irqsave(&rdev->uvd_idx_lock, flags);
150 spin_unlock_irqrestore(&rdev->uvd_idx_lock, flags);
154 void r600_uvd_ctx_wreg(struct radeon_device *rdev, u32 reg, u32 v)
158 spin_lock_irqsave(&rdev->uvd_idx_lock, flags);
161 spin_unlock_irqrestore(&rdev->uvd_idx_lock, flags);
167 * @rdev: radeon_device pointer
174 int r600_get_allowed_info_register(struct radeon_device *rdev,
193 * @rdev: radeon_device pointer
198 u32 r600_get_xclk(struct radeon_device *rdev)
200 return rdev->clock.spll.reference_freq;
203 int r600_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk)
217 if (rdev->family >= CHIP_RS780)
227 if (rdev->clock.spll.reference_freq == 10000)
232 r = radeon_uvd_calc_upll_dividers(rdev, vclk, dclk, 50000, 160000,
238 if (rdev->family >= CHIP_RV670 && rdev->family < CHIP_RS780)
243 r = radeon_uvd_send_upll_ctlreq(rdev, CG_UPLL_FUNC_CNTL);
251 if (rdev->family >= CHIP_RS780)
279 if (rdev->family >= CHIP_RS780)
282 r = radeon_uvd_send_upll_ctlreq(rdev, CG_UPLL_FUNC_CNTL);
299 struct radeon_device *rdev = dev->dev_private;
350 int rv6xx_get_temp(struct radeon_device *rdev)
362 void r600_pm_get_dynpm_state(struct radeon_device *rdev)
366 rdev->pm.dynpm_can_upclock = true;
367 rdev->pm.dynpm_can_downclock = true;
370 if ((rdev->flags & RADEON_IS_IGP) || (rdev->family == CHIP_R600)) {
373 if (rdev->pm.num_power_states > 2)
376 switch (rdev->pm.dynpm_planned_action) {
378 rdev->pm.requested_power_state_index = min_power_state_index;
379 rdev->pm.requested_clock_mode_index = 0;
380 rdev->pm.dynpm_can_downclock = false;
383 if (rdev->pm.current_power_state_index == min_power_state_index) {
384 rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index;
385 rdev->pm.dynpm_can_downclock = false;
387 if (rdev->pm.active_crtc_count > 1) {
388 for (i = 0; i < rdev->pm.num_power_states; i++) {
389 if (rdev->pm.power_state[i].flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY)
391 else if (i >= rdev->pm.current_power_state_index) {
392 rdev->pm.requested_power_state_index =
393 rdev->pm.current_power_state_index;
396 rdev->pm.requested_power_state_index = i;
401 if (rdev->pm.current_power_state_index == 0)
402 rdev->pm.requested_power_state_index =
403 rdev->pm.num_power_states - 1;
405 rdev->pm.requested_power_state_index =
406 rdev->pm.current_power_state_index - 1;
409 rdev->pm.requested_clock_mode_index = 0;
411 if ((rdev->pm.active_crtc_count > 0) &&
412 (rdev->pm.power_state[rdev->pm.requested_power_state_index].
413 clock_info[rdev->pm.requested_clock_mode_index].flags &
415 rdev->pm.requested_power_state_index++;
419 if (rdev->pm.current_power_state_index == (rdev->pm.num_power_states - 1)) {
420 rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index;
421 rdev->pm.dynpm_can_upclock = false;
423 if (rdev->pm.active_crtc_count > 1) {
424 for (i = (rdev->pm.num_power_states - 1); i >= 0; i--) {
425 if (rdev->pm.power_state[i].flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY)
427 else if (i <= rdev->pm.current_power_state_index) {
428 rdev->pm.requested_power_state_index =
429 rdev->pm.current_power_state_index;
432 rdev->pm.requested_power_state_index = i;
437 rdev->pm.requested_power_state_index =
438 rdev->pm.current_power_state_index + 1;
440 rdev->pm.requested_clock_mode_index = 0;
443 rdev->pm.requested_power_state_index = rdev->pm.default_power_state_index;
444 rdev->pm.requested_clock_mode_index = 0;
445 rdev->pm.dynpm_can_upclock = false;
456 if (rdev->pm.active_crtc_count > 1) {
457 rdev->pm.requested_power_state_index = -1;
459 for (i = 1; i < rdev->pm.num_power_states; i++) {
460 if (rdev->pm.power_state[i].flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY)
462 else if ((rdev->pm.power_state[i].type == POWER_STATE_TYPE_PERFORMANCE) ||
463 (rdev->pm.power_state[i].type == POWER_STATE_TYPE_BATTERY)) {
464 rdev->pm.requested_power_state_index = i;
469 if (rdev->pm.requested_power_state_index == -1)
470 rdev->pm.requested_power_state_index = 0;
472 rdev->pm.requested_power_state_index = 1;
474 switch (rdev->pm.dynpm_planned_action) {
476 rdev->pm.requested_clock_mode_index = 0;
477 rdev->pm.dynpm_can_downclock = false;
480 if (rdev->pm.requested_power_state_index == rdev->pm.current_power_state_index) {
481 if (rdev->pm.current_clock_mode_index == 0) {
482 rdev->pm.requested_clock_mode_index = 0;
483 rdev->pm.dynpm_can_downclock = false;
485 rdev->pm.requested_clock_mode_index =
486 rdev->pm.current_clock_mode_index - 1;
488 rdev->pm.requested_clock_mode_index = 0;
489 rdev->pm.dynpm_can_downclock = false;
492 if ((rdev->pm.active_crtc_count > 0) &&
493 (rdev->pm.power_state[rdev->pm.requested_power_state_index].
494 clock_info[rdev->pm.requested_clock_mode_index].flags &
496 rdev->pm.requested_clock_mode_index++;
500 if (rdev->pm.requested_power_state_index == rdev->pm.current_power_state_index) {
501 if (rdev->pm.current_clock_mode_index ==
502 (rdev->pm.power_state[rdev->pm.requested_power_state_index].num_clock_modes - 1)) {
503 rdev->pm.requested_clock_mode_index = rdev->pm.current_clock_mode_index;
504 rdev->pm.dynpm_can_upclock = false;
506 rdev->pm.requested_clock_mode_index =
507 rdev->pm.current_clock_mode_index + 1;
509 rdev->pm.requested_clock_mode_index =
510 rdev->pm.power_state[rdev->pm.requested_power_state_index].num_clock_modes - 1;
511 rdev->pm.dynpm_can_upclock = false;
515 rdev->pm.requested_power_state_index = rdev->pm.default_power_state_index;
516 rdev->pm.requested_clock_mode_index = 0;
517 rdev->pm.dynpm_can_upclock = false;
527 rdev->pm.power_state[rdev->pm.requested_power_state_index].
528 clock_info[rdev->pm.requested_clock_mode_index].sclk,
529 rdev->pm.power_state[rdev->pm.requested_power_state_index].
530 clock_info[rdev->pm.requested_clock_mode_index].mclk,
531 rdev->pm.power_state[rdev->pm.requested_power_state_index].
535 void rs780_pm_init_profile(struct radeon_device *rdev)
537 if (rdev->pm.num_power_states == 2) {
539 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
540 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
541 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0;
542 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0;
544 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = 0;
545 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 0;
546 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
547 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
549 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = 0;
550 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = 0;
551 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
552 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0;
554 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 0;
555 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = 1;
556 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0;
557 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 0;
559 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = 0;
560 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = 0;
561 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
562 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
564 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = 0;
565 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = 0;
566 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
567 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0;
569 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 0;
570 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = 1;
571 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0;
572 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 0;
573 } else if (rdev->pm.num_power_states == 3) {
575 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
576 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
577 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0;
578 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0;
580 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = 1;
581 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 1;
582 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
583 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
585 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = 1;
586 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = 1;
587 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
588 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0;
590 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 1;
591 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = 2;
592 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0;
593 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 0;
595 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = 1;
596 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = 1;
597 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
598 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
600 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = 1;
601 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = 1;
602 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
603 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0;
605 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 1;
606 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = 2;
607 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0;
608 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 0;
611 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
612 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
613 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0;
614 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0;
616 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = 2;
617 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 2;
618 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
619 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
621 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = 2;
622 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = 2;
623 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
624 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0;
626 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 2;
627 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = 3;
628 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0;
629 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 0;
631 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = 2;
632 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = 0;
633 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
634 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
636 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = 2;
637 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = 0;
638 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
639 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0;
641 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 2;
642 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = 3;
643 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0;
644 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 0;
648 void r600_pm_init_profile(struct radeon_device *rdev)
652 if (rdev->family == CHIP_R600) {
655 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
656 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
657 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0;
658 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0;
660 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
661 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
662 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
663 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
665 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
666 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
667 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
668 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0;
670 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
671 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
672 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0;
673 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 0;
675 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
676 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
677 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
678 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
680 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
681 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
682 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
683 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0;
685 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
686 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
687 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0;
688 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 0;
690 if (rdev->pm.num_power_states < 4) {
692 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
693 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
694 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0;
695 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 2;
697 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = 1;
698 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 1;
699 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
700 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
702 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = 1;
703 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = 1;
704 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
705 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 1;
707 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 1;
708 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = 1;
709 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0;
710 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 2;
712 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = 2;
713 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = 2;
714 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
715 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
717 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = 2;
718 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = 2;
719 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
720 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 1;
722 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 2;
723 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = 2;
724 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0;
725 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 2;
728 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
729 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
730 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0;
731 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 2;
733 if (rdev->flags & RADEON_IS_MOBILITY)
734 idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_BATTERY, 0);
736 idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 0);
737 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = idx;
738 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = idx;
739 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
740 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
742 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = idx;
743 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = idx;
744 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
745 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 1;
747 idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 0);
748 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = idx;
749 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = idx;
750 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0;
751 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 2;
753 if (rdev->flags & RADEON_IS_MOBILITY)
754 idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_BATTERY, 1);
756 idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 1);
757 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = idx;
758 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = idx;
759 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
760 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
762 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = idx;
763 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = idx;
764 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
765 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 1;
767 idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 1);
768 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = idx;
769 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = idx;
770 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0;
771 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 2;
776 void r600_pm_misc(struct radeon_device *rdev)
778 int req_ps_idx = rdev->pm.requested_power_state_index;
779 int req_cm_idx = rdev->pm.requested_clock_mode_index;
780 struct radeon_power_state *ps = &rdev->pm.power_state[req_ps_idx];
787 if (voltage->voltage != rdev->pm.current_vddc) {
788 radeon_atom_set_voltage(rdev, voltage->voltage, SET_VOLTAGE_TYPE_ASIC_VDDC);
789 rdev->pm.current_vddc = voltage->voltage;
795 bool r600_gui_idle(struct radeon_device *rdev)
804 bool r600_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd)
808 if (ASIC_IS_DCE3(rdev)) {
859 void r600_hpd_set_polarity(struct radeon_device *rdev,
863 bool connected = r600_hpd_sense(rdev, hpd);
865 if (ASIC_IS_DCE3(rdev)) {
951 void r600_hpd_init(struct radeon_device *rdev)
953 struct drm_device *dev = rdev->ddev;
968 if (ASIC_IS_DCE3(rdev)) {
970 if (ASIC_IS_DCE32(rdev))
1013 radeon_hpd_set_polarity(rdev, radeon_connector->hpd.hpd);
1015 radeon_irq_kms_enable_hpd(rdev, enable);
1018 void r600_hpd_fini(struct radeon_device *rdev)
1020 struct drm_device *dev = rdev->ddev;
1026 if (ASIC_IS_DCE3(rdev)) {
1068 radeon_irq_kms_disable_hpd(rdev, disable);
1074 void r600_pcie_gart_tlb_flush(struct radeon_device *rdev)
1080 if ((rdev->family >= CHIP_RV770) && (rdev->family <= CHIP_RV740) &&
1081 !(rdev->flags & RADEON_IS_AGP)) {
1082 void __iomem *ptr = (void *)rdev->gart.ptr;
1095 WREG32(VM_CONTEXT0_INVALIDATION_LOW_ADDR, rdev->mc.gtt_start >> 12);
1096 WREG32(VM_CONTEXT0_INVALIDATION_HIGH_ADDR, (rdev->mc.gtt_end - 1) >> 12);
1098 for (i = 0; i < rdev->usec_timeout; i++) {
1113 int r600_pcie_gart_init(struct radeon_device *rdev)
1117 if (rdev->gart.robj) {
1122 r = radeon_gart_init(rdev);
1125 rdev->gart.table_size = rdev->gart.num_gpu_pages * 8;
1126 return radeon_gart_table_vram_alloc(rdev);
1129 static int r600_pcie_gart_enable(struct radeon_device *rdev)
1134 if (rdev->gart.robj == NULL) {
1135 dev_err(rdev->dev, "No VRAM object for PCIE GART.\n");
1138 r = radeon_gart_table_vram_pin(rdev);
1169 WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR, rdev->mc.gtt_start >> 12);
1170 WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR, rdev->mc.gtt_end >> 12);
1171 WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, rdev->gart.table_addr >> 12);
1175 (u32)(rdev->dummy_page.addr >> 12));
1179 r600_pcie_gart_tlb_flush(rdev);
1181 (unsigned)(rdev->mc.gtt_size >> 20),
1182 (unsigned long long)rdev->gart.table_addr);
1183 rdev->gart.ready = true;
1187 static void r600_pcie_gart_disable(struct radeon_device *rdev)
1219 radeon_gart_table_vram_unpin(rdev);
1222 static void r600_pcie_gart_fini(struct radeon_device *rdev)
1224 radeon_gart_fini(rdev);
1225 r600_pcie_gart_disable(rdev);
1226 radeon_gart_table_vram_free(rdev);
1229 static void r600_agp_enable(struct radeon_device *rdev)
1263 int r600_mc_wait_for_idle(struct radeon_device *rdev)
1268 for (i = 0; i < rdev->usec_timeout; i++) {
1278 uint32_t rs780_mc_rreg(struct radeon_device *rdev, uint32_t reg)
1283 spin_lock_irqsave(&rdev->mc_idx_lock, flags);
1287 spin_unlock_irqrestore(&rdev->mc_idx_lock, flags);
1291 void rs780_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
1295 spin_lock_irqsave(&rdev->mc_idx_lock, flags);
1300 spin_unlock_irqrestore(&rdev->mc_idx_lock, flags);
1303 static void r600_mc_program(struct radeon_device *rdev)
1319 rv515_mc_stop(rdev, &save);
1320 if (r600_mc_wait_for_idle(rdev)) {
1321 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
1326 if (rdev->flags & RADEON_IS_AGP) {
1327 if (rdev->mc.vram_start < rdev->mc.gtt_start) {
1330 rdev->mc.vram_start >> 12);
1332 rdev->mc.gtt_end >> 12);
1336 rdev->mc.gtt_start >> 12);
1338 rdev->mc.vram_end >> 12);
1341 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR, rdev->mc.vram_start >> 12);
1342 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR, rdev->mc.vram_end >> 12);
1344 WREG32(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR, rdev->vram_scratch.gpu_addr >> 12);
1345 tmp = ((rdev->mc.vram_end >> 24) & 0xFFFF) << 16;
1346 tmp |= ((rdev->mc.vram_start >> 24) & 0xFFFF);
1348 WREG32(HDP_NONSURFACE_BASE, (rdev->mc.vram_start >> 8));
1351 if (rdev->flags & RADEON_IS_AGP) {
1352 WREG32(MC_VM_AGP_TOP, rdev->mc.gtt_end >> 22);
1353 WREG32(MC_VM_AGP_BOT, rdev->mc.gtt_start >> 22);
1354 WREG32(MC_VM_AGP_BASE, rdev->mc.agp_base >> 22);
1360 if (r600_mc_wait_for_idle(rdev)) {
1361 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
1363 rv515_mc_resume(rdev, &save);
1366 rv515_vga_render_disable(rdev);
1371 * @rdev: radeon device structure holding all necessary informations
1390 static void r600_vram_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc)
1396 dev_warn(rdev->dev, "limiting VRAM\n");
1400 if (rdev->flags & RADEON_IS_AGP) {
1405 dev_warn(rdev->dev, "limiting VRAM\n");
1412 dev_warn(rdev->dev, "limiting VRAM\n");
1419 dev_info(rdev->dev, "VRAM: %lluM 0x%08llX - 0x%08llX (%lluM used)\n",
1424 if (rdev->flags & RADEON_IS_IGP) {
1428 radeon_vram_location(rdev, &rdev->mc, base);
1429 rdev->mc.gtt_base_align = 0;
1430 radeon_gtt_location(rdev, mc);
1434 static int r600_mc_init(struct radeon_device *rdev)
1442 rdev->mc.vram_is_ddr = true;
1467 rdev->mc.vram_width = numchan * chansize;
1469 rdev->mc.aper_base = pci_resource_start(rdev->pdev, 0);
1470 rdev->mc.aper_size = pci_resource_len(rdev->pdev, 0);
1472 rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE);
1473 rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE);
1474 rdev->mc.visible_vram_size = rdev->mc.aper_size;
1475 r600_vram_gtt_location(rdev, &rdev->mc);
1477 if (rdev->flags & RADEON_IS_IGP) {
1478 rs690_pm_info(rdev);
1479 rdev->mc.igp_sideport_enabled = radeon_atombios_sideport_present(rdev);
1481 if (rdev->family == CHIP_RS780 || rdev->family == CHIP_RS880) {
1483 rdev->fastfb_working = false;
1488 if (k8_addr + rdev->mc.visible_vram_size < 0x100000000ULL)
1494 if (rdev->mc.igp_sideport_enabled == false && radeon_fastfb == 1) {
1496 (unsigned long long)rdev->mc.aper_base, k8_addr);
1497 rdev->mc.aper_base = (resource_size_t)k8_addr;
1498 rdev->fastfb_working = true;
1504 radeon_update_bandwidth_info(rdev);
1508 int r600_vram_scratch_init(struct radeon_device *rdev)
1512 if (rdev->vram_scratch.robj == NULL) {
1513 r = radeon_bo_create(rdev, RADEON_GPU_PAGE_SIZE,
1515 0, NULL, NULL, &rdev->vram_scratch.robj);
1521 r = radeon_bo_reserve(rdev->vram_scratch.robj, false);
1524 r = radeon_bo_pin(rdev->vram_scratch.robj,
1525 RADEON_GEM_DOMAIN_VRAM, &rdev->vram_scratch.gpu_addr);
1527 radeon_bo_unreserve(rdev->vram_scratch.robj);
1530 r = radeon_bo_kmap(rdev->vram_scratch.robj,
1531 (void **)&rdev->vram_scratch.ptr);
1533 radeon_bo_unpin(rdev->vram_scratch.robj);
1534 radeon_bo_unreserve(rdev->vram_scratch.robj);
1539 void r600_vram_scratch_fini(struct radeon_device *rdev)
1543 if (rdev->vram_scratch.robj == NULL) {
1546 r = radeon_bo_reserve(rdev->vram_scratch.robj, false);
1548 radeon_bo_kunmap(rdev->vram_scratch.robj);
1549 radeon_bo_unpin(rdev->vram_scratch.robj);
1550 radeon_bo_unreserve(rdev->vram_scratch.robj);
1552 radeon_bo_unref(&rdev->vram_scratch.robj);
1555 void r600_set_bios_scratch_engine_hung(struct radeon_device *rdev, bool hung)
1567 static void r600_print_gpu_status_regs(struct radeon_device *rdev)
1569 dev_info(rdev->dev, " R_008010_GRBM_STATUS = 0x%08X\n",
1571 dev_info(rdev->dev, " R_008014_GRBM_STATUS2 = 0x%08X\n",
1573 dev_info(rdev->dev, " R_000E50_SRBM_STATUS = 0x%08X\n",
1575 dev_info(rdev->dev, " R_008674_CP_STALLED_STAT1 = 0x%08X\n",
1577 dev_info(rdev->dev, " R_008678_CP_STALLED_STAT2 = 0x%08X\n",
1579 dev_info(rdev->dev, " R_00867C_CP_BUSY_STAT = 0x%08X\n",
1581 dev_info(rdev->dev, " R_008680_CP_STAT = 0x%08X\n",
1583 dev_info(rdev->dev, " R_00D034_DMA_STATUS_REG = 0x%08X\n",
1587 static bool r600_is_display_hung(struct radeon_device *rdev)
1593 for (i = 0; i < rdev->num_crtc; i++) {
1601 for (i = 0; i < rdev->num_crtc; i++) {
1616 u32 r600_gpu_check_soft_reset(struct radeon_device *rdev)
1623 if (rdev->family >= CHIP_RV770) {
1673 if (r600_is_display_hung(rdev))
1685 static void r600_gpu_soft_reset(struct radeon_device *rdev, u32 reset_mask)
1694 dev_info(rdev->dev, "GPU softreset: 0x%08X\n", reset_mask);
1696 r600_print_gpu_status_regs(rdev);
1699 if (rdev->family >= CHIP_RV770)
1716 rv515_mc_stop(rdev, &save);
1717 if (r600_mc_wait_for_idle(rdev)) {
1718 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
1722 if (rdev->family >= CHIP_RV770)
1758 if (rdev->family >= CHIP_RV770)
1776 if (!(rdev->flags & RADEON_IS_IGP)) {
1787 dev_info(rdev->dev, "R_008020_GRBM_SOFT_RESET=0x%08X\n", tmp);
1801 dev_info(rdev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
1815 rv515_mc_resume(rdev, &save);
1818 r600_print_gpu_status_regs(rdev);
1821 static void r600_gpu_pci_config_reset(struct radeon_device *rdev)
1826 dev_info(rdev->dev, "GPU pci config reset\n");
1831 if (rdev->family >= CHIP_RV770)
1847 if (rdev->family >= CHIP_RV770)
1848 rv770_set_clk_bypass_mode(rdev);
1850 pci_clear_master(rdev->pdev);
1852 rv515_mc_stop(rdev, &save);
1853 if (r600_mc_wait_for_idle(rdev)) {
1854 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
1865 radeon_pci_config_reset(rdev);
1875 for (i = 0; i < rdev->usec_timeout; i++) {
1882 int r600_asic_reset(struct radeon_device *rdev, bool hard)
1887 r600_gpu_pci_config_reset(rdev);
1891 reset_mask = r600_gpu_check_soft_reset(rdev);
1894 r600_set_bios_scratch_engine_hung(rdev, true);
1897 r600_gpu_soft_reset(rdev, reset_mask);
1899 reset_mask = r600_gpu_check_soft_reset(rdev);
1903 r600_gpu_pci_config_reset(rdev);
1905 reset_mask = r600_gpu_check_soft_reset(rdev);
1908 r600_set_bios_scratch_engine_hung(rdev, false);
1916 * @rdev: radeon_device pointer
1922 bool r600_gfx_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring)
1924 u32 reset_mask = r600_gpu_check_soft_reset(rdev);
1929 radeon_ring_lockup_update(rdev, ring);
1932 return radeon_ring_test_lockup(rdev, ring);
1935 u32 r6xx_remap_render_backend(struct radeon_device *rdev,
1959 if (rdev->family <= CHIP_RV740) {
1990 static void r600_gpu_init(struct radeon_device *rdev)
2005 rdev->config.r600.tiling_group_size = 256;
2006 switch (rdev->family) {
2008 rdev->config.r600.max_pipes = 4;
2009 rdev->config.r600.max_tile_pipes = 8;
2010 rdev->config.r600.max_simds = 4;
2011 rdev->config.r600.max_backends = 4;
2012 rdev->config.r600.max_gprs = 256;
2013 rdev->config.r600.max_threads = 192;
2014 rdev->config.r600.max_stack_entries = 256;
2015 rdev->config.r600.max_hw_contexts = 8;
2016 rdev->config.r600.max_gs_threads = 16;
2017 rdev->config.r600.sx_max_export_size = 128;
2018 rdev->config.r600.sx_max_export_pos_size = 16;
2019 rdev->config.r600.sx_max_export_smx_size = 128;
2020 rdev->config.r600.sq_num_cf_insts = 2;
2024 rdev->config.r600.max_pipes = 2;
2025 rdev->config.r600.max_tile_pipes = 2;
2026 rdev->config.r600.max_simds = 3;
2027 rdev->config.r600.max_backends = 1;
2028 rdev->config.r600.max_gprs = 128;
2029 rdev->config.r600.max_threads = 192;
2030 rdev->config.r600.max_stack_entries = 128;
2031 rdev->config.r600.max_hw_contexts = 8;
2032 rdev->config.r600.max_gs_threads = 4;
2033 rdev->config.r600.sx_max_export_size = 128;
2034 rdev->config.r600.sx_max_export_pos_size = 16;
2035 rdev->config.r600.sx_max_export_smx_size = 128;
2036 rdev->config.r600.sq_num_cf_insts = 2;
2042 rdev->config.r600.max_pipes = 1;
2043 rdev->config.r600.max_tile_pipes = 1;
2044 rdev->config.r600.max_simds = 2;
2045 rdev->config.r600.max_backends = 1;
2046 rdev->config.r600.max_gprs = 128;
2047 rdev->config.r600.max_threads = 192;
2048 rdev->config.r600.max_stack_entries = 128;
2049 rdev->config.r600.max_hw_contexts = 4;
2050 rdev->config.r600.max_gs_threads = 4;
2051 rdev->config.r600.sx_max_export_size = 128;
2052 rdev->config.r600.sx_max_export_pos_size = 16;
2053 rdev->config.r600.sx_max_export_smx_size = 128;
2054 rdev->config.r600.sq_num_cf_insts = 1;
2057 rdev->config.r600.max_pipes = 4;
2058 rdev->config.r600.max_tile_pipes = 4;
2059 rdev->config.r600.max_simds = 4;
2060 rdev->config.r600.max_backends = 4;
2061 rdev->config.r600.max_gprs = 192;
2062 rdev->config.r600.max_threads = 192;
2063 rdev->config.r600.max_stack_entries = 256;
2064 rdev->config.r600.max_hw_contexts = 8;
2065 rdev->config.r600.max_gs_threads = 16;
2066 rdev->config.r600.sx_max_export_size = 128;
2067 rdev->config.r600.sx_max_export_pos_size = 16;
2068 rdev->config.r600.sx_max_export_smx_size = 128;
2069 rdev->config.r600.sq_num_cf_insts = 2;
2089 switch (rdev->config.r600.max_tile_pipes) {
2105 rdev->config.r600.tiling_npipes = rdev->config.r600.max_tile_pipes;
2106 rdev->config.r600.tiling_nbanks = 4 << ((ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT);
2121 tmp = rdev->config.r600.max_simds -
2123 rdev->config.r600.active_simds = tmp;
2127 for (i = 0; i < rdev->config.r600.max_backends; i++)
2131 for (i = 0; i < rdev->config.r600.max_backends; i++)
2135 tmp = r6xx_remap_render_backend(rdev, tmp, rdev->config.r600.max_backends,
2138 rdev->config.r600.backend_map = tmp;
2140 rdev->config.r600.tile_config = tiling_config;
2157 if (rdev->family == CHIP_RV670)
2162 if ((rdev->family > CHIP_R600))
2166 if (((rdev->family) == CHIP_R600) ||
2167 ((rdev->family) == CHIP_RV630) ||
2168 ((rdev->family) == CHIP_RV610) ||
2169 ((rdev->family) == CHIP_RV620) ||
2170 ((rdev->family) == CHIP_RS780) ||
2171 ((rdev->family) == CHIP_RS880)) {
2186 if (((rdev->family) == CHIP_RV610) ||
2187 ((rdev->family) == CHIP_RV620) ||
2188 ((rdev->family) == CHIP_RS780) ||
2189 ((rdev->family) == CHIP_RS880)) {
2194 } else if (((rdev->family) == CHIP_R600) ||
2195 ((rdev->family) == CHIP_RV630)) {
2216 if ((rdev->family) == CHIP_R600) {
2230 } else if (((rdev->family) == CHIP_RV610) ||
2231 ((rdev->family) == CHIP_RV620) ||
2232 ((rdev->family) == CHIP_RS780) ||
2233 ((rdev->family) == CHIP_RS880)) {
2250 } else if (((rdev->family) == CHIP_RV630) ||
2251 ((rdev->family) == CHIP_RV635)) {
2265 } else if ((rdev->family) == CHIP_RV670) {
2288 if (((rdev->family) == CHIP_RV610) ||
2289 ((rdev->family) == CHIP_RV620) ||
2290 ((rdev->family) == CHIP_RS780) ||
2291 ((rdev->family) == CHIP_RS880)) {
2314 tmp = rdev->config.r600.max_pipes * 16;
2315 switch (rdev->family) {
2358 switch (rdev->family) {
2396 u32 r600_pciep_rreg(struct radeon_device *rdev, u32 reg)
2401 spin_lock_irqsave(&rdev->pciep_idx_lock, flags);
2405 spin_unlock_irqrestore(&rdev->pciep_idx_lock, flags);
2409 void r600_pciep_wreg(struct radeon_device *rdev, u32 reg, u32 v)
2413 spin_lock_irqsave(&rdev->pciep_idx_lock, flags);
2418 spin_unlock_irqrestore(&rdev->pciep_idx_lock, flags);
2424 void r600_cp_stop(struct radeon_device *rdev)
2426 if (rdev->asic->copy.copy_ring_index == RADEON_RING_TYPE_GFX_INDEX)
2427 radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size);
2430 rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = false;
2433 int r600_init_microcode(struct radeon_device *rdev)
2444 switch (rdev->family) {
2538 if (rdev->family >= CHIP_CEDAR) {
2542 } else if (rdev->family >= CHIP_RV770) {
2555 err = request_firmware(&rdev->pfp_fw, fw_name, rdev->dev);
2558 if (rdev->pfp_fw->size != pfp_req_size) {
2560 rdev->pfp_fw->size, fw_name);
2566 err = request_firmware(&rdev->me_fw, fw_name, rdev->dev);
2569 if (rdev->me_fw->size != me_req_size) {
2571 rdev->me_fw->size, fw_name);
2576 err = request_firmware(&rdev->rlc_fw, fw_name, rdev->dev);
2579 if (rdev->rlc_fw->size != rlc_req_size) {
2581 rdev->rlc_fw->size, fw_name);
2585 if ((rdev->family >= CHIP_RV770) && (rdev->family <= CHIP_HEMLOCK)) {
2587 err = request_firmware(&rdev->smc_fw, fw_name, rdev->dev);
2590 release_firmware(rdev->smc_fw);
2591 rdev->smc_fw = NULL;
2593 } else if (rdev->smc_fw->size != smc_req_size) {
2595 rdev->smc_fw->size, fw_name);
2605 release_firmware(rdev->pfp_fw);
2606 rdev->pfp_fw = NULL;
2607 release_firmware(rdev->me_fw);
2608 rdev->me_fw = NULL;
2609 release_firmware(rdev->rlc_fw);
2610 rdev->rlc_fw = NULL;
2611 release_firmware(rdev->smc_fw);
2612 rdev->smc_fw = NULL;
2617 u32 r600_gfx_get_rptr(struct radeon_device *rdev,
2622 if (rdev->wb.enabled)
2623 rptr = rdev->wb.wb[ring->rptr_offs/4];
2630 u32 r600_gfx_get_wptr(struct radeon_device *rdev,
2636 void r600_gfx_set_wptr(struct radeon_device *rdev,
2643 static int r600_cp_load_microcode(struct radeon_device *rdev)
2648 if (!rdev->me_fw || !rdev->pfp_fw)
2651 r600_cp_stop(rdev);
2667 fw_data = (const __be32 *)rdev->me_fw->data;
2673 fw_data = (const __be32 *)rdev->pfp_fw->data;
2685 int r600_cp_start(struct radeon_device *rdev)
2687 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
2691 r = radeon_ring_lock(rdev, ring, 7);
2698 if (rdev->family >= CHIP_RV770) {
2700 radeon_ring_write(ring, rdev->config.rv770.max_hw_contexts - 1);
2703 radeon_ring_write(ring, rdev->config.r600.max_hw_contexts - 1);
2708 radeon_ring_unlock_commit(rdev, ring, false);
2715 int r600_cp_resume(struct radeon_device *rdev)
2717 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
2748 ((rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFFFFFFFC));
2749 WREG32(CP_RB_RPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFF);
2750 WREG32(SCRATCH_ADDR, ((rdev->wb.gpu_addr + RADEON_WB_SCRATCH_OFFSET) >> 8) & 0xFFFFFFFF);
2752 if (rdev->wb.enabled)
2765 r600_cp_start(rdev);
2767 r = radeon_ring_test(rdev, RADEON_RING_TYPE_GFX_INDEX, ring);
2773 if (rdev->asic->copy.copy_ring_index == RADEON_RING_TYPE_GFX_INDEX)
2774 radeon_ttm_set_active_vram_size(rdev, rdev->mc.real_vram_size);
2779 void r600_ring_init(struct radeon_device *rdev, struct radeon_ring *ring, unsigned ring_size)
2790 if (radeon_ring_supports_scratch_reg(rdev, ring)) {
2791 r = radeon_scratch_get(rdev, &ring->rptr_save_reg);
2799 void r600_cp_fini(struct radeon_device *rdev)
2801 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
2802 r600_cp_stop(rdev);
2803 radeon_ring_fini(rdev, ring);
2804 radeon_scratch_free(rdev, ring->rptr_save_reg);
2810 void r600_scratch_init(struct radeon_device *rdev)
2814 rdev->scratch.num_reg = 7;
2815 rdev->scratch.reg_base = SCRATCH_REG0;
2816 for (i = 0; i < rdev->scratch.num_reg; i++) {
2817 rdev->scratch.free[i] = true;
2818 rdev->scratch.reg[i] = rdev->scratch.reg_base + (i * 4);
2822 int r600_ring_test(struct radeon_device *rdev, struct radeon_ring *ring)
2829 r = radeon_scratch_get(rdev, &scratch);
2835 r = radeon_ring_lock(rdev, ring, 3);
2838 radeon_scratch_free(rdev, scratch);
2844 radeon_ring_unlock_commit(rdev, ring, false);
2845 for (i = 0; i < rdev->usec_timeout; i++) {
2851 if (i < rdev->usec_timeout) {
2858 radeon_scratch_free(rdev, scratch);
2866 void r600_fence_ring_emit(struct radeon_device *rdev,
2869 struct radeon_ring *ring = &rdev->ring[fence->ring];
2873 if (rdev->family >= CHIP_RV770)
2876 if (rdev->wb.use_event) {
2877 u64 addr = rdev->fence_drv[fence->ring].gpu_addr;
2906 radeon_ring_write(ring, ((rdev->fence_drv[fence->ring].scratch_reg - PACKET3_SET_CONFIG_REG_OFFSET) >> 2));
2917 * @rdev: radeon_device pointer
2925 bool r600_semaphore_ring_emit(struct radeon_device *rdev,
2933 if (rdev->family < CHIP_CAYMAN)
2941 if (emit_wait && (rdev->family >= CHIP_CEDAR)) {
2953 * @rdev: radeon_device pointer
2963 struct radeon_fence *r600_copy_cpdma(struct radeon_device *rdev,
2970 int ring_index = rdev->asic->copy.blit_ring_index;
2971 struct radeon_ring *ring = &rdev->ring[ring_index];
2980 r = radeon_ring_lock(rdev, ring, num_loops * 6 + 24);
2983 radeon_sync_free(rdev, &sync, NULL);
2987 radeon_sync_resv(rdev, &sync, resv, false);
2988 radeon_sync_rings(rdev, &sync, ring->idx);
3014 r = radeon_fence_emit(rdev, &fence, ring->idx);
3016 radeon_ring_unlock_undo(rdev, ring);
3017 radeon_sync_free(rdev, &sync, NULL);
3021 radeon_ring_unlock_commit(rdev, ring, false);
3022 radeon_sync_free(rdev, &sync, fence);
3027 int r600_set_surface_reg(struct radeon_device *rdev, int reg,
3035 void r600_clear_surface_reg(struct radeon_device *rdev, int reg)
3040 static void r600_uvd_init(struct radeon_device *rdev)
3044 if (!rdev->has_uvd)
3047 r = radeon_uvd_init(rdev);
3049 dev_err(rdev->dev, "failed UVD (%d) init.\n", r);
3051 * At this point rdev->uvd.vcpu_bo is NULL which trickles down
3056 rdev->has_uvd = false;
3059 rdev->ring[R600_RING_TYPE_UVD_INDEX].ring_obj = NULL;
3060 r600_ring_init(rdev, &rdev->ring[R600_RING_TYPE_UVD_INDEX], 4096);
3063 static void r600_uvd_start(struct radeon_device *rdev)
3067 if (!rdev->has_uvd)
3070 r = uvd_v1_0_resume(rdev);
3072 dev_err(rdev->dev, "failed UVD resume (%d).\n", r);
3075 r = radeon_fence_driver_start_ring(rdev, R600_RING_TYPE_UVD_INDEX);
3077 dev_err(rdev->dev, "failed initializing UVD fences (%d).\n", r);
3083 rdev->ring[R600_RING_TYPE_UVD_INDEX].ring_size = 0;
3086 static void r600_uvd_resume(struct radeon_device *rdev)
3091 if (!rdev->has_uvd || !rdev->ring[R600_RING_TYPE_UVD_INDEX].ring_size)
3094 ring = &rdev->ring[R600_RING_TYPE_UVD_INDEX];
3095 r = radeon_ring_init(rdev, ring, ring->ring_size, 0, PACKET0(UVD_NO_OP, 0));
3097 dev_err(rdev->dev, "failed initializing UVD ring (%d).\n", r);
3100 r = uvd_v1_0_init(rdev);
3102 dev_err(rdev->dev, "failed initializing UVD (%d).\n", r);
3107 static int r600_startup(struct radeon_device *rdev)
3113 r600_pcie_gen2_enable(rdev);
3116 r = r600_vram_scratch_init(rdev);
3120 r600_mc_program(rdev);
3122 if (rdev->flags & RADEON_IS_AGP) {
3123 r600_agp_enable(rdev);
3125 r = r600_pcie_gart_enable(rdev);
3129 r600_gpu_init(rdev);
3132 r = radeon_wb_init(rdev);
3136 r = radeon_fence_driver_start_ring(rdev, RADEON_RING_TYPE_GFX_INDEX);
3138 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r);
3142 r600_uvd_start(rdev);
3145 if (!rdev->irq.installed) {
3146 r = radeon_irq_kms_init(rdev);
3151 r = r600_irq_init(rdev);
3154 radeon_irq_kms_fini(rdev);
3157 r600_irq_set(rdev);
3159 ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
3160 r = radeon_ring_init(rdev, ring, ring->ring_size, RADEON_WB_CP_RPTR_OFFSET,
3165 r = r600_cp_load_microcode(rdev);
3168 r = r600_cp_resume(rdev);
3172 r600_uvd_resume(rdev);
3174 r = radeon_ib_pool_init(rdev);
3176 dev_err(rdev->dev, "IB initialization failed (%d).\n", r);
3180 r = radeon_audio_init(rdev);
3189 void r600_vga_set_state(struct radeon_device *rdev, bool state)
3203 int r600_resume(struct radeon_device *rdev)
3212 atom_asic_init(rdev->mode_info.atom_context);
3214 if (rdev->pm.pm_method == PM_METHOD_DPM)
3215 radeon_pm_resume(rdev);
3217 rdev->accel_working = true;
3218 r = r600_startup(rdev);
3221 rdev->accel_working = false;
3228 int r600_suspend(struct radeon_device *rdev)
3230 radeon_pm_suspend(rdev);
3231 radeon_audio_fini(rdev);
3232 r600_cp_stop(rdev);
3233 if (rdev->has_uvd) {
3234 uvd_v1_0_fini(rdev);
3235 radeon_uvd_suspend(rdev);
3237 r600_irq_suspend(rdev);
3238 radeon_wb_disable(rdev);
3239 r600_pcie_gart_disable(rdev);
3250 int r600_init(struct radeon_device *rdev)
3254 if (r600_debugfs_mc_info_init(rdev)) {
3258 if (!radeon_get_bios(rdev)) {
3259 if (ASIC_IS_AVIVO(rdev))
3263 if (!rdev->is_atom_bios) {
3264 dev_err(rdev->dev, "Expecting atombios for R600 GPU\n");
3267 r = radeon_atombios_init(rdev);
3271 if (!radeon_card_posted(rdev)) {
3272 if (!rdev->bios) {
3273 dev_err(rdev->dev, "Card not posted and no BIOS - ignoring\n");
3277 atom_asic_init(rdev->mode_info.atom_context);
3280 r600_scratch_init(rdev);
3282 radeon_surface_init(rdev);
3284 radeon_get_clock_info(rdev->ddev);
3286 r = radeon_fence_driver_init(rdev);
3289 if (rdev->flags & RADEON_IS_AGP) {
3290 r = radeon_agp_init(rdev);
3292 radeon_agp_disable(rdev);
3294 r = r600_mc_init(rdev);
3298 r = radeon_bo_init(rdev);
3302 if (!rdev->me_fw || !rdev->pfp_fw || !rdev->rlc_fw) {
3303 r = r600_init_microcode(rdev);
3311 radeon_pm_init(rdev);
3313 rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ring_obj = NULL;
3314 r600_ring_init(rdev, &rdev->ring[RADEON_RING_TYPE_GFX_INDEX], 1024 * 1024);
3316 r600_uvd_init(rdev);
3318 rdev->ih.ring_obj = NULL;
3319 r600_ih_ring_init(rdev, 64 * 1024);
3321 r = r600_pcie_gart_init(rdev);
3325 rdev->accel_working = true;
3326 r = r600_startup(rdev);
3328 dev_err(rdev->dev, "disabling GPU acceleration\n");
3329 r600_cp_fini(rdev);
3330 r600_irq_fini(rdev);
3331 radeon_wb_fini(rdev);
3332 radeon_ib_pool_fini(rdev);
3333 radeon_irq_kms_fini(rdev);
3334 r600_pcie_gart_fini(rdev);
3335 rdev->accel_working = false;
3341 void r600_fini(struct radeon_device *rdev)
3343 radeon_pm_fini(rdev);
3344 radeon_audio_fini(rdev);
3345 r600_cp_fini(rdev);
3346 r600_irq_fini(rdev);
3347 if (rdev->has_uvd) {
3348 uvd_v1_0_fini(rdev);
3349 radeon_uvd_fini(rdev);
3351 radeon_wb_fini(rdev);
3352 radeon_ib_pool_fini(rdev);
3353 radeon_irq_kms_fini(rdev);
3354 r600_pcie_gart_fini(rdev);
3355 r600_vram_scratch_fini(rdev);
3356 radeon_agp_fini(rdev);
3357 radeon_gem_fini(rdev);
3358 radeon_fence_driver_fini(rdev);
3359 radeon_bo_fini(rdev);
3360 radeon_atombios_fini(rdev);
3361 kfree(rdev->bios);
3362 rdev->bios = NULL;
3369 void r600_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib)
3371 struct radeon_ring *ring = &rdev->ring[ib->ring];
3380 } else if (rdev->wb.enabled) {
3399 int r600_ib_test(struct radeon_device *rdev, struct radeon_ring *ring)
3407 r = radeon_scratch_get(rdev, &scratch);
3413 r = radeon_ib_get(rdev, ring->idx, &ib, NULL, 256);
3422 r = radeon_ib_schedule(rdev, &ib, NULL, false);
3438 for (i = 0; i < rdev->usec_timeout; i++) {
3444 if (i < rdev->usec_timeout) {
3452 radeon_ib_free(rdev, &ib);
3454 radeon_scratch_free(rdev, scratch);
3469 void r600_ih_ring_init(struct radeon_device *rdev, unsigned ring_size)
3476 rdev->ih.ring_size = ring_size;
3477 rdev->ih.ptr_mask = rdev->ih.ring_size - 1;
3478 rdev->ih.rptr = 0;
3481 int r600_ih_ring_alloc(struct radeon_device *rdev)
3486 if (rdev->ih.ring_obj == NULL) {
3487 r = radeon_bo_create(rdev, rdev->ih.ring_size,
3490 NULL, NULL, &rdev->ih.ring_obj);
3495 r = radeon_bo_reserve(rdev->ih.ring_obj, false);
3498 r = radeon_bo_pin(rdev->ih.ring_obj,
3500 &rdev->ih.gpu_addr);
3502 radeon_bo_unreserve(rdev->ih.ring_obj);
3506 r = radeon_bo_kmap(rdev->ih.ring_obj,
3507 (void **)&rdev->ih.ring);
3508 radeon_bo_unreserve(rdev->ih.ring_obj);
3517 void r600_ih_ring_fini(struct radeon_device *rdev)
3520 if (rdev->ih.ring_obj) {
3521 r = radeon_bo_reserve(rdev->ih.ring_obj, false);
3523 radeon_bo_kunmap(rdev->ih.ring_obj);
3524 radeon_bo_unpin(rdev->ih.ring_obj);
3525 radeon_bo_unreserve(rdev->ih.ring_obj);
3527 radeon_bo_unref(&rdev->ih.ring_obj);
3528 rdev->ih.ring = NULL;
3529 rdev->ih.ring_obj = NULL;
3533 void r600_rlc_stop(struct radeon_device *rdev)
3536 if ((rdev->family >= CHIP_RV770) &&
3537 (rdev->family <= CHIP_RV740)) {
3549 static void r600_rlc_start(struct radeon_device *rdev)
3554 static int r600_rlc_resume(struct radeon_device *rdev)
3559 if (!rdev->rlc_fw)
3562 r600_rlc_stop(rdev);
3574 fw_data = (const __be32 *)rdev->rlc_fw->data;
3575 if (rdev->family >= CHIP_RV770) {
3588 r600_rlc_start(rdev);
3593 static void r600_enable_interrupts(struct radeon_device *rdev)
3602 rdev->ih.enabled = true;
3605 void r600_disable_interrupts(struct radeon_device *rdev)
3617 rdev->ih.enabled = false;
3618 rdev->ih.rptr = 0;
3621 static void r600_disable_interrupt_state(struct radeon_device *rdev)
3632 if (ASIC_IS_DCE3(rdev)) {
3643 if (ASIC_IS_DCE32(rdev)) {
3674 int r600_irq_init(struct radeon_device *rdev)
3681 ret = r600_ih_ring_alloc(rdev);
3686 r600_disable_interrupts(rdev);
3689 if (rdev->family >= CHIP_CEDAR)
3690 ret = evergreen_rlc_resume(rdev);
3692 ret = r600_rlc_resume(rdev);
3694 r600_ih_ring_fini(rdev);
3700 WREG32(INTERRUPT_CNTL2, rdev->dummy_page.addr >> 8);
3710 WREG32(IH_RB_BASE, rdev->ih.gpu_addr >> 8);
3711 rb_bufsz = order_base_2(rdev->ih.ring_size / 4);
3717 if (rdev->wb.enabled)
3721 WREG32(IH_RB_WPTR_ADDR_LO, (rdev->wb.gpu_addr + R600_WB_IH_WPTR_OFFSET) & 0xFFFFFFFC);
3722 WREG32(IH_RB_WPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + R600_WB_IH_WPTR_OFFSET) & 0xFF);
3733 if (rdev->msi_enabled)
3738 if (rdev->family >= CHIP_CEDAR)
3739 evergreen_disable_interrupt_state(rdev);
3741 r600_disable_interrupt_state(rdev);
3744 pci_set_master(rdev->pdev);
3747 r600_enable_interrupts(rdev);
3752 void r600_irq_suspend(struct radeon_device *rdev)
3754 r600_irq_disable(rdev);
3755 r600_rlc_stop(rdev);
3758 void r600_irq_fini(struct radeon_device *rdev)
3760 r600_irq_suspend(rdev);
3761 r600_ih_ring_fini(rdev);
3764 int r600_irq_set(struct radeon_device *rdev)
3774 if (!rdev->irq.installed) {
3779 if (!rdev->ih.enabled) {
3780 r600_disable_interrupts(rdev);
3782 r600_disable_interrupt_state(rdev);
3786 if (ASIC_IS_DCE3(rdev)) {
3791 if (ASIC_IS_DCE32(rdev)) {
3810 if ((rdev->family > CHIP_R600) && (rdev->family < CHIP_RV770)) {
3813 } else if (rdev->family >= CHIP_RV770) {
3817 if (rdev->irq.dpm_thermal) {
3822 if (atomic_read(&rdev->irq.ring_int[RADEON_RING_TYPE_GFX_INDEX])) {
3828 if (atomic_read(&rdev->irq.ring_int[R600_RING_TYPE_DMA_INDEX])) {
3833 if (rdev->irq.crtc_vblank_int[0] ||
3834 atomic_read(&rdev->irq.pflip[0])) {
3838 if (rdev->irq.crtc_vblank_int[1] ||
3839 atomic_read(&rdev->irq.pflip[1])) {
3843 if (rdev->irq.hpd[0]) {
3847 if (rdev->irq.hpd[1]) {
3851 if (rdev->irq.hpd[2]) {
3855 if (rdev->irq.hpd[3]) {
3859 if (rdev->irq.hpd[4]) {
3863 if (rdev->irq.hpd[5]) {
3867 if (rdev->irq.afmt[0]) {
3871 if (rdev->irq.afmt[1]) {
3882 if (ASIC_IS_DCE3(rdev)) {
3887 if (ASIC_IS_DCE32(rdev)) {
3903 if ((rdev->family > CHIP_R600) && (rdev->family < CHIP_RV770)) {
3905 } else if (rdev->family >= CHIP_RV770) {
3915 static void r600_irq_ack(struct radeon_device *rdev)
3919 if (ASIC_IS_DCE3(rdev)) {
3920 rdev->irq.stat_regs.r600.disp_int = RREG32(DCE3_DISP_INTERRUPT_STATUS);
3921 rdev->irq.stat_regs.r600.disp_int_cont = RREG32(DCE3_DISP_INTERRUPT_STATUS_CONTINUE);
3922 rdev->irq.stat_regs.r600.disp_int_cont2 = RREG32(DCE3_DISP_INTERRUPT_STATUS_CONTINUE2);
3923 if (ASIC_IS_DCE32(rdev)) {
3924 rdev->irq.stat_regs.r600.hdmi0_status = RREG32(AFMT_STATUS + DCE3_HDMI_OFFSET0);
3925 rdev->irq.stat_regs.r600.hdmi1_status = RREG32(AFMT_STATUS + DCE3_HDMI_OFFSET1);
3927 rdev->irq.stat_regs.r600.hdmi0_status = RREG32(HDMI0_STATUS);
3928 rdev->irq.stat_regs.r600.hdmi1_status = RREG32(DCE3_HDMI1_STATUS);
3931 rdev->irq.stat_regs.r600.disp_int = RREG32(DISP_INTERRUPT_STATUS);
3932 rdev->irq.stat_regs.r600.disp_int_cont = RREG32(DISP_INTERRUPT_STATUS_CONTINUE);
3933 rdev->irq.stat_regs.r600.disp_int_cont2 = 0;
3934 rdev->irq.stat_regs.r600.hdmi0_status = RREG32(HDMI0_STATUS);
3935 rdev->irq.stat_regs.r600.hdmi1_status = RREG32(HDMI1_STATUS);
3937 rdev->irq.stat_regs.r600.d1grph_int = RREG32(D1GRPH_INTERRUPT_STATUS);
3938 rdev->irq.stat_regs.r600.d2grph_int = RREG32(D2GRPH_INTERRUPT_STATUS);
3940 if (rdev->irq.stat_regs.r600.d1grph_int & DxGRPH_PFLIP_INT_OCCURRED)
3942 if (rdev->irq.stat_regs.r600.d2grph_int & DxGRPH_PFLIP_INT_OCCURRED)
3944 if (rdev->irq.stat_regs.r600.disp_int & LB_D1_VBLANK_INTERRUPT)
3946 if (rdev->irq.stat_regs.r600.disp_int & LB_D1_VLINE_INTERRUPT)
3948 if (rdev->irq.stat_regs.r600.disp_int & LB_D2_VBLANK_INTERRUPT)
3950 if (rdev->irq.stat_regs.r600.disp_int & LB_D2_VLINE_INTERRUPT)
3952 if (rdev->irq.stat_regs.r600.disp_int & DC_HPD1_INTERRUPT) {
3953 if (ASIC_IS_DCE3(rdev)) {
3963 if (rdev->irq.stat_regs.r600.disp_int & DC_HPD2_INTERRUPT) {
3964 if (ASIC_IS_DCE3(rdev)) {
3974 if (rdev->irq.stat_regs.r600.disp_int_cont & DC_HPD3_INTERRUPT) {
3975 if (ASIC_IS_DCE3(rdev)) {
3985 if (rdev->irq.stat_regs.r600.disp_int_cont & DC_HPD4_INTERRUPT) {
3990 if (ASIC_IS_DCE32(rdev)) {
3991 if (rdev->irq.stat_regs.r600.disp_int_cont2 & DC_HPD5_INTERRUPT) {
3996 if (rdev->irq.stat_regs.r600.disp_int_cont2 & DC_HPD6_INTERRUPT) {
4001 if (rdev->irq.stat_regs.r600.hdmi0_status & AFMT_AZ_FORMAT_WTRIG) {
4006 if (rdev->irq.stat_regs.r600.hdmi1_status & AFMT_AZ_FORMAT_WTRIG) {
4012 if (rdev->irq.stat_regs.r600.hdmi0_status & HDMI0_AZ_FORMAT_WTRIG) {
4017 if (rdev->irq.stat_regs.r600.hdmi1_status & HDMI0_AZ_FORMAT_WTRIG) {
4018 if (ASIC_IS_DCE3(rdev)) {
4031 void r600_irq_disable(struct radeon_device *rdev)
4033 r600_disable_interrupts(rdev);
4036 r600_irq_ack(rdev);
4037 r600_disable_interrupt_state(rdev);
4040 static u32 r600_get_ih_wptr(struct radeon_device *rdev)
4044 if (rdev->wb.enabled)
4045 wptr = le32_to_cpu(rdev->wb.wb[R600_WB_IH_WPTR_OFFSET/4]);
4055 dev_warn(rdev->dev, "IH ring buffer overflow (0x%08X, 0x%08X, 0x%08X)\n",
4056 wptr, rdev->ih.rptr, (wptr + 16) & rdev->ih.ptr_mask);
4057 rdev->ih.rptr = (wptr + 16) & rdev->ih.ptr_mask;
4062 return (wptr & rdev->ih.ptr_mask);
4095 int r600_irq_process(struct radeon_device *rdev)
4105 if (!rdev->ih.enabled || rdev->shutdown)
4109 if (!rdev->msi_enabled)
4112 wptr = r600_get_ih_wptr(rdev);
4116 if (atomic_xchg(&rdev->ih.lock, 1))
4119 rptr = rdev->ih.rptr;
4126 r600_irq_ack(rdev);
4131 src_id = le32_to_cpu(rdev->ih.ring[ring_index]) & 0xff;
4132 src_data = le32_to_cpu(rdev->ih.ring[ring_index + 1]) & 0xfffffff;
4138 if (!(rdev->irq.stat_regs.r600.disp_int & LB_D1_VBLANK_INTERRUPT))
4141 if (rdev->irq.crtc_vblank_int[0]) {
4142 drm_handle_vblank(rdev->ddev, 0);
4143 rdev->pm.vblank_sync = true;
4144 wake_up(&rdev->irq.vblank_queue);
4146 if (atomic_read(&rdev->irq.pflip[0]))
4147 radeon_crtc_handle_vblank(rdev, 0);
4148 rdev->irq.stat_regs.r600.disp_int &= ~LB_D1_VBLANK_INTERRUPT;
4153 if (!(rdev->irq.stat_regs.r600.disp_int & LB_D1_VLINE_INTERRUPT))
4156 rdev->irq.stat_regs.r600.disp_int &= ~LB_D1_VLINE_INTERRUPT;
4168 if (!(rdev->irq.stat_regs.r600.disp_int & LB_D2_VBLANK_INTERRUPT))
4171 if (rdev->irq.crtc_vblank_int[1]) {
4172 drm_handle_vblank(rdev->ddev, 1);
4173 rdev->pm.vblank_sync = true;
4174 wake_up(&rdev->irq.vblank_queue);
4176 if (atomic_read(&rdev->irq.pflip[1]))
4177 radeon_crtc_handle_vblank(rdev, 1);
4178 rdev->irq.stat_regs.r600.disp_int &= ~LB_D2_VBLANK_INTERRUPT;
4183 if (!(rdev->irq.stat_regs.r600.disp_int & LB_D2_VLINE_INTERRUPT))
4186 rdev->irq.stat_regs.r600.disp_int &= ~LB_D2_VLINE_INTERRUPT;
4198 radeon_crtc_handle_flip(rdev, 0);
4203 radeon_crtc_handle_flip(rdev, 1);
4208 if (!(rdev->irq.stat_regs.r600.disp_int & DC_HPD1_INTERRUPT))
4211 rdev->irq.stat_regs.r600.disp_int &= ~DC_HPD1_INTERRUPT;
4216 if (!(rdev->irq.stat_regs.r600.disp_int & DC_HPD2_INTERRUPT))
4219 rdev->irq.stat_regs.r600.disp_int &= ~DC_HPD2_INTERRUPT;
4224 if (!(rdev->irq.stat_regs.r600.disp_int_cont & DC_HPD3_INTERRUPT))
4227 rdev->irq.stat_regs.r600.disp_int_cont &= ~DC_HPD3_INTERRUPT;
4232 if (!(rdev->irq.stat_regs.r600.disp_int_cont & DC_HPD4_INTERRUPT))
4235 rdev->irq.stat_regs.r600.disp_int_cont &= ~DC_HPD4_INTERRUPT;
4240 if (!(rdev->irq.stat_regs.r600.disp_int_cont2 & DC_HPD5_INTERRUPT))
4243 rdev->irq.stat_regs.r600.disp_int_cont2 &= ~DC_HPD5_INTERRUPT;
4248 if (!(rdev->irq.stat_regs.r600.disp_int_cont2 & DC_HPD6_INTERRUPT))
4251 rdev->irq.stat_regs.r600.disp_int_cont2 &= ~DC_HPD6_INTERRUPT;
4264 if (!(rdev->irq.stat_regs.r600.hdmi0_status & HDMI0_AZ_FORMAT_WTRIG))
4267 rdev->irq.stat_regs.r600.hdmi0_status &= ~HDMI0_AZ_FORMAT_WTRIG;
4273 if (!(rdev->irq.stat_regs.r600.hdmi1_status & HDMI0_AZ_FORMAT_WTRIG))
4276 rdev->irq.stat_regs.r600.hdmi1_status &= ~HDMI0_AZ_FORMAT_WTRIG;
4288 radeon_fence_process(rdev, R600_RING_TYPE_UVD_INDEX);
4294 radeon_fence_process(rdev, RADEON_RING_TYPE_GFX_INDEX);
4298 radeon_fence_process(rdev, RADEON_RING_TYPE_GFX_INDEX);
4302 radeon_fence_process(rdev, R600_RING_TYPE_DMA_INDEX);
4306 rdev->pm.dpm.thermal.high_to_low = false;
4311 rdev->pm.dpm.thermal.high_to_low = true;
4324 rptr &= rdev->ih.ptr_mask;
4328 schedule_delayed_work(&rdev->hotplug_work, 0);
4330 schedule_work(&rdev->audio_work);
4331 if (queue_thermal && rdev->pm.dpm_enabled)
4332 schedule_work(&rdev->pm.dpm.thermal.work);
4333 rdev->ih.rptr = rptr;
4335 atomic_set(&rdev->ih.lock, 0);
4338 wptr = r600_get_ih_wptr(rdev);
4354 struct radeon_device *rdev = dev->dev_private;
4356 DREG32_SYS(m, rdev, R_000E50_SRBM_STATUS);
4357 DREG32_SYS(m, rdev, VM_L2_STATUS);
4366 int r600_debugfs_mc_info_init(struct radeon_device *rdev)
4369 return radeon_debugfs_add_files(rdev, r600_mc_info_list, ARRAY_SIZE(r600_mc_info_list));
4377 * rdev: radeon device structure
4384 void r600_mmio_hdp_flush(struct radeon_device *rdev)
4391 if ((rdev->family >= CHIP_RV770) && (rdev->family <= CHIP_RV740) &&
4392 rdev->vram_scratch.ptr && !(rdev->flags & RADEON_IS_AGP)) {
4393 void __iomem *ptr = (void *)rdev->vram_scratch.ptr;
4402 void r600_set_pcie_lanes(struct radeon_device *rdev, int lanes)
4406 if (rdev->flags & RADEON_IS_IGP)
4409 if (!(rdev->flags & RADEON_IS_PCIE))
4413 if (ASIC_IS_X2(rdev))
4416 radeon_gui_idle(rdev);
4455 int r600_get_pcie_lanes(struct radeon_device *rdev)
4459 if (rdev->flags & RADEON_IS_IGP)
4462 if (!(rdev->flags & RADEON_IS_PCIE))
4466 if (ASIC_IS_X2(rdev))
4469 radeon_gui_idle(rdev);
4492 static void r600_pcie_gen2_enable(struct radeon_device *rdev)
4500 if (rdev->flags & RADEON_IS_IGP)
4503 if (!(rdev->flags & RADEON_IS_PCIE))
4507 if (ASIC_IS_X2(rdev))
4511 if (rdev->family <= CHIP_R600)
4514 if ((rdev->pdev->bus->max_bus_speed != PCIE_SPEED_5_0GT) &&
4515 (rdev->pdev->bus->max_bus_speed != PCIE_SPEED_8_0GT))
4527 if ((rdev->family == CHIP_RV670) ||
4528 (rdev->family == CHIP_RV620) ||
4529 (rdev->family == CHIP_RV635)) {
4552 if ((rdev->family == CHIP_RV670) ||
4553 (rdev->family == CHIP_RV620) ||
4554 (rdev->family == CHIP_RV635)) {
4579 if ((rdev->family == CHIP_RV670) ||
4580 (rdev->family == CHIP_RV620) ||
4581 (rdev->family == CHIP_RV635)) {
4609 * @rdev: radeon_device pointer
4614 uint64_t r600_get_gpu_clock_counter(struct radeon_device *rdev)
4618 mutex_lock(&rdev->gpu_clock_mutex);
4622 mutex_unlock(&rdev->gpu_clock_mutex);