Lines Matching refs:r600
108 /* r600,rv610,rv630,rv620,rv635,rv670 */
1103 pr_warn("[drm] r600 flush TLB failed\n");
2005 rdev->config.r600.tiling_group_size = 256;
2008 rdev->config.r600.max_pipes = 4;
2009 rdev->config.r600.max_tile_pipes = 8;
2010 rdev->config.r600.max_simds = 4;
2011 rdev->config.r600.max_backends = 4;
2012 rdev->config.r600.max_gprs = 256;
2013 rdev->config.r600.max_threads = 192;
2014 rdev->config.r600.max_stack_entries = 256;
2015 rdev->config.r600.max_hw_contexts = 8;
2016 rdev->config.r600.max_gs_threads = 16;
2017 rdev->config.r600.sx_max_export_size = 128;
2018 rdev->config.r600.sx_max_export_pos_size = 16;
2019 rdev->config.r600.sx_max_export_smx_size = 128;
2020 rdev->config.r600.sq_num_cf_insts = 2;
2024 rdev->config.r600.max_pipes = 2;
2025 rdev->config.r600.max_tile_pipes = 2;
2026 rdev->config.r600.max_simds = 3;
2027 rdev->config.r600.max_backends = 1;
2028 rdev->config.r600.max_gprs = 128;
2029 rdev->config.r600.max_threads = 192;
2030 rdev->config.r600.max_stack_entries = 128;
2031 rdev->config.r600.max_hw_contexts = 8;
2032 rdev->config.r600.max_gs_threads = 4;
2033 rdev->config.r600.sx_max_export_size = 128;
2034 rdev->config.r600.sx_max_export_pos_size = 16;
2035 rdev->config.r600.sx_max_export_smx_size = 128;
2036 rdev->config.r600.sq_num_cf_insts = 2;
2042 rdev->config.r600.max_pipes = 1;
2043 rdev->config.r600.max_tile_pipes = 1;
2044 rdev->config.r600.max_simds = 2;
2045 rdev->config.r600.max_backends = 1;
2046 rdev->config.r600.max_gprs = 128;
2047 rdev->config.r600.max_threads = 192;
2048 rdev->config.r600.max_stack_entries = 128;
2049 rdev->config.r600.max_hw_contexts = 4;
2050 rdev->config.r600.max_gs_threads = 4;
2051 rdev->config.r600.sx_max_export_size = 128;
2052 rdev->config.r600.sx_max_export_pos_size = 16;
2053 rdev->config.r600.sx_max_export_smx_size = 128;
2054 rdev->config.r600.sq_num_cf_insts = 1;
2057 rdev->config.r600.max_pipes = 4;
2058 rdev->config.r600.max_tile_pipes = 4;
2059 rdev->config.r600.max_simds = 4;
2060 rdev->config.r600.max_backends = 4;
2061 rdev->config.r600.max_gprs = 192;
2062 rdev->config.r600.max_threads = 192;
2063 rdev->config.r600.max_stack_entries = 256;
2064 rdev->config.r600.max_hw_contexts = 8;
2065 rdev->config.r600.max_gs_threads = 16;
2066 rdev->config.r600.sx_max_export_size = 128;
2067 rdev->config.r600.sx_max_export_pos_size = 16;
2068 rdev->config.r600.sx_max_export_smx_size = 128;
2069 rdev->config.r600.sq_num_cf_insts = 2;
2089 switch (rdev->config.r600.max_tile_pipes) {
2105 rdev->config.r600.tiling_npipes = rdev->config.r600.max_tile_pipes;
2106 rdev->config.r600.tiling_nbanks = 4 << ((ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT);
2121 tmp = rdev->config.r600.max_simds -
2123 rdev->config.r600.active_simds = tmp;
2127 for (i = 0; i < rdev->config.r600.max_backends; i++)
2131 for (i = 0; i < rdev->config.r600.max_backends; i++)
2135 tmp = r6xx_remap_render_backend(rdev, tmp, rdev->config.r600.max_backends,
2138 rdev->config.r600.backend_map = tmp;
2140 rdev->config.r600.tile_config = tiling_config;
2314 tmp = rdev->config.r600.max_pipes * 16;
2703 radeon_ring_write(ring, rdev->config.r600.max_hw_contexts - 1);
3207 /* Do not reset GPU before posting, on r600 hw unlike on r500 hw,
3220 DRM_ERROR("r600 startup failed on resume\n");
3920 rdev->irq.stat_regs.r600.disp_int = RREG32(DCE3_DISP_INTERRUPT_STATUS);
3921 rdev->irq.stat_regs.r600.disp_int_cont = RREG32(DCE3_DISP_INTERRUPT_STATUS_CONTINUE);
3922 rdev->irq.stat_regs.r600.disp_int_cont2 = RREG32(DCE3_DISP_INTERRUPT_STATUS_CONTINUE2);
3924 rdev->irq.stat_regs.r600.hdmi0_status = RREG32(AFMT_STATUS + DCE3_HDMI_OFFSET0);
3925 rdev->irq.stat_regs.r600.hdmi1_status = RREG32(AFMT_STATUS + DCE3_HDMI_OFFSET1);
3927 rdev->irq.stat_regs.r600.hdmi0_status = RREG32(HDMI0_STATUS);
3928 rdev->irq.stat_regs.r600.hdmi1_status = RREG32(DCE3_HDMI1_STATUS);
3931 rdev->irq.stat_regs.r600.disp_int = RREG32(DISP_INTERRUPT_STATUS);
3932 rdev->irq.stat_regs.r600.disp_int_cont = RREG32(DISP_INTERRUPT_STATUS_CONTINUE);
3933 rdev->irq.stat_regs.r600.disp_int_cont2 = 0;
3934 rdev->irq.stat_regs.r600.hdmi0_status = RREG32(HDMI0_STATUS);
3935 rdev->irq.stat_regs.r600.hdmi1_status = RREG32(HDMI1_STATUS);
3937 rdev->irq.stat_regs.r600.d1grph_int = RREG32(D1GRPH_INTERRUPT_STATUS);
3938 rdev->irq.stat_regs.r600.d2grph_int = RREG32(D2GRPH_INTERRUPT_STATUS);
3940 if (rdev->irq.stat_regs.r600.d1grph_int & DxGRPH_PFLIP_INT_OCCURRED)
3942 if (rdev->irq.stat_regs.r600.d2grph_int & DxGRPH_PFLIP_INT_OCCURRED)
3944 if (rdev->irq.stat_regs.r600.disp_int & LB_D1_VBLANK_INTERRUPT)
3946 if (rdev->irq.stat_regs.r600.disp_int & LB_D1_VLINE_INTERRUPT)
3948 if (rdev->irq.stat_regs.r600.disp_int & LB_D2_VBLANK_INTERRUPT)
3950 if (rdev->irq.stat_regs.r600.disp_int & LB_D2_VLINE_INTERRUPT)
3952 if (rdev->irq.stat_regs.r600.disp_int & DC_HPD1_INTERRUPT) {
3963 if (rdev->irq.stat_regs.r600.disp_int & DC_HPD2_INTERRUPT) {
3974 if (rdev->irq.stat_regs.r600.disp_int_cont & DC_HPD3_INTERRUPT) {
3985 if (rdev->irq.stat_regs.r600.disp_int_cont & DC_HPD4_INTERRUPT) {
3991 if (rdev->irq.stat_regs.r600.disp_int_cont2 & DC_HPD5_INTERRUPT) {
3996 if (rdev->irq.stat_regs.r600.disp_int_cont2 & DC_HPD6_INTERRUPT) {
4001 if (rdev->irq.stat_regs.r600.hdmi0_status & AFMT_AZ_FORMAT_WTRIG) {
4006 if (rdev->irq.stat_regs.r600.hdmi1_status & AFMT_AZ_FORMAT_WTRIG) {
4012 if (rdev->irq.stat_regs.r600.hdmi0_status & HDMI0_AZ_FORMAT_WTRIG) {
4017 if (rdev->irq.stat_regs.r600.hdmi1_status & HDMI0_AZ_FORMAT_WTRIG) {
4065 /* r600 IV Ring
4091 * Note, these are based on r600 and may need to be
4138 if (!(rdev->irq.stat_regs.r600.disp_int & LB_D1_VBLANK_INTERRUPT))
4148 rdev->irq.stat_regs.r600.disp_int &= ~LB_D1_VBLANK_INTERRUPT;
4153 if (!(rdev->irq.stat_regs.r600.disp_int & LB_D1_VLINE_INTERRUPT))
4156 rdev->irq.stat_regs.r600.disp_int &= ~LB_D1_VLINE_INTERRUPT;
4168 if (!(rdev->irq.stat_regs.r600.disp_int & LB_D2_VBLANK_INTERRUPT))
4178 rdev->irq.stat_regs.r600.disp_int &= ~LB_D2_VBLANK_INTERRUPT;
4183 if (!(rdev->irq.stat_regs.r600.disp_int & LB_D2_VLINE_INTERRUPT))
4186 rdev->irq.stat_regs.r600.disp_int &= ~LB_D2_VLINE_INTERRUPT;
4208 if (!(rdev->irq.stat_regs.r600.disp_int & DC_HPD1_INTERRUPT))
4211 rdev->irq.stat_regs.r600.disp_int &= ~DC_HPD1_INTERRUPT;
4216 if (!(rdev->irq.stat_regs.r600.disp_int & DC_HPD2_INTERRUPT))
4219 rdev->irq.stat_regs.r600.disp_int &= ~DC_HPD2_INTERRUPT;
4224 if (!(rdev->irq.stat_regs.r600.disp_int_cont & DC_HPD3_INTERRUPT))
4227 rdev->irq.stat_regs.r600.disp_int_cont &= ~DC_HPD3_INTERRUPT;
4232 if (!(rdev->irq.stat_regs.r600.disp_int_cont & DC_HPD4_INTERRUPT))
4235 rdev->irq.stat_regs.r600.disp_int_cont &= ~DC_HPD4_INTERRUPT;
4240 if (!(rdev->irq.stat_regs.r600.disp_int_cont2 & DC_HPD5_INTERRUPT))
4243 rdev->irq.stat_regs.r600.disp_int_cont2 &= ~DC_HPD5_INTERRUPT;
4248 if (!(rdev->irq.stat_regs.r600.disp_int_cont2 & DC_HPD6_INTERRUPT))
4251 rdev->irq.stat_regs.r600.disp_int_cont2 &= ~DC_HPD6_INTERRUPT;
4264 if (!(rdev->irq.stat_regs.r600.hdmi0_status & HDMI0_AZ_FORMAT_WTRIG))
4267 rdev->irq.stat_regs.r600.hdmi0_status &= ~HDMI0_AZ_FORMAT_WTRIG;
4273 if (!(rdev->irq.stat_regs.r600.hdmi1_status & HDMI0_AZ_FORMAT_WTRIG))
4276 rdev->irq.stat_regs.r600.hdmi1_status &= ~HDMI0_AZ_FORMAT_WTRIG;