Lines Matching defs:rdev
45 void r420_pm_init_profile(struct radeon_device *rdev)
48 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
49 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
50 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0;
51 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0;
53 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = 0;
54 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 0;
55 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
56 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
58 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = 0;
59 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = 1;
60 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
61 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0;
63 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 0;
64 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
65 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0;
66 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 0;
68 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = 0;
69 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
70 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
71 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
73 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = 0;
74 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
75 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
76 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0;
78 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 0;
79 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
80 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0;
81 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 0;
84 static void r420_set_reg_safe(struct radeon_device *rdev)
86 rdev->config.r300.reg_safe_bm = r420_reg_safe_bm;
87 rdev->config.r300.reg_safe_bm_size = ARRAY_SIZE(r420_reg_safe_bm);
90 void r420_pipes_init(struct radeon_device *rdev)
100 if (r100_gui_wait_for_idle(rdev)) {
108 if ((rdev->pdev->device == 0x5e4c) ||
109 (rdev->pdev->device == 0x5e4f))
112 rdev->num_gb_pipes = num_pipes;
136 if (r100_gui_wait_for_idle(rdev)) {
148 if (r100_gui_wait_for_idle(rdev)) {
152 if (rdev->family == CHIP_RV530) {
155 rdev->num_z_pipes = 2;
157 rdev->num_z_pipes = 1;
159 rdev->num_z_pipes = 1;
162 rdev->num_gb_pipes, rdev->num_z_pipes);
165 u32 r420_mc_rreg(struct radeon_device *rdev, u32 reg)
170 spin_lock_irqsave(&rdev->mc_idx_lock, flags);
173 spin_unlock_irqrestore(&rdev->mc_idx_lock, flags);
177 void r420_mc_wreg(struct radeon_device *rdev, u32 reg, u32 v)
181 spin_lock_irqsave(&rdev->mc_idx_lock, flags);
185 spin_unlock_irqrestore(&rdev->mc_idx_lock, flags);
188 static void r420_debugfs(struct radeon_device *rdev)
190 if (r100_debugfs_rbbm_init(rdev)) {
193 if (r420_debugfs_pipes_info_init(rdev)) {
198 static void r420_clock_resume(struct radeon_device *rdev)
203 radeon_atom_set_clock_gating(rdev, 1);
206 if (rdev->family == CHIP_R420)
211 static void r420_cp_errata_init(struct radeon_device *rdev)
214 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
222 radeon_scratch_get(rdev, &rdev->config.r300.resync_scratch);
223 r = radeon_ring_lock(rdev, ring, 8);
226 radeon_ring_write(ring, rdev->config.r300.resync_scratch);
228 radeon_ring_unlock_commit(rdev, ring, false);
231 static void r420_cp_errata_fini(struct radeon_device *rdev)
234 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
239 r = radeon_ring_lock(rdev, ring, 8);
243 radeon_ring_unlock_commit(rdev, ring, false);
244 radeon_scratch_free(rdev, rdev->config.r300.resync_scratch);
247 static int r420_startup(struct radeon_device *rdev)
252 r100_set_common_regs(rdev);
254 r300_mc_program(rdev);
256 r420_clock_resume(rdev);
259 if (rdev->flags & RADEON_IS_PCIE) {
260 r = rv370_pcie_gart_enable(rdev);
264 if (rdev->flags & RADEON_IS_PCI) {
265 r = r100_pci_gart_enable(rdev);
269 r420_pipes_init(rdev);
272 r = radeon_wb_init(rdev);
276 r = radeon_fence_driver_start_ring(rdev, RADEON_RING_TYPE_GFX_INDEX);
278 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r);
283 if (!rdev->irq.installed) {
284 r = radeon_irq_kms_init(rdev);
289 r100_irq_set(rdev);
290 rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL);
292 r = r100_cp_init(rdev, 1024 * 1024);
294 dev_err(rdev->dev, "failed initializing CP (%d).\n", r);
297 r420_cp_errata_init(rdev);
299 r = radeon_ib_pool_init(rdev);
301 dev_err(rdev->dev, "IB initialization failed (%d).\n", r);
308 int r420_resume(struct radeon_device *rdev)
313 if (rdev->flags & RADEON_IS_PCIE)
314 rv370_pcie_gart_disable(rdev);
315 if (rdev->flags & RADEON_IS_PCI)
316 r100_pci_gart_disable(rdev);
318 r420_clock_resume(rdev);
320 if (radeon_asic_reset(rdev)) {
321 dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
326 if (rdev->is_atom_bios) {
327 atom_asic_init(rdev->mode_info.atom_context);
329 radeon_combios_asic_init(rdev->ddev);
332 r420_clock_resume(rdev);
334 radeon_surface_init(rdev);
336 rdev->accel_working = true;
337 r = r420_startup(rdev);
339 rdev->accel_working = false;
344 int r420_suspend(struct radeon_device *rdev)
346 radeon_pm_suspend(rdev);
347 r420_cp_errata_fini(rdev);
348 r100_cp_disable(rdev);
349 radeon_wb_disable(rdev);
350 r100_irq_disable(rdev);
351 if (rdev->flags & RADEON_IS_PCIE)
352 rv370_pcie_gart_disable(rdev);
353 if (rdev->flags & RADEON_IS_PCI)
354 r100_pci_gart_disable(rdev);
358 void r420_fini(struct radeon_device *rdev)
360 radeon_pm_fini(rdev);
361 r100_cp_fini(rdev);
362 radeon_wb_fini(rdev);
363 radeon_ib_pool_fini(rdev);
364 radeon_gem_fini(rdev);
365 if (rdev->flags & RADEON_IS_PCIE)
366 rv370_pcie_gart_fini(rdev);
367 if (rdev->flags & RADEON_IS_PCI)
368 r100_pci_gart_fini(rdev);
369 radeon_agp_fini(rdev);
370 radeon_irq_kms_fini(rdev);
371 radeon_fence_driver_fini(rdev);
372 radeon_bo_fini(rdev);
373 if (rdev->is_atom_bios) {
374 radeon_atombios_fini(rdev);
376 radeon_combios_fini(rdev);
378 kfree(rdev->bios);
379 rdev->bios = NULL;
382 int r420_init(struct radeon_device *rdev)
387 radeon_scratch_init(rdev);
389 radeon_surface_init(rdev);
392 r100_restore_sanity(rdev);
394 if (!radeon_get_bios(rdev)) {
395 if (ASIC_IS_AVIVO(rdev))
398 if (rdev->is_atom_bios) {
399 r = radeon_atombios_init(rdev);
404 r = radeon_combios_init(rdev);
410 if (radeon_asic_reset(rdev)) {
411 dev_warn(rdev->dev,
417 if (radeon_boot_test_post_card(rdev) == false)
421 radeon_get_clock_info(rdev->ddev);
423 if (rdev->flags & RADEON_IS_AGP) {
424 r = radeon_agp_init(rdev);
426 radeon_agp_disable(rdev);
430 r300_mc_init(rdev);
431 r420_debugfs(rdev);
433 r = radeon_fence_driver_init(rdev);
438 r = radeon_bo_init(rdev);
442 if (rdev->family == CHIP_R420)
443 r100_enable_bm(rdev);
445 if (rdev->flags & RADEON_IS_PCIE) {
446 r = rv370_pcie_gart_init(rdev);
450 if (rdev->flags & RADEON_IS_PCI) {
451 r = r100_pci_gart_init(rdev);
455 r420_set_reg_safe(rdev);
458 radeon_pm_init(rdev);
460 rdev->accel_working = true;
461 r = r420_startup(rdev);
464 dev_err(rdev->dev, "Disabling GPU acceleration\n");
465 r100_cp_fini(rdev);
466 radeon_wb_fini(rdev);
467 radeon_ib_pool_fini(rdev);
468 radeon_irq_kms_fini(rdev);
469 if (rdev->flags & RADEON_IS_PCIE)
470 rv370_pcie_gart_fini(rdev);
471 if (rdev->flags & RADEON_IS_PCI)
472 r100_pci_gart_fini(rdev);
473 radeon_agp_fini(rdev);
474 rdev->accel_working = false;
487 struct radeon_device *rdev = dev->dev_private;
504 int r420_debugfs_pipes_info_init(struct radeon_device *rdev)
507 return radeon_debugfs_add_files(rdev, r420_pipes_info_list, 1);