Lines Matching defs:idx_value
641 u32 idx_value;
645 idx_value = radeon_get_ib_value(p, idx);
677 track->cb[i].offset = idx_value;
679 ib[idx] = idx_value + ((u32)reloc->gpu_offset);
690 track->zb.offset = idx_value;
692 ib[idx] = idx_value + ((u32)reloc->gpu_offset);
720 ib[idx] = (idx_value & 31) | /* keep the 1st 5 bits */
721 ((idx_value & ~31) + (u32)reloc->gpu_offset);
730 tmp = idx_value + ((u32)reloc->gpu_offset);
740 track->vap_vf_cntl = idx_value;
744 track->vtx_size = idx_value & 0x7F;
748 track->max_indx = idx_value & 0x00FFFFFFUL;
754 track->vap_alt_nverts = idx_value & 0xFFFFFF;
758 track->maxy = ((idx_value >> 13) & 0x1FFF) + 1;
767 if ((idx_value & (1 << 10)) && /* CMASK_ENABLE */
772 track->num_cb = ((idx_value >> 5) & 0x3) + 1;
799 tmp = idx_value & ~(0x7 << 16);
804 track->cb[i].pitch = idx_value & 0x3FFE;
805 switch (((idx_value >> 21) & 0xF)) {
820 ((idx_value >> 21) & 0xF));
835 ((idx_value >> 21) & 0xF));
842 if (idx_value & 2) {
851 switch ((idx_value & 0xF)) {
861 (idx_value & 0xF));
884 tmp = idx_value & ~(0x7 << 16);
888 track->zb.pitch = idx_value & 0x3FFC;
896 enabled = !!(idx_value & (1 << i));
919 tmp = (idx_value >> 25) & 0x3;
921 switch ((idx_value & 0x1F)) {
970 (idx_value & 0x1F));
982 (idx_value & 0x1F));
1005 tmp = idx_value & 0x7;
1009 tmp = (idx_value >> 3) & 0x7;
1033 tmp = idx_value & 0x3FFF;
1036 tmp = ((idx_value >> 15) & 1) << 11;
1038 tmp = ((idx_value >> 16) & 1) << 11;
1042 if (idx_value & (1 << 14)) {
1047 } else if (idx_value & (1 << 14)) {
1071 tmp = idx_value & 0x7FF;
1073 tmp = (idx_value >> 11) & 0x7FF;
1075 tmp = (idx_value >> 26) & 0xF;
1077 tmp = idx_value & (1 << 31);
1079 tmp = (idx_value >> 22) & 0xF;
1091 ib[idx] = idx_value + ((u32)reloc->gpu_offset);
1095 track->color_channel_mask = idx_value;
1103 if (idx_value & 0x1)
1104 ib[idx] = idx_value & ~1;
1109 track->zb_cb_clear = !!(idx_value & (1 << 5));
1113 if (idx_value & (R300_HIZ_ENABLE |
1122 track->blend_read_enable = !!(idx_value & (1 << 2));
1134 track->aa.offset = idx_value;
1136 ib[idx] = idx_value + ((u32)reloc->gpu_offset);
1139 track->aa.pitch = idx_value & 0x3FFE;
1143 track->aaresolve = idx_value & 0x1;
1150 if (idx_value && (p->rdev->hyperz_filp != p->filp))
1154 if (idx_value && (p->rdev->hyperz_filp != p->filp))
1172 reg, idx, idx_value);