Lines Matching refs:temp
1780 uint32_t temp = idx_value >> 4;
1782 track->textures[i].enabled = !!(temp & (1 << i));
2815 uint32_t temp;
2817 temp = RREG32(RADEON_CONFIG_CNTL);
2819 temp &= ~RADEON_CFG_VGA_RAM_EN;
2820 temp |= RADEON_CFG_VGA_IO_DIS;
2822 temp &= ~RADEON_CFG_VGA_IO_DIS;
2824 WREG32(RADEON_CONFIG_CNTL, temp);
3153 uint32_t temp, data, mem_trcd, mem_trp, mem_tras;
3264 temp = (rdev->mc.vram_width / 8) * (rdev->mc.vram_is_ddr ? 2 : 1);
3265 temp_ff.full = dfixed_const(temp);
3293 temp = RREG32(RADEON_MEM_TIMING_CNTL);
3295 mem_trcd = ((temp >> 2) & 0x3) + 1;
3296 mem_trp = ((temp & 0x3)) + 1;
3297 mem_tras = ((temp & 0x70) >> 4) + 1;
3300 mem_trcd = (temp & 0x7) + 1;
3301 mem_trp = ((temp >> 8) & 0x7) + 1;
3302 mem_tras = ((temp >> 11) & 0xf) + 4;
3306 mem_trcd = (temp & 0x7) + 3;
3307 mem_trp = ((temp >> 8) & 0x7) + 3;
3308 mem_tras = ((temp >> 11) & 0xf) + 6;
3313 mem_trcd = (temp & 0xf) + 3;
3316 mem_trp = ((temp >> 8) & 0xf) + 3;
3319 mem_tras = ((temp >> 12) & 0x1f) + 6;
3323 mem_trcd = (temp & 0x7) + 1;
3324 mem_trp = ((temp >> 8) & 0x7) + 1;
3325 mem_tras = ((temp >> 12) & 0xf) + 4;
3333 temp = RREG32(RADEON_MEM_SDRAM_MODE_REG);
3334 data = (temp & (7 << 20)) >> 20;
3346 data = (temp >> 23) & 0x7;
3354 temp = RREG32(RADEON_MEM_CNTL);
3355 data = (R300_MEM_NUM_CHANNELS_MASK & temp);
3357 if (R300_MEM_USE_CD_CH_ONLY & temp) {
3358 temp = RREG32(R300_MC_IND_INDEX);
3359 temp &= ~R300_MC_IND_ADDR_MASK;
3360 temp |= R300_MC_READ_CNTL_CD_mcind;
3361 WREG32(R300_MC_IND_INDEX, temp);
3362 temp = RREG32(R300_MC_IND_DATA);
3363 data = (R300_MEM_RBS_POSITION_C_MASK & temp);
3365 temp = RREG32(R300_MC_READ_CNTL_AB);
3366 data = (R300_MEM_RBS_POSITION_A_MASK & temp);
3369 temp = RREG32(R300_MC_READ_CNTL_AB);
3370 data = (R300_MEM_RBS_POSITION_A_MASK & temp);
3505 temp = RREG32(RADEON_GRPH_BUFFER_CNTL);
3506 temp &= ~(RADEON_GRPH_STOP_REQ_MASK);
3507 temp |= (stop_req << RADEON_GRPH_STOP_REQ_SHIFT);
3508 temp &= ~(RADEON_GRPH_START_REQ_MASK);
3513 temp |= (stop_req << RADEON_GRPH_START_REQ_SHIFT);
3514 temp |= RADEON_GRPH_BUFFER_SIZE;
3515 temp &= ~(RADEON_GRPH_CRITICAL_CNTL |
3521 WREG32(RADEON_GRPH_BUFFER_CNTL, ((temp & ~RADEON_GRPH_CRITICAL_POINT_MASK) |
3528 temp = RREG32(RS400_DISP1_REG_CNTL);
3529 temp &= ~(RS400_DISP1_START_REQ_LEVEL_MASK |
3531 WREG32(RS400_DISP1_REQ_CNTL1, (temp |
3534 temp = RREG32(RS400_DMIF_MEM_CNTL1);
3535 temp &= ~(RS400_DISP1_CRITICAL_POINT_START_MASK |
3537 WREG32(RS400_DMIF_MEM_CNTL1, (temp |
3579 temp = (rdev->mc.vram_width * rdev->mc.vram_is_ddr + 1)/128;
3580 temp_ff.full = dfixed_const(temp);
3620 temp = RREG32(RS400_DISP2_REQ_CNTL1);
3621 temp &= ~(RS400_DISP2_START_REQ_LEVEL_MASK |
3623 WREG32(RS400_DISP2_REQ_CNTL1, (temp |
3626 temp = RREG32(RS400_DISP2_REQ_CNTL2);
3627 temp &= ~(RS400_DISP2_CRITICAL_POINT_START_MASK |
3629 WREG32(RS400_DISP2_REQ_CNTL2, (temp |