Lines Matching defs:save
1224 DRM_ERROR("failed to get scratch reg for rptr save (%d).\n", r);
2558 struct r100_mc_save save;
2566 r100_mc_stop(rdev, &save);
2576 /* save PCI state */
2608 r100_mc_resume(rdev, &save);
2870 uint32_t save, tmp;
2872 save = RREG32(RADEON_CLOCK_CNTL_INDEX);
2873 tmp = save & ~(0x3f | RADEON_PLL_WR_EN);
2876 WREG32(RADEON_CLOCK_CNTL_INDEX, save);
3771 void r100_mc_stop(struct radeon_device *rdev, struct r100_mc_save *save)
3780 save->GENMO_WT = RREG8(R_0003C2_GENMO_WT);
3781 save->CRTC_EXT_CNTL = RREG32(R_000054_CRTC_EXT_CNTL);
3782 save->CRTC_GEN_CNTL = RREG32(R_000050_CRTC_GEN_CNTL);
3783 save->CUR_OFFSET = RREG32(R_000260_CUR_OFFSET);
3785 save->CRTC2_GEN_CNTL = RREG32(R_0003F8_CRTC2_GEN_CNTL);
3786 save->CUR2_OFFSET = RREG32(R_000360_CUR2_OFFSET);
3790 WREG8(R_0003C2_GENMO_WT, C_0003C2_VGA_RAM_EN & save->GENMO_WT);
3792 WREG32(R_000260_CUR_OFFSET, save->CUR_OFFSET | S_000260_CUR_LOCK(1));
3793 WREG32(R_000054_CRTC_EXT_CNTL, save->CRTC_EXT_CNTL |
3796 (C_000050_CRTC_CUR_EN & save->CRTC_GEN_CNTL) |
3800 WREG32(R_000260_CUR_OFFSET, C_000260_CUR_LOCK & save->CUR_OFFSET);
3802 WREG32(R_000360_CUR2_OFFSET, save->CUR2_OFFSET |
3805 (C_0003F8_CRTC2_CUR_EN & save->CRTC2_GEN_CNTL) |
3809 C_000360_CUR2_LOCK & save->CUR2_OFFSET);
3813 void r100_mc_resume(struct radeon_device *rdev, struct r100_mc_save *save)
3821 WREG8(R_0003C2_GENMO_WT, save->GENMO_WT);
3822 WREG32(R_000054_CRTC_EXT_CNTL, save->CRTC_EXT_CNTL);
3823 WREG32(R_000050_CRTC_GEN_CNTL, save->CRTC_GEN_CNTL);
3825 WREG32(R_0003F8_CRTC2_GEN_CNTL, save->CRTC2_GEN_CNTL);
3848 struct r100_mc_save save;
3851 r100_mc_stop(rdev, &save);
3873 r100_mc_resume(rdev, &save);