Lines Matching defs:rdev
77 static bool r100_is_in_vblank(struct radeon_device *rdev, int crtc)
92 static bool r100_is_counter_moving(struct radeon_device *rdev, int crtc)
112 * @rdev: radeon_device pointer
117 void r100_wait_for_vblank(struct radeon_device *rdev, int crtc)
121 if (crtc >= rdev->num_crtc)
135 while (r100_is_in_vblank(rdev, crtc)) {
137 if (!r100_is_counter_moving(rdev, crtc))
142 while (!r100_is_in_vblank(rdev, crtc)) {
144 if (!r100_is_counter_moving(rdev, crtc))
153 * @rdev: radeon_device pointer
162 void r100_page_flip(struct radeon_device *rdev, int crtc_id, u64 crtc_base, bool async)
164 struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id];
173 for (i = 0; i < rdev->usec_timeout; i++) {
189 * @rdev: radeon_device pointer
195 bool r100_page_flip_pending(struct radeon_device *rdev, int crtc_id)
197 struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id];
207 * @rdev: radeon_device pointer
213 void r100_pm_get_dynpm_state(struct radeon_device *rdev)
216 rdev->pm.dynpm_can_upclock = true;
217 rdev->pm.dynpm_can_downclock = true;
219 switch (rdev->pm.dynpm_planned_action) {
221 rdev->pm.requested_power_state_index = 0;
222 rdev->pm.dynpm_can_downclock = false;
225 if (rdev->pm.current_power_state_index == 0) {
226 rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index;
227 rdev->pm.dynpm_can_downclock = false;
229 if (rdev->pm.active_crtc_count > 1) {
230 for (i = 0; i < rdev->pm.num_power_states; i++) {
231 if (rdev->pm.power_state[i].flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY)
233 else if (i >= rdev->pm.current_power_state_index) {
234 rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index;
237 rdev->pm.requested_power_state_index = i;
242 rdev->pm.requested_power_state_index =
243 rdev->pm.current_power_state_index - 1;
246 if ((rdev->pm.active_crtc_count > 0) &&
247 (rdev->pm.power_state[rdev->pm.requested_power_state_index].clock_info[0].flags &
249 rdev->pm.requested_power_state_index++;
253 if (rdev->pm.current_power_state_index == (rdev->pm.num_power_states - 1)) {
254 rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index;
255 rdev->pm.dynpm_can_upclock = false;
257 if (rdev->pm.active_crtc_count > 1) {
258 for (i = (rdev->pm.num_power_states - 1); i >= 0; i--) {
259 if (rdev->pm.power_state[i].flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY)
261 else if (i <= rdev->pm.current_power_state_index) {
262 rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index;
265 rdev->pm.requested_power_state_index = i;
270 rdev->pm.requested_power_state_index =
271 rdev->pm.current_power_state_index + 1;
275 rdev->pm.requested_power_state_index = rdev->pm.default_power_state_index;
276 rdev->pm.dynpm_can_upclock = false;
284 rdev->pm.requested_clock_mode_index = 0;
287 rdev->pm.power_state[rdev->pm.requested_power_state_index].
288 clock_info[rdev->pm.requested_clock_mode_index].sclk,
289 rdev->pm.power_state[rdev->pm.requested_power_state_index].
290 clock_info[rdev->pm.requested_clock_mode_index].mclk,
291 rdev->pm.power_state[rdev->pm.requested_power_state_index].
298 * @rdev: radeon_device pointer
304 void r100_pm_init_profile(struct radeon_device *rdev)
307 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
308 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
309 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0;
310 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0;
312 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = 0;
313 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 0;
314 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
315 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
317 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = 0;
318 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = 0;
319 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
320 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0;
322 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 0;
323 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
324 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0;
325 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 0;
327 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = 0;
328 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
329 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
330 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
332 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = 0;
333 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
334 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
335 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0;
337 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 0;
338 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
339 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0;
340 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 0;
346 * @rdev: radeon_device pointer
351 void r100_pm_misc(struct radeon_device *rdev)
353 int requested_index = rdev->pm.requested_power_state_index;
354 struct radeon_power_state *ps = &rdev->pm.power_state[requested_index];
431 if ((rdev->flags & RADEON_IS_PCIE) &&
432 !(rdev->flags & RADEON_IS_IGP) &&
433 rdev->asic->pm.set_pcie_lanes &&
435 rdev->pm.power_state[rdev->pm.current_power_state_index].pcie_lanes)) {
436 radeon_set_pcie_lanes(rdev,
445 * @rdev: radeon_device pointer
449 void r100_pm_prepare(struct radeon_device *rdev)
451 struct drm_device *ddev = rdev->ddev;
476 * @rdev: radeon_device pointer
480 void r100_pm_finish(struct radeon_device *rdev)
482 struct drm_device *ddev = rdev->ddev;
507 * @rdev: radeon_device pointer
512 bool r100_gui_idle(struct radeon_device *rdev)
524 * @rdev: radeon_device pointer
530 bool r100_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd)
552 * @rdev: radeon_device pointer
557 void r100_hpd_set_polarity(struct radeon_device *rdev,
561 bool connected = r100_hpd_sense(rdev, hpd);
588 * @rdev: radeon_device pointer
593 void r100_hpd_init(struct radeon_device *rdev)
595 struct drm_device *dev = rdev->ddev;
603 radeon_hpd_set_polarity(rdev, radeon_connector->hpd.hpd);
605 radeon_irq_kms_enable_hpd(rdev, enable);
611 * @rdev: radeon_device pointer
616 void r100_hpd_fini(struct radeon_device *rdev)
618 struct drm_device *dev = rdev->ddev;
627 radeon_irq_kms_disable_hpd(rdev, disable);
633 void r100_pci_gart_tlb_flush(struct radeon_device *rdev)
641 int r100_pci_gart_init(struct radeon_device *rdev)
645 if (rdev->gart.ptr) {
650 r = radeon_gart_init(rdev);
653 rdev->gart.table_size = rdev->gart.num_gpu_pages * 4;
654 rdev->asic->gart.tlb_flush = &r100_pci_gart_tlb_flush;
655 rdev->asic->gart.get_page_entry = &r100_pci_gart_get_page_entry;
656 rdev->asic->gart.set_page = &r100_pci_gart_set_page;
657 return radeon_gart_table_ram_alloc(rdev);
660 int r100_pci_gart_enable(struct radeon_device *rdev)
668 WREG32(RADEON_AIC_LO_ADDR, rdev->mc.gtt_start);
669 WREG32(RADEON_AIC_HI_ADDR, rdev->mc.gtt_end);
671 WREG32(RADEON_AIC_PT_BASE, rdev->gart.table_addr);
674 r100_pci_gart_tlb_flush(rdev);
676 (unsigned)(rdev->mc.gtt_size >> 20),
677 (unsigned long long)rdev->gart.table_addr);
678 rdev->gart.ready = true;
682 void r100_pci_gart_disable(struct radeon_device *rdev)
698 void r100_pci_gart_set_page(struct radeon_device *rdev, unsigned i,
701 u32 *gtt = rdev->gart.ptr;
705 void r100_pci_gart_fini(struct radeon_device *rdev)
707 radeon_gart_fini(rdev);
708 r100_pci_gart_disable(rdev);
709 radeon_gart_table_ram_free(rdev);
712 int r100_irq_set(struct radeon_device *rdev)
716 if (!rdev->irq.installed) {
721 if (atomic_read(&rdev->irq.ring_int[RADEON_RING_TYPE_GFX_INDEX])) {
724 if (rdev->irq.crtc_vblank_int[0] ||
725 atomic_read(&rdev->irq.pflip[0])) {
728 if (rdev->irq.crtc_vblank_int[1] ||
729 atomic_read(&rdev->irq.pflip[1])) {
732 if (rdev->irq.hpd[0]) {
735 if (rdev->irq.hpd[1]) {
746 void r100_irq_disable(struct radeon_device *rdev)
757 static uint32_t r100_irq_ack(struct radeon_device *rdev)
770 int r100_irq_process(struct radeon_device *rdev)
775 status = r100_irq_ack(rdev);
779 if (rdev->shutdown) {
785 radeon_fence_process(rdev, RADEON_RING_TYPE_GFX_INDEX);
789 if (rdev->irq.crtc_vblank_int[0]) {
790 drm_handle_vblank(rdev->ddev, 0);
791 rdev->pm.vblank_sync = true;
792 wake_up(&rdev->irq.vblank_queue);
794 if (atomic_read(&rdev->irq.pflip[0]))
795 radeon_crtc_handle_vblank(rdev, 0);
798 if (rdev->irq.crtc_vblank_int[1]) {
799 drm_handle_vblank(rdev->ddev, 1);
800 rdev->pm.vblank_sync = true;
801 wake_up(&rdev->irq.vblank_queue);
803 if (atomic_read(&rdev->irq.pflip[1]))
804 radeon_crtc_handle_vblank(rdev, 1);
814 status = r100_irq_ack(rdev);
817 schedule_delayed_work(&rdev->hotplug_work, 0);
818 if (rdev->msi_enabled) {
819 switch (rdev->family) {
834 u32 r100_get_vblank_counter(struct radeon_device *rdev, int crtc)
844 * rdev: radeon device structure
847 static void r100_ring_hdp_flush(struct radeon_device *rdev, struct radeon_ring *ring)
850 radeon_ring_write(ring, rdev->config.r100.hdp_cntl |
853 radeon_ring_write(ring, rdev->config.r100.hdp_cntl);
858 void r100_fence_ring_emit(struct radeon_device *rdev,
861 struct radeon_ring *ring = &rdev->ring[fence->ring];
872 r100_ring_hdp_flush(rdev, ring);
874 radeon_ring_write(ring, PACKET0(rdev->fence_drv[fence->ring].scratch_reg, 0));
880 bool r100_semaphore_ring_emit(struct radeon_device *rdev,
890 struct radeon_fence *r100_copy_blit(struct radeon_device *rdev,
896 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
915 r = radeon_ring_lock(rdev, ring, ndw);
958 r = radeon_fence_emit(rdev, &fence, RADEON_RING_TYPE_GFX_INDEX);
960 radeon_ring_unlock_undo(rdev, ring);
963 radeon_ring_unlock_commit(rdev, ring, false);
967 static int r100_cp_wait_for_idle(struct radeon_device *rdev)
972 for (i = 0; i < rdev->usec_timeout; i++) {
982 void r100_ring_start(struct radeon_device *rdev, struct radeon_ring *ring)
986 r = radeon_ring_lock(rdev, ring, 2);
996 radeon_ring_unlock_commit(rdev, ring, false);
1001 static int r100_cp_init_microcode(struct radeon_device *rdev)
1008 if ((rdev->family == CHIP_R100) || (rdev->family == CHIP_RV100) ||
1009 (rdev->family == CHIP_RV200) || (rdev->family == CHIP_RS100) ||
1010 (rdev->family == CHIP_RS200)) {
1013 } else if ((rdev->family == CHIP_R200) ||
1014 (rdev->family == CHIP_RV250) ||
1015 (rdev->family == CHIP_RV280) ||
1016 (rdev->family == CHIP_RS300)) {
1019 } else if ((rdev->family == CHIP_R300) ||
1020 (rdev->family == CHIP_R350) ||
1021 (rdev->family == CHIP_RV350) ||
1022 (rdev->family == CHIP_RV380) ||
1023 (rdev->family == CHIP_RS400) ||
1024 (rdev->family == CHIP_RS480)) {
1027 } else if ((rdev->family == CHIP_R420) ||
1028 (rdev->family == CHIP_R423) ||
1029 (rdev->family == CHIP_RV410)) {
1032 } else if ((rdev->family == CHIP_RS690) ||
1033 (rdev->family == CHIP_RS740)) {
1036 } else if (rdev->family == CHIP_RS600) {
1039 } else if ((rdev->family == CHIP_RV515) ||
1040 (rdev->family == CHIP_R520) ||
1041 (rdev->family == CHIP_RV530) ||
1042 (rdev->family == CHIP_R580) ||
1043 (rdev->family == CHIP_RV560) ||
1044 (rdev->family == CHIP_RV570)) {
1049 err = request_firmware(&rdev->me_fw, fw_name, rdev->dev);
1052 } else if (rdev->me_fw->size % 8) {
1054 rdev->me_fw->size, fw_name);
1056 release_firmware(rdev->me_fw);
1057 rdev->me_fw = NULL;
1062 u32 r100_gfx_get_rptr(struct radeon_device *rdev,
1067 if (rdev->wb.enabled)
1068 rptr = le32_to_cpu(rdev->wb.wb[ring->rptr_offs/4]);
1075 u32 r100_gfx_get_wptr(struct radeon_device *rdev,
1081 void r100_gfx_set_wptr(struct radeon_device *rdev,
1088 static void r100_cp_load_microcode(struct radeon_device *rdev)
1093 if (r100_gui_wait_for_idle(rdev)) {
1097 if (rdev->me_fw) {
1098 size = rdev->me_fw->size / 4;
1099 fw_data = (const __be32 *)&rdev->me_fw->data[0];
1110 int r100_cp_init(struct radeon_device *rdev, unsigned ring_size)
1112 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
1123 if (r100_debugfs_cp_init(rdev)) {
1126 if (!rdev->me_fw) {
1127 r = r100_cp_init_microcode(rdev);
1137 r100_cp_load_microcode(rdev);
1138 r = radeon_ring_init(rdev, ring, ring_size, RADEON_WB_CP_RPTR_OFFSET,
1188 S_00070C_RB_RPTR_ADDR((rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) >> 2));
1189 WREG32(R_000774_SCRATCH_ADDR, rdev->wb.gpu_addr + RADEON_WB_SCRATCH_OFFSET);
1191 if (rdev->wb.enabled)
1209 pci_set_master(rdev->pdev);
1211 radeon_ring_start(rdev, RADEON_RING_TYPE_GFX_INDEX, &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]);
1212 r = radeon_ring_test(rdev, RADEON_RING_TYPE_GFX_INDEX, ring);
1218 radeon_ttm_set_active_vram_size(rdev, rdev->mc.real_vram_size);
1221 && radeon_ring_supports_scratch_reg(rdev, ring)) {
1222 r = radeon_scratch_get(rdev, &ring->rptr_save_reg);
1231 void r100_cp_fini(struct radeon_device *rdev)
1233 if (r100_cp_wait_for_idle(rdev)) {
1237 r100_cp_disable(rdev);
1238 radeon_scratch_free(rdev, rdev->ring[RADEON_RING_TYPE_GFX_INDEX].rptr_save_reg);
1239 radeon_ring_fini(rdev, &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]);
1243 void r100_cp_disable(struct radeon_device *rdev)
1246 radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size);
1247 rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = false;
1251 if (r100_gui_wait_for_idle(rdev)) {
1465 crtc = drm_crtc_find(p->rdev->ddev, p->filp, crtc_id);
1960 r = r100_cs_track_check(p->rdev, track);
1972 r = r100_cs_track_check(p->rdev, track);
1984 r = r100_cs_track_check(p->rdev, track);
1991 r = r100_cs_track_check(p->rdev, track);
1998 r = r100_cs_track_check(p->rdev, track);
2005 r = r100_cs_track_check(p->rdev, track);
2012 r = r100_cs_track_check(p->rdev, track);
2019 if (p->rdev->hyperz_filp != p->filp)
2040 r100_cs_track_clear(p->rdev, track);
2050 if (p->rdev->family >= CHIP_R200)
2052 p->rdev->config.r100.reg_safe_bm,
2053 p->rdev->config.r100.reg_safe_bm_size,
2057 p->rdev->config.r100.reg_safe_bm,
2058 p->rdev->config.r100.reg_safe_bm_size,
2124 static int r100_cs_track_cube(struct radeon_device *rdev,
2155 static int r100_cs_track_texture_check(struct radeon_device *rdev,
2176 if (rdev->family < CHIP_R300)
2182 if (rdev->family >= CHIP_RV515)
2189 if (rdev->family >= CHIP_RV515)
2216 ret = r100_cs_track_cube(rdev, track, u);
2237 int r100_cs_track_check(struct radeon_device *rdev, struct r100_cs_track *track)
2323 dev_err(rdev->dev, "(PW %u) Vertex array %u "
2342 dev_err(rdev->dev, "(PW %u) Vertex array %u "
2369 return r100_cs_track_texture_check(rdev, track);
2374 void r100_cs_track_clear(struct radeon_device *rdev, struct r100_cs_track *track)
2383 if (rdev->family < CHIP_R300) {
2385 if (rdev->family <= CHIP_RS200)
2427 if (rdev->family <= CHIP_RS200) {
2454 static void r100_errata(struct radeon_device *rdev)
2456 rdev->pll_errata = 0;
2458 if (rdev->family == CHIP_RV200 || rdev->family == CHIP_RS200) {
2459 rdev->pll_errata |= CHIP_ERRATA_PLL_DUMMYREADS;
2462 if (rdev->family == CHIP_RV100 ||
2463 rdev->family == CHIP_RS100 ||
2464 rdev->family == CHIP_RS200) {
2465 rdev->pll_errata |= CHIP_ERRATA_PLL_DELAY;
2469 static int r100_rbbm_fifo_wait_for_entry(struct radeon_device *rdev, unsigned n)
2474 for (i = 0; i < rdev->usec_timeout; i++) {
2484 int r100_gui_wait_for_idle(struct radeon_device *rdev)
2489 if (r100_rbbm_fifo_wait_for_entry(rdev, 64)) {
2492 for (i = 0; i < rdev->usec_timeout; i++) {
2502 int r100_mc_wait_for_idle(struct radeon_device *rdev)
2507 for (i = 0; i < rdev->usec_timeout; i++) {
2518 bool r100_gpu_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring)
2524 radeon_ring_lockup_update(rdev, ring);
2527 return radeon_ring_test_lockup(rdev, ring);
2531 void r100_enable_bm(struct radeon_device *rdev)
2539 void r100_bm_disable(struct radeon_device *rdev)
2552 pci_clear_master(rdev->pdev);
2556 int r100_asic_reset(struct radeon_device *rdev, bool hard)
2566 r100_mc_stop(rdev, &save);
2568 dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status);
2577 pci_save_state(rdev->pdev);
2579 r100_bm_disable(rdev);
2589 dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status);
2597 dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status);
2599 pci_restore_state(rdev->pdev);
2600 r100_enable_bm(rdev);
2604 dev_err(rdev->dev, "failed to reset GPU\n");
2607 dev_info(rdev->dev, "GPU reset succeed\n");
2608 r100_mc_resume(rdev, &save);
2612 void r100_set_common_regs(struct radeon_device *rdev)
2614 struct drm_device *dev = rdev->ddev;
2699 static void r100_vram_get_type(struct radeon_device *rdev)
2703 rdev->mc.vram_is_ddr = false;
2704 if (rdev->flags & RADEON_IS_IGP)
2705 rdev->mc.vram_is_ddr = true;
2707 rdev->mc.vram_is_ddr = true;
2708 if ((rdev->family == CHIP_RV100) ||
2709 (rdev->family == CHIP_RS100) ||
2710 (rdev->family == CHIP_RS200)) {
2713 rdev->mc.vram_width = 32;
2715 rdev->mc.vram_width = 64;
2717 if (rdev->flags & RADEON_SINGLE_CRTC) {
2718 rdev->mc.vram_width /= 4;
2719 rdev->mc.vram_is_ddr = true;
2721 } else if (rdev->family <= CHIP_RV280) {
2724 rdev->mc.vram_width = 128;
2726 rdev->mc.vram_width = 64;
2730 rdev->mc.vram_width = 128;
2734 static u32 r100_get_accessible_vram(struct radeon_device *rdev)
2744 if (rdev->family == CHIP_RV280 ||
2745 rdev->family >= CHIP_RV350) {
2756 pci_read_config_byte(rdev->pdev, 0xe, &byte);
2772 void r100_vram_init_sizes(struct radeon_device *rdev)
2777 rdev->mc.aper_base = pci_resource_start(rdev->pdev, 0);
2778 rdev->mc.aper_size = pci_resource_len(rdev->pdev, 0);
2779 rdev->mc.visible_vram_size = r100_get_accessible_vram(rdev);
2781 if (rdev->mc.visible_vram_size > rdev->mc.aper_size)
2782 rdev->mc.visible_vram_size = rdev->mc.aper_size;
2784 if (rdev->flags & RADEON_IS_IGP) {
2788 rdev->mc.real_vram_size = (((tom >> 16) - (tom & 0xffff) + 1) << 16);
2789 WREG32(RADEON_CONFIG_MEMSIZE, rdev->mc.real_vram_size);
2790 rdev->mc.mc_vram_size = rdev->mc.real_vram_size;
2792 rdev->mc.real_vram_size = RREG32(RADEON_CONFIG_MEMSIZE);
2796 if (rdev->mc.real_vram_size == 0) {
2797 rdev->mc.real_vram_size = 8192 * 1024;
2798 WREG32(RADEON_CONFIG_MEMSIZE, rdev->mc.real_vram_size);
2803 if (rdev->mc.aper_size > config_aper_size)
2804 config_aper_size = rdev->mc.aper_size;
2806 if (config_aper_size > rdev->mc.real_vram_size)
2807 rdev->mc.mc_vram_size = config_aper_size;
2809 rdev->mc.mc_vram_size = rdev->mc.real_vram_size;
2813 void r100_vga_set_state(struct radeon_device *rdev, bool state)
2827 static void r100_mc_init(struct radeon_device *rdev)
2831 r100_vram_get_type(rdev);
2832 r100_vram_init_sizes(rdev);
2833 base = rdev->mc.aper_base;
2834 if (rdev->flags & RADEON_IS_IGP)
2836 radeon_vram_location(rdev, &rdev->mc, base);
2837 rdev->mc.gtt_base_align = 0;
2838 if (!(rdev->flags & RADEON_IS_AGP))
2839 radeon_gtt_location(rdev, &rdev->mc);
2840 radeon_update_bandwidth_info(rdev);
2847 void r100_pll_errata_after_index(struct radeon_device *rdev)
2849 if (rdev->pll_errata & CHIP_ERRATA_PLL_DUMMYREADS) {
2855 static void r100_pll_errata_after_data(struct radeon_device *rdev)
2860 if (rdev->pll_errata & CHIP_ERRATA_PLL_DELAY) {
2869 if (rdev->pll_errata & CHIP_ERRATA_R300_CG) {
2880 uint32_t r100_pll_rreg(struct radeon_device *rdev, uint32_t reg)
2885 spin_lock_irqsave(&rdev->pll_idx_lock, flags);
2887 r100_pll_errata_after_index(rdev);
2889 r100_pll_errata_after_data(rdev);
2890 spin_unlock_irqrestore(&rdev->pll_idx_lock, flags);
2894 void r100_pll_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
2898 spin_lock_irqsave(&rdev->pll_idx_lock, flags);
2900 r100_pll_errata_after_index(rdev);
2902 r100_pll_errata_after_data(rdev);
2903 spin_unlock_irqrestore(&rdev->pll_idx_lock, flags);
2906 static void r100_set_safe_registers(struct radeon_device *rdev)
2908 if (ASIC_IS_RN50(rdev)) {
2909 rdev->config.r100.reg_safe_bm = rn50_reg_safe_bm;
2910 rdev->config.r100.reg_safe_bm_size = ARRAY_SIZE(rn50_reg_safe_bm);
2911 } else if (rdev->family < CHIP_R200) {
2912 rdev->config.r100.reg_safe_bm = r100_reg_safe_bm;
2913 rdev->config.r100.reg_safe_bm_size = ARRAY_SIZE(r100_reg_safe_bm);
2915 r200_set_safe_registers(rdev);
2927 struct radeon_device *rdev = dev->dev_private;
2948 struct radeon_device *rdev = dev->dev_private;
2949 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
2953 radeon_ring_free_size(rdev, ring);
2976 struct radeon_device *rdev = dev->dev_private;
3026 struct radeon_device *rdev = dev->dev_private;
3066 int r100_debugfs_rbbm_init(struct radeon_device *rdev)
3069 return radeon_debugfs_add_files(rdev, r100_debugfs_rbbm_list, 1);
3075 int r100_debugfs_cp_init(struct radeon_device *rdev)
3078 return radeon_debugfs_add_files(rdev, r100_debugfs_cp_list, 2);
3084 int r100_debugfs_mc_info_init(struct radeon_device *rdev)
3087 return radeon_debugfs_add_files(rdev, r100_debugfs_mc_info_list, 1);
3093 int r100_set_surface_reg(struct radeon_device *rdev, int reg,
3100 if (rdev->family <= CHIP_RS200) {
3110 } else if (rdev->family <= CHIP_RV280) {
3128 if (rdev->family < CHIP_R300)
3141 void r100_clear_surface_reg(struct radeon_device *rdev, int reg)
3147 void r100_bandwidth_update(struct radeon_device *rdev)
3222 if (!rdev->mode_info.mode_config_initialized)
3225 radeon_update_display_priority(rdev);
3227 if (rdev->mode_info.crtcs[0]->base.enabled) {
3229 rdev->mode_info.crtcs[0]->base.primary->fb;
3231 mode1 = &rdev->mode_info.crtcs[0]->base.mode;
3234 if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
3235 if (rdev->mode_info.crtcs[1]->base.enabled) {
3237 rdev->mode_info.crtcs[1]->base.primary->fb;
3239 mode2 = &rdev->mode_info.crtcs[1]->base.mode;
3246 if ((rdev->disp_priority == 2) && ASIC_IS_R300(rdev)) {
3261 sclk_ff = rdev->pm.sclk;
3262 mclk_ff = rdev->pm.mclk;
3264 temp = (rdev->mc.vram_width / 8) * (rdev->mc.vram_is_ddr ? 2 : 1);
3294 if ((rdev->family == CHIP_RV100) || (rdev->flags & RADEON_IS_IGP)) { /* RV100, M6, IGPs */
3298 } else if (rdev->family == CHIP_R300 ||
3299 rdev->family == CHIP_R350) { /* r300, r350 */
3303 } else if (rdev->family == CHIP_RV350 ||
3304 rdev->family == CHIP_RV380) {
3309 } else if (rdev->family == CHIP_R420 ||
3310 rdev->family == CHIP_R423 ||
3311 rdev->family == CHIP_RV410) {
3335 if ((rdev->family == CHIP_RV100) || rdev->flags & RADEON_IS_IGP) {
3336 if (rdev->family == CHIP_RS480) /* don't think rs400 */
3343 if (rdev->family == CHIP_RS400 ||
3344 rdev->family == CHIP_RS480) {
3351 if (ASIC_IS_R300(rdev) && !(rdev->flags & RADEON_IS_IGP)) {
3372 if (rdev->family == CHIP_RV410 ||
3373 rdev->family == CHIP_R420 ||
3374 rdev->family == CHIP_R423)
3383 if (rdev->flags & RADEON_IS_AGP) {
3391 if (ASIC_IS_R300(rdev)) {
3394 if ((rdev->family == CHIP_RV100) ||
3395 rdev->flags & RADEON_IS_IGP) {
3396 if (rdev->mc.vram_is_ddr)
3401 if (rdev->mc.vram_width == 128)
3410 if (rdev->mc.vram_is_ddr) {
3411 if (rdev->mc.vram_width == 32) {
3438 temp_ff.full = dfixed_const((2 * (cur_size - (rdev->mc.vram_is_ddr + 1))));
3460 if (ASIC_IS_RV100(rdev))
3489 if (rdev->disp_priority == 2) {
3500 if (critical_point == 0 && mode2 && rdev->family == CHIP_R300) {
3509 if ((rdev->family == CHIP_R350) &&
3525 if ((rdev->family == CHIP_RS400) ||
3526 (rdev->family == CHIP_RS480)) {
3565 if ((rdev->family == CHIP_R350) &&
3575 if ((rdev->family == CHIP_RS100) ||
3576 (rdev->family == CHIP_RS200))
3579 temp = (rdev->mc.vram_width * rdev->mc.vram_is_ddr + 1)/128;
3599 if (rdev->disp_priority == 2) {
3608 if (critical_point2 == 0 && rdev->family == CHIP_R300) {
3616 if ((rdev->family == CHIP_RS400) ||
3617 (rdev->family == CHIP_RS480)) {
3645 rdev->mode_info.crtcs[0]->lb_vblank_lead_lines = DIV_ROUND_UP(lb_size, mode1->crtc_hdisplay);
3648 rdev->mode_info.crtcs[1]->lb_vblank_lead_lines = DIV_ROUND_UP(lb_size, mode2->crtc_hdisplay);
3651 int r100_ring_test(struct radeon_device *rdev, struct radeon_ring *ring)
3658 r = radeon_scratch_get(rdev, &scratch);
3664 r = radeon_ring_lock(rdev, ring, 2);
3667 radeon_scratch_free(rdev, scratch);
3672 radeon_ring_unlock_commit(rdev, ring, false);
3673 for (i = 0; i < rdev->usec_timeout; i++) {
3680 if (i < rdev->usec_timeout) {
3687 radeon_scratch_free(rdev, scratch);
3691 void r100_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib)
3693 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
3706 int r100_ib_test(struct radeon_device *rdev, struct radeon_ring *ring)
3714 r = radeon_scratch_get(rdev, &scratch);
3720 r = radeon_ib_get(rdev, RADEON_RING_TYPE_GFX_INDEX, &ib, NULL, 256);
3734 r = radeon_ib_schedule(rdev, &ib, NULL, false);
3750 for (i = 0; i < rdev->usec_timeout; i++) {
3757 if (i < rdev->usec_timeout) {
3765 radeon_ib_free(rdev, &ib);
3767 radeon_scratch_free(rdev, scratch);
3771 void r100_mc_stop(struct radeon_device *rdev, struct r100_mc_save *save)
3776 rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = false;
3784 if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
3801 if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
3813 void r100_mc_resume(struct radeon_device *rdev, struct r100_mc_save *save)
3816 WREG32(R_00023C_DISPLAY_BASE_ADDR, rdev->mc.vram_start);
3817 if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
3818 WREG32(R_00033C_CRTC2_DISPLAY_BASE_ADDR, rdev->mc.vram_start);
3824 if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
3829 void r100_vga_render_disable(struct radeon_device *rdev)
3837 static void r100_debugfs(struct radeon_device *rdev)
3841 r = r100_debugfs_mc_info_init(rdev);
3843 dev_warn(rdev->dev, "Failed to create r100_mc debugfs file.\n");
3846 static void r100_mc_program(struct radeon_device *rdev)
3851 r100_mc_stop(rdev, &save);
3852 if (rdev->flags & RADEON_IS_AGP) {
3854 S_00014C_MC_AGP_START(rdev->mc.gtt_start >> 16) |
3855 S_00014C_MC_AGP_TOP(rdev->mc.gtt_end >> 16));
3856 WREG32(R_000170_AGP_BASE, lower_32_bits(rdev->mc.agp_base));
3857 if (rdev->family > CHIP_RV200)
3859 upper_32_bits(rdev->mc.agp_base) & 0xff);
3863 if (rdev->family > CHIP_RV200)
3867 if (r100_mc_wait_for_idle(rdev))
3868 dev_warn(rdev->dev, "Wait for MC idle timeout.\n");
3871 S_000148_MC_FB_START(rdev->mc.vram_start >> 16) |
3872 S_000148_MC_FB_TOP(rdev->mc.vram_end >> 16));
3873 r100_mc_resume(rdev, &save);
3876 static void r100_clock_startup(struct radeon_device *rdev)
3881 radeon_legacy_set_clock_gating(rdev, 1);
3885 if ((rdev->family == CHIP_RV250) || (rdev->family == CHIP_RV280))
3890 static int r100_startup(struct radeon_device *rdev)
3895 r100_set_common_regs(rdev);
3897 r100_mc_program(rdev);
3899 r100_clock_startup(rdev);
3902 r100_enable_bm(rdev);
3903 if (rdev->flags & RADEON_IS_PCI) {
3904 r = r100_pci_gart_enable(rdev);
3910 r = radeon_wb_init(rdev);
3914 r = radeon_fence_driver_start_ring(rdev, RADEON_RING_TYPE_GFX_INDEX);
3916 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r);
3921 if (!rdev->irq.installed) {
3922 r = radeon_irq_kms_init(rdev);
3927 r100_irq_set(rdev);
3928 rdev->config.r100.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL);
3930 r = r100_cp_init(rdev, 1024 * 1024);
3932 dev_err(rdev->dev, "failed initializing CP (%d).\n", r);
3936 r = radeon_ib_pool_init(rdev);
3938 dev_err(rdev->dev, "IB initialization failed (%d).\n", r);
3945 int r100_resume(struct radeon_device *rdev)
3950 if (rdev->flags & RADEON_IS_PCI)
3951 r100_pci_gart_disable(rdev);
3953 r100_clock_startup(rdev);
3955 if (radeon_asic_reset(rdev)) {
3956 dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
3961 radeon_combios_asic_init(rdev->ddev);
3963 r100_clock_startup(rdev);
3965 radeon_surface_init(rdev);
3967 rdev->accel_working = true;
3968 r = r100_startup(rdev);
3970 rdev->accel_working = false;
3975 int r100_suspend(struct radeon_device *rdev)
3977 radeon_pm_suspend(rdev);
3978 r100_cp_disable(rdev);
3979 radeon_wb_disable(rdev);
3980 r100_irq_disable(rdev);
3981 if (rdev->flags & RADEON_IS_PCI)
3982 r100_pci_gart_disable(rdev);
3986 void r100_fini(struct radeon_device *rdev)
3988 radeon_pm_fini(rdev);
3989 r100_cp_fini(rdev);
3990 radeon_wb_fini(rdev);
3991 radeon_ib_pool_fini(rdev);
3992 radeon_gem_fini(rdev);
3993 if (rdev->flags & RADEON_IS_PCI)
3994 r100_pci_gart_fini(rdev);
3995 radeon_agp_fini(rdev);
3996 radeon_irq_kms_fini(rdev);
3997 radeon_fence_driver_fini(rdev);
3998 radeon_bo_fini(rdev);
3999 radeon_atombios_fini(rdev);
4000 kfree(rdev->bios);
4001 rdev->bios = NULL;
4011 void r100_restore_sanity(struct radeon_device *rdev)
4029 int r100_init(struct radeon_device *rdev)
4034 r100_debugfs(rdev);
4036 r100_vga_render_disable(rdev);
4038 radeon_scratch_init(rdev);
4040 radeon_surface_init(rdev);
4042 r100_restore_sanity(rdev);
4045 if (!radeon_get_bios(rdev)) {
4046 if (ASIC_IS_AVIVO(rdev))
4049 if (rdev->is_atom_bios) {
4050 dev_err(rdev->dev, "Expecting combios for RS400/RS480 GPU\n");
4053 r = radeon_combios_init(rdev);
4058 if (radeon_asic_reset(rdev)) {
4059 dev_warn(rdev->dev,
4065 if (radeon_boot_test_post_card(rdev) == false)
4068 r100_errata(rdev);
4070 radeon_get_clock_info(rdev->ddev);
4072 if (rdev->flags & RADEON_IS_AGP) {
4073 r = radeon_agp_init(rdev);
4075 radeon_agp_disable(rdev);
4079 r100_mc_init(rdev);
4081 r = radeon_fence_driver_init(rdev);
4085 r = radeon_bo_init(rdev);
4088 if (rdev->flags & RADEON_IS_PCI) {
4089 r = r100_pci_gart_init(rdev);
4093 r100_set_safe_registers(rdev);
4096 radeon_pm_init(rdev);
4098 rdev->accel_working = true;
4099 r = r100_startup(rdev);
4102 dev_err(rdev->dev, "Disabling GPU acceleration\n");
4103 r100_cp_fini(rdev);
4104 radeon_wb_fini(rdev);
4105 radeon_ib_pool_fini(rdev);
4106 radeon_irq_kms_fini(rdev);
4107 if (rdev->flags & RADEON_IS_PCI)
4108 r100_pci_gart_fini(rdev);
4109 rdev->accel_working = false;
4114 uint32_t r100_mm_rreg_slow(struct radeon_device *rdev, uint32_t reg)
4119 spin_lock_irqsave(&rdev->mmio_idx_lock, flags);
4120 writel(reg, ((void __iomem *)rdev->rmmio) + RADEON_MM_INDEX);
4121 ret = readl(((void __iomem *)rdev->rmmio) + RADEON_MM_DATA);
4122 spin_unlock_irqrestore(&rdev->mmio_idx_lock, flags);
4126 void r100_mm_wreg_slow(struct radeon_device *rdev, uint32_t reg, uint32_t v)
4130 spin_lock_irqsave(&rdev->mmio_idx_lock, flags);
4131 writel(reg, ((void __iomem *)rdev->rmmio) + RADEON_MM_INDEX);
4132 writel(v, ((void __iomem *)rdev->rmmio) + RADEON_MM_DATA);
4133 spin_unlock_irqrestore(&rdev->mmio_idx_lock, flags);
4136 u32 r100_io_rreg(struct radeon_device *rdev, u32 reg)
4138 if (reg < rdev->rio_mem_size)
4139 return ioread32(rdev->rio_mem + reg);
4141 iowrite32(reg, rdev->rio_mem + RADEON_MM_INDEX);
4142 return ioread32(rdev->rio_mem + RADEON_MM_DATA);
4146 void r100_io_wreg(struct radeon_device *rdev, u32 reg, u32 v)
4148 if (reg < rdev->rio_mem_size)
4149 iowrite32(v, rdev->rio_mem + reg);
4151 iowrite32(reg, rdev->rio_mem + RADEON_MM_INDEX);
4152 iowrite32(v, rdev->rio_mem + RADEON_MM_DATA);