Lines Matching refs:vddc
746 s64 kt, kv, leakage_w, i_leakage, vddc, temperature;
749 vddc = div64_s64(drm_int2fixp(v), 1000);
755 drm_fixp_exp(drm_fixp_mul(div64_s64(drm_int2fixp(coeff->bv), 1000), vddc)));
757 leakage_w = drm_fixp_mul(drm_fixp_mul(drm_fixp_mul(i_leakage, kt), kv), vddc);
813 if (ps->performance_levels[i].vddc > max_limits->vddc)
814 ps->performance_levels[i].vddc = max_limits->vddc;
837 if (ps->performance_levels[i].vddc < ps->performance_levels[i - 1].vddc)
838 ps->performance_levels[i].vddc = ps->performance_levels[i - 1].vddc;
876 max_limits->vddc, &ps->performance_levels[i].vddc);
882 max_limits->vddc, &ps->performance_levels[i].vddc);
885 max_limits->vddc, &ps->performance_levels[i].vddc);
890 max_limits->vddc, max_limits->vddci,
891 &ps->performance_levels[i].vddc,
897 if (ps->performance_levels[i].vddc > rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc.vddc)
900 if (ps->performance_levels[i].vddc < rdev->pm.dpm.dyn_state.min_vddc_for_pcie_gen2)
1349 *std_voltage = rdev->pm.dpm.dyn_state.cac_leakage_table.entries[voltage->index].vddc;
1393 NISLANDS_SMC_VOLTAGE_VALUE vddc;
1402 state->performance_levels[state->performance_level_count - 2].vddc,
1403 &vddc);
1407 ret = ni_get_std_voltage_value(rdev, &vddc, &std_vddc_med);
1412 state->performance_levels[state->performance_level_count - 1].vddc,
1413 &vddc);
1417 ret = ni_get_std_voltage_value(rdev, &vddc, &std_vddc_high);
1730 initial_state->performance_levels[0].vddc,
1731 &table->initialState.levels[0].vddc);
1736 &table->initialState.levels[0].vddc,
1740 table->initialState.levels[0].vddc.index,
1817 pi->acpi_vddc, &table->ACPIState.levels[0].vddc);
1822 &table->ACPIState.levels[0].vddc, &std_vddc);
1825 table->ACPIState.levels[0].vddc.index,
1841 &table->ACPIState.levels[0].vddc);
1846 &table->ACPIState.levels[0].vddc,
1850 table->ACPIState.levels[0].vddc.index,
2370 pl->vddc, &level->vddc);
2374 ret = ni_get_std_voltage_value(rdev, &level->vddc, &std_vddc);
2379 level->vddc.index, &level->std_vddc);
3938 pl->vddc = le16_to_cpu(clock_info->evergreen.usVDDC);
3942 /* patch up vddc if necessary */
3943 if (pl->vddc == 0xff01) {
3945 pl->vddc = pi->max_vddc;
3949 pi->acpi_vddc = pl->vddc;
3962 if (pi->min_vddc_in_table > pl->vddc)
3963 pi->min_vddc_in_table = pl->vddc;
3965 if (pi->max_vddc_in_table < pl->vddc)
3966 pi->max_vddc_in_table = pl->vddc;
3970 u16 vddc, vddci, mvdd;
3971 radeon_atombios_get_default_voltages(rdev, &vddc, &vddci, &mvdd);
3974 pl->vddc = vddc;
3982 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.vddc = pl->vddc;
4297 printk("\t\tpower level %d sclk: %u mclk: %u vddc: %u vddci: %u pcie gen: %u\n",
4298 i, pl->sclk, pl->mclk, pl->vddc, pl->vddci, pl->pcie_gen + 1);
4300 printk("\t\tpower level %d sclk: %u mclk: %u vddc: %u vddci: %u\n",
4301 i, pl->sclk, pl->mclk, pl->vddc, pl->vddci);
4322 seq_printf(m, "power level %d sclk: %u mclk: %u vddc: %u vddci: %u\n",
4323 current_index, pl->sclk, pl->mclk, pl->vddc, pl->vddci);