Lines Matching refs:ret
1010 int ret = 0;
1012 ret = ni_patch_single_dependency_table_based_on_leakage(rdev,
1015 ret = ni_patch_single_dependency_table_based_on_leakage(rdev,
1017 return ret;
1104 int ret;
1106 ret = rv770_read_smc_sram_dword(rdev,
1111 if (ret)
1112 return ret;
1116 ret = rv770_read_smc_sram_dword(rdev,
1121 if (ret)
1122 return ret;
1126 ret = rv770_read_smc_sram_dword(rdev,
1131 if (ret)
1132 return ret;
1136 ret = rv770_read_smc_sram_dword(rdev,
1141 if (ret)
1142 return ret;
1146 ret = rv770_read_smc_sram_dword(rdev,
1151 if (ret)
1152 return ret;
1156 ret = rv770_read_smc_sram_dword(rdev,
1161 if (ret)
1162 return ret;
1166 ret = rv770_read_smc_sram_dword(rdev,
1171 if (ret)
1172 return ret;
1177 return ret;
1389 int ret;
1401 ret = ni_populate_voltage_value(rdev, &eg_pi->vddc_voltage_table,
1404 if (ret)
1407 ret = ni_get_std_voltage_value(rdev, &vddc, &std_vddc_med);
1408 if (ret)
1411 ret = ni_populate_voltage_value(rdev, &eg_pi->vddc_voltage_table,
1414 if (ret)
1417 ret = ni_get_std_voltage_value(rdev, &vddc, &std_vddc_high);
1418 if (ret)
1465 int ret;
1472 ret = ni_calculate_adjusted_tdp_limits(rdev,
1477 if (ret)
1478 return ret;
1493 ret = rv770_copy_bytes_to_smc(rdev,
1498 if (ret)
1499 return ret;
1575 int ret;
1577 ret = rv770_read_smc_sram_dword(rdev, ni_pi->arb_table_start,
1579 if (ret)
1580 return ret;
1599 int ret;
1601 ret = rv770_read_smc_sram_dword(rdev, ni_pi->arb_table_start,
1603 if (ret)
1604 return ret;
1644 int i, ret = 0;
1647 ret = ni_populate_memory_timing_parameters(rdev, &state->performance_levels[i], &arb_regs);
1648 if (ret)
1651 ret = rv770_copy_bytes_to_smc(rdev,
1658 if (ret)
1661 return ret;
1689 int ret;
1729 ret = ni_populate_voltage_value(rdev, &eg_pi->vddc_voltage_table,
1732 if (!ret) {
1735 ret = ni_get_std_voltage_value(rdev,
1738 if (!ret)
1808 int ret;
1815 ret = ni_populate_voltage_value(rdev,
1818 if (!ret) {
1821 ret = ni_get_std_voltage_value(rdev,
1823 if (!ret)
1838 ret = ni_populate_voltage_value(rdev,
1842 if (!ret) {
1845 ret = ni_get_std_voltage_value(rdev,
1848 if (!ret)
1943 int ret;
1976 ret = ni_populate_smc_initial_state(rdev, radeon_boot_state, table);
1977 if (ret)
1978 return ret;
1980 ret = ni_populate_smc_acpi_state(rdev, table);
1981 if (ret)
1982 return ret;
1988 ret = ni_do_program_memory_timing_parameters(rdev, radeon_boot_state,
1990 if (ret)
1991 return ret;
2014 int ret;
2016 ret = radeon_atom_get_clock_dividers(rdev, COMPUTE_ENGINE_PLL_PARAM,
2018 if (ret)
2019 return ret;
2073 int ret;
2075 ret = ni_calculate_sclk_params(rdev, engine_clock, &sclk_tmp);
2076 if (!ret) {
2086 return ret;
2100 int i, ret;
2111 ret = ni_calculate_sclk_params(rdev, sclk, &sclk_params);
2112 if (ret)
2125 ret = -EINVAL;
2128 ret = -EINVAL;
2131 ret = -EINVAL;
2134 ret = -EINVAL;
2136 if (ret)
2150 if (!ret)
2151 ret = rv770_copy_bytes_to_smc(rdev, ni_pi->spll_table_start, (u8 *)spll_table,
2156 return ret;
2179 int ret;
2182 ret = radeon_atom_get_clock_dividers(rdev, COMPUTE_MEMORY_PLL_PARAM,
2184 if (ret)
2185 return ret;
2319 int ret;
2327 ret = ni_populate_sclk_value(rdev, pl->sclk, &level->sclk);
2328 if (ret)
2329 return ret;
2359 ret = ni_populate_mclk_value(rdev, pl->sclk, pl->mclk,
2364 ret = ni_populate_mclk_value(rdev, pl->sclk, pl->mclk, &level->mclk, 1, 1);
2366 if (ret)
2367 return ret;
2369 ret = ni_populate_voltage_value(rdev, &eg_pi->vddc_voltage_table,
2371 if (ret)
2372 return ret;
2374 ret = ni_get_std_voltage_value(rdev, &level->vddc, &std_vddc);
2375 if (ret)
2376 return ret;
2382 ret = ni_populate_voltage_value(rdev, &eg_pi->vddci_voltage_table,
2384 if (ret)
2385 return ret;
2390 return ret;
2403 int i, ret;
2418 ret = r600_calculate_at(
2426 ret = r600_calculate_at(
2434 if (ret) {
2464 int i, ret;
2479 ret = ni_calculate_adjusted_tdp_limits(rdev,
2484 if (ret)
2485 return ret;
2489 ret = rv770_write_smc_sram_dword(rdev,
2495 if (ret)
2603 int ret = 0;
2610 ret = -EINVAL;
2619 ret = -EINVAL;
2624 return ret;
2634 int i, ret;
2646 ret = ni_convert_power_level_to_smc(rdev, &state->performance_levels[i],
2651 if (ret)
2652 return ret;
2675 ret = ni_populate_power_containment_values(rdev, radeon_state, smc_state);
2676 if (ret)
2679 ret = ni_populate_sq_ramping_values(rdev, radeon_state, smc_state);
2680 if (ret)
2695 int ret;
2701 ret = ni_convert_power_state_to_smc(rdev, radeon_new_state, smc_state);
2702 if (ret)
2705 ret = rv770_copy_bytes_to_smc(rdev, address, (u8 *)smc_state, state_size, pi->sram_end);
2710 return ret;
2876 int ret;
2899 ret = radeon_atom_init_mc_reg_table(rdev, module_index, table);
2901 if (ret)
2904 ret = ni_copy_vbios_mc_reg_table(table, ni_table);
2906 if (ret)
2911 ret = ni_set_mc_special_registers(rdev, ni_table);
2913 if (ret)
2921 return ret;
3146 int i, ret;
3179 ret = ni_init_driver_calculated_leakage_table(rdev, cac_tables);
3181 ret = ni_init_simplified_leakage_table(rdev, cac_tables);
3183 if (ret)
3196 ret = rv770_copy_bytes_to_smc(rdev, ni_pi->cac_table_start, (u8 *)cac_tables,
3200 if (ret) {
3384 int ret = 0;
3400 ret = -EINVAL;
3417 return ret;
3592 int ret;
3604 ret = cypress_construct_voltage_tables(rdev);
3605 if (ret) {
3607 return ret;
3611 ret = ni_initialize_mc_reg_table(rdev);
3612 if (ret)
3628 ret = rv770_upload_firmware(rdev);
3629 if (ret) {
3631 return ret;
3633 ret = ni_process_firmware_header(rdev);
3634 if (ret) {
3636 return ret;
3638 ret = ni_initial_switch_from_arb_f0_to_f1(rdev);
3639 if (ret) {
3641 return ret;
3643 ret = ni_init_smc_table(rdev);
3644 if (ret) {
3646 return ret;
3648 ret = ni_init_smc_spll_table(rdev);
3649 if (ret) {
3651 return ret;
3653 ret = ni_init_arb_table_index(rdev);
3654 if (ret) {
3656 return ret;
3659 ret = ni_populate_mc_reg_table(rdev, boot_ps);
3660 if (ret) {
3662 return ret;
3665 ret = ni_initialize_smc_cac_tables(rdev);
3666 if (ret) {
3668 return ret;
3670 ret = ni_initialize_hardware_cac_manager(rdev);
3671 if (ret) {
3673 return ret;
3675 ret = ni_populate_smc_tdp_limits(rdev, boot_ps);
3676 if (ret) {
3678 return ret;
3682 ret = cypress_notify_smc_display_change(rdev, false);
3683 if (ret) {
3685 return ret;
3746 int ret;
3748 ret = ni_restrict_performance_levels_before_switch(rdev);
3749 if (ret)
3750 return ret;
3751 ret = rv770_halt_smc(rdev);
3752 if (ret)
3753 return ret;
3754 ret = ni_populate_smc_tdp_limits(rdev, new_ps);
3755 if (ret)
3756 return ret;
3757 ret = rv770_resume_smc(rdev);
3758 if (ret)
3759 return ret;
3760 ret = rv770_set_sw_state(rdev);
3761 if (ret)
3762 return ret;
3785 int ret;
3787 ret = ni_restrict_performance_levels_before_switch(rdev);
3788 if (ret) {
3790 return ret;
3793 ret = ni_enable_power_containment(rdev, new_ps, false);
3794 if (ret) {
3796 return ret;
3798 ret = ni_enable_smc_cac(rdev, new_ps, false);
3799 if (ret) {
3801 return ret;
3803 ret = rv770_halt_smc(rdev);
3804 if (ret) {
3806 return ret;
3810 ret = ni_upload_sw_state(rdev, new_ps);
3811 if (ret) {
3813 return ret;
3816 ret = ni_upload_mc_reg_table(rdev, new_ps);
3817 if (ret) {
3819 return ret;
3822 ret = ni_program_memory_timing_parameters(rdev, new_ps);
3823 if (ret) {
3825 return ret;
3827 ret = rv770_resume_smc(rdev);
3828 if (ret) {
3830 return ret;
3832 ret = rv770_set_sw_state(rdev);
3833 if (ret) {
3835 return ret;
3838 ret = ni_enable_smc_cac(rdev, new_ps, true);
3839 if (ret) {
3841 return ret;
3843 ret = ni_enable_power_containment(rdev, new_ps, true);
3844 if (ret) {
3846 return ret;
3850 ret = ni_power_control_set_level(rdev);
3851 if (ret) {
3853 return ret;
4054 int ret;
4071 ret = r600_get_platform_caps(rdev);
4072 if (ret)
4073 return ret;
4075 ret = ni_parse_power_table(rdev);
4076 if (ret)
4077 return ret;
4078 ret = r600_parse_extended_power_table(rdev);
4079 if (ret)
4080 return ret;
4107 ret = radeon_atom_get_clock_dividers(rdev, COMPUTE_ENGINE_PLL_PARAM,
4109 if (ret)