Lines Matching refs:levels
1691 table->initialState.levels[0].mclk.vMPLL_AD_FUNC_CNTL =
1693 table->initialState.levels[0].mclk.vMPLL_AD_FUNC_CNTL_2 =
1695 table->initialState.levels[0].mclk.vMPLL_DQ_FUNC_CNTL =
1697 table->initialState.levels[0].mclk.vMPLL_DQ_FUNC_CNTL_2 =
1699 table->initialState.levels[0].mclk.vMCLK_PWRMGT_CNTL =
1701 table->initialState.levels[0].mclk.vDLL_CNTL =
1703 table->initialState.levels[0].mclk.vMPLL_SS =
1705 table->initialState.levels[0].mclk.vMPLL_SS2 =
1707 table->initialState.levels[0].mclk.mclk_value =
1710 table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL =
1712 table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_2 =
1714 table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_3 =
1716 table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_4 =
1718 table->initialState.levels[0].sclk.vCG_SPLL_SPREAD_SPECTRUM =
1720 table->initialState.levels[0].sclk.vCG_SPLL_SPREAD_SPECTRUM_2 =
1722 table->initialState.levels[0].sclk.sclk_value =
1724 table->initialState.levels[0].arbRefreshState =
1727 table->initialState.levels[0].ACIndex = 0;
1731 &table->initialState.levels[0].vddc);
1736 &table->initialState.levels[0].vddc,
1740 table->initialState.levels[0].vddc.index,
1741 &table->initialState.levels[0].std_vddc);
1748 &table->initialState.levels[0].vddci);
1750 ni_populate_initial_mvdd_value(rdev, &table->initialState.levels[0].mvdd);
1753 table->initialState.levels[0].aT = cpu_to_be32(reg);
1755 table->initialState.levels[0].bSP = cpu_to_be32(pi->dsp);
1758 table->initialState.levels[0].gen2PCIE = 1;
1760 table->initialState.levels[0].gen2PCIE = 0;
1763 table->initialState.levels[0].strobeMode =
1768 table->initialState.levels[0].mcFlags = NISLANDS_SMC_MC_EDC_RD_FLAG | NISLANDS_SMC_MC_EDC_WR_FLAG;
1770 table->initialState.levels[0].mcFlags = 0;
1777 table->initialState.levels[0].dpm2.MaxPS = 0;
1778 table->initialState.levels[0].dpm2.NearTDPDec = 0;
1779 table->initialState.levels[0].dpm2.AboveSafeInc = 0;
1780 table->initialState.levels[0].dpm2.BelowSafeInc = 0;
1783 table->initialState.levels[0].SQPowerThrottle = cpu_to_be32(reg);
1786 table->initialState.levels[0].SQPowerThrottle_2 = cpu_to_be32(reg);
1817 pi->acpi_vddc, &table->ACPIState.levels[0].vddc);
1822 &table->ACPIState.levels[0].vddc, &std_vddc);
1825 table->ACPIState.levels[0].vddc.index,
1826 &table->ACPIState.levels[0].std_vddc);
1831 table->ACPIState.levels[0].gen2PCIE = 1;
1833 table->ACPIState.levels[0].gen2PCIE = 0;
1835 table->ACPIState.levels[0].gen2PCIE = 0;
1841 &table->ACPIState.levels[0].vddc);
1846 &table->ACPIState.levels[0].vddc,
1850 table->ACPIState.levels[0].vddc.index,
1851 &table->ACPIState.levels[0].std_vddc);
1853 table->ACPIState.levels[0].gen2PCIE = 0;
1861 &table->ACPIState.levels[0].vddci);
1904 table->ACPIState.levels[0].mclk.vMPLL_AD_FUNC_CNTL = cpu_to_be32(mpll_ad_func_cntl);
1905 table->ACPIState.levels[0].mclk.vMPLL_AD_FUNC_CNTL_2 = cpu_to_be32(mpll_ad_func_cntl_2);
1906 table->ACPIState.levels[0].mclk.vMPLL_DQ_FUNC_CNTL = cpu_to_be32(mpll_dq_func_cntl);
1907 table->ACPIState.levels[0].mclk.vMPLL_DQ_FUNC_CNTL_2 = cpu_to_be32(mpll_dq_func_cntl_2);
1908 table->ACPIState.levels[0].mclk.vMCLK_PWRMGT_CNTL = cpu_to_be32(mclk_pwrmgt_cntl);
1909 table->ACPIState.levels[0].mclk.vDLL_CNTL = cpu_to_be32(dll_cntl);
1911 table->ACPIState.levels[0].mclk.mclk_value = 0;
1913 table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL = cpu_to_be32(spll_func_cntl);
1914 table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_2 = cpu_to_be32(spll_func_cntl_2);
1915 table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_3 = cpu_to_be32(spll_func_cntl_3);
1916 table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_4 = cpu_to_be32(spll_func_cntl_4);
1918 table->ACPIState.levels[0].sclk.sclk_value = 0;
1920 ni_populate_mvdd_value(rdev, 0, &table->ACPIState.levels[0].mvdd);
1923 table->ACPIState.levels[0].ACIndex = 1;
1925 table->ACPIState.levels[0].dpm2.MaxPS = 0;
1926 table->ACPIState.levels[0].dpm2.NearTDPDec = 0;
1927 table->ACPIState.levels[0].dpm2.AboveSafeInc = 0;
1928 table->ACPIState.levels[0].dpm2.BelowSafeInc = 0;
1931 table->ACPIState.levels[0].SQPowerThrottle = cpu_to_be32(reg);
1934 table->ACPIState.levels[0].SQPowerThrottle_2 = cpu_to_be32(reg);
2306 smc_state->levels[i].bSP = cpu_to_be32(pi->dsp);
2308 smc_state->levels[ps->performance_level_count - 1].bSP =
2410 smc_state->levels[0].aT = cpu_to_be32(a_t);
2414 smc_state->levels[0].aT = cpu_to_be32(0);
2439 a_t = be32_to_cpu(smc_state->levels[i].aT) & ~CG_R_MASK;
2441 smc_state->levels[i].aT = cpu_to_be32(a_t);
2447 smc_state->levels[i + 1].aT = cpu_to_be32(a_t);
2498 smc_state->levels[0].dpm2.MaxPS = 0;
2499 smc_state->levels[0].dpm2.NearTDPDec = 0;
2500 smc_state->levels[0].dpm2.AboveSafeInc = 0;
2501 smc_state->levels[0].dpm2.BelowSafeInc = 0;
2502 smc_state->levels[0].stateFlags |= power_boost_limit ? PPSMC_STATEFLAG_POWERBOOST : 0;
2526 smc_state->levels[i].dpm2.MaxPS =
2528 smc_state->levels[i].dpm2.NearTDPDec = NISLANDS_DPM2_NEAR_TDP_DEC;
2529 smc_state->levels[i].dpm2.AboveSafeInc = NISLANDS_DPM2_ABOVE_SAFE_INC;
2530 smc_state->levels[i].dpm2.BelowSafeInc = NISLANDS_DPM2_BELOW_SAFE_INC;
2531 smc_state->levels[i].stateFlags |=
2590 smc_state->levels[i].SQPowerThrottle = cpu_to_be32(sq_power_throttle);
2591 smc_state->levels[i].SQPowerThrottle_2 = cpu_to_be32(sq_power_throttle2);
2647 &smc_state->levels[i]);
2648 smc_state->levels[i].arbRefreshState =
2655 smc_state->levels[i].displayWatermark =
2659 smc_state->levels[i].displayWatermark = (i < 2) ?
2663 smc_state->levels[i].ACIndex = NISLANDS_MCREGISTERTABLE_FIRST_DRIVERSTATE_SLOT + i;
2665 smc_state->levels[i].ACIndex = 0;
2693 size_t state_size = struct_size(smc_state, levels,