Lines Matching defs:rdev
722 struct rv7xx_power_info *rv770_get_pi(struct radeon_device *rdev);
723 struct evergreen_power_info *evergreen_get_pi(struct radeon_device *rdev);
725 extern int ni_mc_load_microcode(struct radeon_device *rdev);
727 struct ni_power_info *ni_get_pi(struct radeon_device *rdev)
729 struct ni_power_info *pi = rdev->pm.dpm.priv;
762 static void ni_calculate_leakage_for_v_and_t(struct radeon_device *rdev,
772 bool ni_dpm_vblank_too_short(struct radeon_device *rdev)
774 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
775 u32 vblank_time = r600_dpm_get_vblank_time(rdev);
786 static void ni_apply_state_adjust_rules(struct radeon_device *rdev,
796 if ((rdev->pm.dpm.new_active_crtc_count > 1) ||
797 ni_dpm_vblank_too_short(rdev))
802 if (rdev->pm.dpm.ac_power)
803 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac;
805 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc;
807 if (rdev->pm.dpm.ac_power == false) {
830 btc_skip_blacklist_clocks(rdev, max_limits->sclk, max_limits->mclk,
865 btc_skip_blacklist_clocks(rdev, max_limits->sclk, max_limits->mclk,
870 btc_adjust_clock_combinations(rdev, max_limits,
874 btc_apply_voltage_dependency_rules(&rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk,
877 btc_apply_voltage_dependency_rules(&rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk,
880 btc_apply_voltage_dependency_rules(&rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk,
883 btc_apply_voltage_dependency_rules(&rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk,
884 rdev->clock.current_dispclk,
889 btc_apply_voltage_delta_rules(rdev,
897 if (ps->performance_levels[i].vddc > rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc.vddc)
900 if (ps->performance_levels[i].vddc < rdev->pm.dpm.dyn_state.min_vddc_for_pcie_gen2)
905 static void ni_cg_clockgating_default(struct radeon_device *rdev)
913 btc_program_mgcg_hw_sequence(rdev, ps, count);
916 static void ni_gfx_clockgating_enable(struct radeon_device *rdev,
930 btc_program_mgcg_hw_sequence(rdev, ps, count);
933 static void ni_mg_clockgating_default(struct radeon_device *rdev)
941 btc_program_mgcg_hw_sequence(rdev, ps, count);
944 static void ni_mg_clockgating_enable(struct radeon_device *rdev,
958 btc_program_mgcg_hw_sequence(rdev, ps, count);
961 static void ni_ls_clockgating_default(struct radeon_device *rdev)
969 btc_program_mgcg_hw_sequence(rdev, ps, count);
972 static void ni_ls_clockgating_enable(struct radeon_device *rdev,
986 btc_program_mgcg_hw_sequence(rdev, ps, count);
990 static int ni_patch_single_dependency_table_based_on_leakage(struct radeon_device *rdev,
993 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
1008 static int ni_patch_dependency_tables_based_on_leakage(struct radeon_device *rdev)
1012 ret = ni_patch_single_dependency_table_based_on_leakage(rdev,
1013 &rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk);
1015 ret = ni_patch_single_dependency_table_based_on_leakage(rdev,
1016 &rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk);
1020 static void ni_stop_dpm(struct radeon_device *rdev)
1026 static int ni_notify_hw_of_power_source(struct radeon_device *rdev,
1030 return (rv770_send_msg_to_smc(rdev, PPSMC_MSG_RunningOnAC) == PPSMC_Result_OK) ?
1037 static PPSMC_Result ni_send_msg_to_smc_with_parameter(struct radeon_device *rdev,
1041 return rv770_send_msg_to_smc(rdev, msg);
1044 static int ni_restrict_performance_levels_before_switch(struct radeon_device *rdev)
1046 if (rv770_send_msg_to_smc(rdev, PPSMC_MSG_NoForcedLevel) != PPSMC_Result_OK)
1049 return (ni_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetEnabledLevels, 1) == PPSMC_Result_OK) ?
1053 int ni_dpm_force_performance_level(struct radeon_device *rdev,
1057 if (ni_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetEnabledLevels, 0) != PPSMC_Result_OK)
1060 if (ni_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetForcedLevels, 1) != PPSMC_Result_OK)
1063 if (ni_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetForcedLevels, 0) != PPSMC_Result_OK)
1066 if (ni_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetEnabledLevels, 1) != PPSMC_Result_OK)
1069 if (ni_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetForcedLevels, 0) != PPSMC_Result_OK)
1072 if (ni_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetEnabledLevels, 0) != PPSMC_Result_OK)
1076 rdev->pm.dpm.forced_level = level;
1081 static void ni_stop_smc(struct radeon_device *rdev)
1086 for (i = 0; i < rdev->usec_timeout; i++) {
1095 r7xx_stop_smc(rdev);
1098 static int ni_process_firmware_header(struct radeon_device *rdev)
1100 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
1101 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
1102 struct ni_power_info *ni_pi = ni_get_pi(rdev);
1106 ret = rv770_read_smc_sram_dword(rdev,
1116 ret = rv770_read_smc_sram_dword(rdev,
1126 ret = rv770_read_smc_sram_dword(rdev,
1136 ret = rv770_read_smc_sram_dword(rdev,
1146 ret = rv770_read_smc_sram_dword(rdev,
1156 ret = rv770_read_smc_sram_dword(rdev,
1166 ret = rv770_read_smc_sram_dword(rdev,
1180 static void ni_read_clock_registers(struct radeon_device *rdev)
1182 struct ni_power_info *ni_pi = ni_get_pi(rdev);
1201 static int ni_enter_ulp_state(struct radeon_device *rdev)
1203 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
1221 static void ni_program_response_times(struct radeon_device *rdev)
1227 rv770_write_smc_soft_register(rdev, NI_SMC_SOFT_REGISTER_mvdd_chg_time, 1);
1229 voltage_response_time = (u32)rdev->pm.dpm.voltage_response_time;
1230 backbias_response_time = (u32)rdev->pm.dpm.backbias_response_time;
1241 reference_clock = radeon_get_xclk(rdev);
1250 rv770_write_smc_soft_register(rdev, NI_SMC_SOFT_REGISTER_delay_vreg, vddc_dly);
1251 rv770_write_smc_soft_register(rdev, NI_SMC_SOFT_REGISTER_delay_bbias, bb_dly);
1252 rv770_write_smc_soft_register(rdev, NI_SMC_SOFT_REGISTER_delay_acpi, acpi_dly);
1253 rv770_write_smc_soft_register(rdev, NI_SMC_SOFT_REGISTER_mclk_chg_timeout, vbi_dly);
1254 rv770_write_smc_soft_register(rdev, NI_SMC_SOFT_REGISTER_mc_block_delay, 0xAA);
1255 rv770_write_smc_soft_register(rdev, NI_SMC_SOFT_REGISTER_mclk_switch_lim, mclk_switch_limit);
1258 static void ni_populate_smc_voltage_table(struct radeon_device *rdev,
1270 static void ni_populate_smc_voltage_tables(struct radeon_device *rdev,
1273 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
1274 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
1278 ni_populate_smc_voltage_table(rdev, &eg_pi->vddc_voltage_table, table);
1292 ni_populate_smc_voltage_table(rdev, &eg_pi->vddci_voltage_table, table);
1300 static int ni_populate_voltage_value(struct radeon_device *rdev,
1321 static void ni_populate_mvdd_value(struct radeon_device *rdev,
1325 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
1326 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
1343 static int ni_get_std_voltage_value(struct radeon_device *rdev,
1347 if (rdev->pm.dpm.dyn_state.cac_leakage_table.entries &&
1348 ((u32)voltage->index < rdev->pm.dpm.dyn_state.cac_leakage_table.count))
1349 *std_voltage = rdev->pm.dpm.dyn_state.cac_leakage_table.entries[voltage->index].vddc;
1356 static void ni_populate_std_voltage_value(struct radeon_device *rdev,
1364 static u32 ni_get_smc_power_scaling_factor(struct radeon_device *rdev)
1367 u32 xclk = radeon_get_xclk(rdev);
1381 static u32 ni_calculate_power_boost_limit(struct radeon_device *rdev,
1386 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
1387 struct ni_power_info *ni_pi = ni_get_pi(rdev);
1401 ret = ni_populate_voltage_value(rdev, &eg_pi->vddc_voltage_table,
1407 ret = ni_get_std_voltage_value(rdev, &vddc, &std_vddc_med);
1411 ret = ni_populate_voltage_value(rdev, &eg_pi->vddc_voltage_table,
1417 ret = ni_get_std_voltage_value(rdev, &vddc, &std_vddc_high);
1433 static int ni_calculate_adjusted_tdp_limits(struct radeon_device *rdev,
1439 if (tdp_adjustment > (u32)rdev->pm.dpm.tdp_od_limit)
1443 *tdp_limit = ((100 + tdp_adjustment) * rdev->pm.dpm.tdp_limit) / 100;
1444 *near_tdp_limit = rdev->pm.dpm.near_tdp_limit + (*tdp_limit - rdev->pm.dpm.tdp_limit);
1446 *tdp_limit = ((100 - tdp_adjustment) * rdev->pm.dpm.tdp_limit) / 100;
1447 *near_tdp_limit = rdev->pm.dpm.near_tdp_limit - (rdev->pm.dpm.tdp_limit - *tdp_limit);
1453 static int ni_populate_smc_tdp_limits(struct radeon_device *rdev,
1456 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
1457 struct ni_power_info *ni_pi = ni_get_pi(rdev);
1461 u32 scaling_factor = ni_get_smc_power_scaling_factor(rdev);
1472 ret = ni_calculate_adjusted_tdp_limits(rdev,
1474 rdev->pm.dpm.tdp_adjustment,
1480 power_boost_limit = ni_calculate_power_boost_limit(rdev, radeon_state,
1493 ret = rv770_copy_bytes_to_smc(rdev,
1505 int ni_copy_and_switch_arb_sets(struct radeon_device *rdev,
1570 static int ni_init_arb_table_index(struct radeon_device *rdev)
1572 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
1573 struct ni_power_info *ni_pi = ni_get_pi(rdev);
1577 ret = rv770_read_smc_sram_dword(rdev, ni_pi->arb_table_start,
1585 return rv770_write_smc_sram_dword(rdev, ni_pi->arb_table_start,
1589 static int ni_initial_switch_from_arb_f0_to_f1(struct radeon_device *rdev)
1591 return ni_copy_and_switch_arb_sets(rdev, MC_CG_ARB_FREQ_F0, MC_CG_ARB_FREQ_F1);
1594 static int ni_force_switch_to_arb_f0(struct radeon_device *rdev)
1596 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
1597 struct ni_power_info *ni_pi = ni_get_pi(rdev);
1601 ret = rv770_read_smc_sram_dword(rdev, ni_pi->arb_table_start,
1611 return ni_copy_and_switch_arb_sets(rdev, tmp, MC_CG_ARB_FREQ_F0);
1614 static int ni_populate_memory_timing_parameters(struct radeon_device *rdev,
1622 (u8)rv770_calculate_memory_refresh_rate(rdev, pl->sclk);
1625 radeon_atom_set_engine_dram_timings(rdev, pl->sclk, pl->mclk);
1636 static int ni_do_program_memory_timing_parameters(struct radeon_device *rdev,
1640 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
1641 struct ni_power_info *ni_pi = ni_get_pi(rdev);
1647 ret = ni_populate_memory_timing_parameters(rdev, &state->performance_levels[i], &arb_regs);
1651 ret = rv770_copy_bytes_to_smc(rdev,
1664 static int ni_program_memory_timing_parameters(struct radeon_device *rdev,
1667 return ni_do_program_memory_timing_parameters(rdev, radeon_new_state,
1671 static void ni_populate_initial_mvdd_value(struct radeon_device *rdev,
1674 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
1680 static int ni_populate_smc_initial_state(struct radeon_device *rdev,
1685 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
1686 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
1687 struct ni_power_info *ni_pi = ni_get_pi(rdev);
1729 ret = ni_populate_voltage_value(rdev, &eg_pi->vddc_voltage_table,
1735 ret = ni_get_std_voltage_value(rdev,
1739 ni_populate_std_voltage_value(rdev, std_vddc,
1745 ni_populate_voltage_value(rdev,
1750 ni_populate_initial_mvdd_value(rdev, &table->initialState.levels[0].mvdd);
1764 cypress_get_strobe_mode_settings(rdev,
1791 static int ni_populate_smc_acpi_state(struct radeon_device *rdev,
1794 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
1795 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
1796 struct ni_power_info *ni_pi = ni_get_pi(rdev);
1815 ret = ni_populate_voltage_value(rdev,
1821 ret = ni_get_std_voltage_value(rdev,
1824 ni_populate_std_voltage_value(rdev, std_vddc,
1838 ret = ni_populate_voltage_value(rdev,
1845 ret = ni_get_std_voltage_value(rdev,
1849 ni_populate_std_voltage_value(rdev, std_vddc,
1858 ni_populate_voltage_value(rdev,
1920 ni_populate_mvdd_value(rdev, 0, &table->ACPIState.levels[0].mvdd);
1939 static int ni_init_smc_table(struct radeon_device *rdev)
1941 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
1942 struct ni_power_info *ni_pi = ni_get_pi(rdev);
1944 struct radeon_ps *radeon_boot_state = rdev->pm.dpm.boot_ps;
1949 ni_populate_smc_voltage_tables(rdev, table);
1951 switch (rdev->pm.int_thermal_type) {
1964 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_HARDWAREDC)
1967 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_REGULATOR_HOT)
1970 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_STEPVDDC)
1976 ret = ni_populate_smc_initial_state(rdev, radeon_boot_state, table);
1980 ret = ni_populate_smc_acpi_state(rdev, table);
1988 ret = ni_do_program_memory_timing_parameters(rdev, radeon_boot_state,
1993 return rv770_copy_bytes_to_smc(rdev, pi->state_table_start, (u8 *)table,
1997 static int ni_calculate_sclk_params(struct radeon_device *rdev,
2001 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
2002 struct ni_power_info *ni_pi = ni_get_pi(rdev);
2011 u32 reference_clock = rdev->clock.spll.reference_freq;
2016 ret = radeon_atom_get_clock_dividers(rdev, COMPUTE_ENGINE_PLL_PARAM,
2043 if (radeon_atombios_get_asic_ss_info(rdev, &ss,
2068 static int ni_populate_sclk_value(struct radeon_device *rdev,
2075 ret = ni_calculate_sclk_params(rdev, engine_clock, &sclk_tmp);
2089 static int ni_init_smc_spll_table(struct radeon_device *rdev)
2091 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
2092 struct ni_power_info *ni_pi = ni_get_pi(rdev);
2111 ret = ni_calculate_sclk_params(rdev, sclk, &sclk_params);
2151 ret = rv770_copy_bytes_to_smc(rdev, ni_pi->spll_table_start, (u8 *)spll_table,
2159 static int ni_populate_mclk_value(struct radeon_device *rdev,
2166 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
2167 struct ni_power_info *ni_pi = ni_get_pi(rdev);
2182 ret = radeon_atom_get_clock_dividers(rdev, COMPUTE_MEMORY_PLL_PARAM,
2194 ibias = cypress_map_clkf_to_ibias(rdev, dividers.whole_fb_div);
2239 if (radeon_atombios_get_asic_ss_info(rdev, &ss,
2241 u32 reference_clock = rdev->clock.mpll.reference_freq;
2297 static void ni_populate_smc_sp(struct radeon_device *rdev,
2302 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
2312 static int ni_convert_power_level_to_smc(struct radeon_device *rdev,
2316 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
2317 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
2318 struct ni_power_info *ni_pi = ni_get_pi(rdev);
2327 ret = ni_populate_sclk_value(rdev, pl->sclk, &level->sclk);
2345 level->strobeMode = cypress_get_strobe_mode_settings(rdev, pl->mclk);
2348 if (cypress_get_mclk_frequency_ratio(rdev, pl->mclk, true) >=
2359 ret = ni_populate_mclk_value(rdev, pl->sclk, pl->mclk,
2364 ret = ni_populate_mclk_value(rdev, pl->sclk, pl->mclk, &level->mclk, 1, 1);
2369 ret = ni_populate_voltage_value(rdev, &eg_pi->vddc_voltage_table,
2374 ret = ni_get_std_voltage_value(rdev, &level->vddc, &std_vddc);
2378 ni_populate_std_voltage_value(rdev, std_vddc,
2382 ret = ni_populate_voltage_value(rdev, &eg_pi->vddci_voltage_table,
2388 ni_populate_mvdd_value(rdev, pl->mclk, &level->mvdd);
2393 static int ni_populate_smc_t(struct radeon_device *rdev,
2397 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
2398 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
2453 static int ni_populate_power_containment_values(struct radeon_device *rdev,
2457 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
2458 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
2459 struct ni_power_info *ni_pi = ni_get_pi(rdev);
2479 ret = ni_calculate_adjusted_tdp_limits(rdev,
2481 rdev->pm.dpm.tdp_adjustment,
2487 power_boost_limit = ni_calculate_power_boost_limit(rdev, radeon_state, near_tdp_limit);
2489 ret = rv770_write_smc_sram_dword(rdev,
2493 ni_scale_power_for_smc(power_boost_limit, ni_get_smc_power_scaling_factor(rdev)),
2539 static int ni_populate_sq_ramping_values(struct radeon_device *rdev,
2543 struct ni_power_info *ni_pi = ni_get_pi(rdev);
2556 if (rdev->pm.dpm.sq_ramping_threshold == 0)
2578 if ((state->performance_levels[i].sclk >= rdev->pm.dpm.sq_ramping_threshold) &&
2597 static int ni_enable_power_containment(struct radeon_device *rdev,
2601 struct ni_power_info *ni_pi = ni_get_pi(rdev);
2608 smc_result = rv770_send_msg_to_smc(rdev, PPSMC_TDPClampingActive);
2617 smc_result = rv770_send_msg_to_smc(rdev, PPSMC_TDPClampingInactive);
2627 static int ni_convert_power_state_to_smc(struct radeon_device *rdev,
2631 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
2632 struct ni_power_info *ni_pi = ni_get_pi(rdev);
2646 ret = ni_convert_power_level_to_smc(rdev, &state->performance_levels[i],
2670 rv770_write_smc_soft_register(rdev, NI_SMC_SOFT_REGISTER_watermark_threshold,
2673 ni_populate_smc_sp(rdev, radeon_state, smc_state);
2675 ret = ni_populate_power_containment_values(rdev, radeon_state, smc_state);
2679 ret = ni_populate_sq_ramping_values(rdev, radeon_state, smc_state);
2683 return ni_populate_smc_t(rdev, radeon_state, smc_state);
2686 static int ni_upload_sw_state(struct radeon_device *rdev,
2689 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
2701 ret = ni_convert_power_state_to_smc(rdev, radeon_new_state, smc_state);
2705 ret = rv770_copy_bytes_to_smc(rdev, address, (u8 *)smc_state, state_size, pi->sram_end);
2713 static int ni_set_mc_special_registers(struct radeon_device *rdev,
2716 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
2873 static int ni_initialize_mc_reg_table(struct radeon_device *rdev)
2875 struct ni_power_info *ni_pi = ni_get_pi(rdev);
2879 u8 module_index = rv770_get_memory_module_index(rdev);
2899 ret = radeon_atom_init_mc_reg_table(rdev, module_index, table);
2911 ret = ni_set_mc_special_registers(rdev, ni_table);
2924 static void ni_populate_mc_reg_addresses(struct radeon_device *rdev,
2927 struct ni_power_info *ni_pi = ni_get_pi(rdev);
2959 static void ni_convert_mc_reg_table_entry_to_smc(struct radeon_device *rdev,
2963 struct ni_power_info *ni_pi = ni_get_pi(rdev);
2980 static void ni_convert_mc_reg_table_to_smc(struct radeon_device *rdev,
2988 ni_convert_mc_reg_table_entry_to_smc(rdev,
2994 static int ni_populate_mc_reg_table(struct radeon_device *rdev,
2997 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
2998 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
2999 struct ni_power_info *ni_pi = ni_get_pi(rdev);
3005 rv770_write_smc_soft_register(rdev, NI_SMC_SOFT_REGISTER_seq_index, 1);
3007 ni_populate_mc_reg_addresses(rdev, mc_reg_table);
3009 ni_convert_mc_reg_table_entry_to_smc(rdev, &boot_state->performance_levels[0],
3017 ni_convert_mc_reg_table_to_smc(rdev, radeon_boot_state, mc_reg_table);
3019 return rv770_copy_bytes_to_smc(rdev, eg_pi->mc_reg_table_start,
3025 static int ni_upload_mc_reg_table(struct radeon_device *rdev,
3028 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
3029 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
3030 struct ni_power_info *ni_pi = ni_get_pi(rdev);
3037 ni_convert_mc_reg_table_to_smc(rdev, radeon_new_state, mc_reg_table);
3042 return rv770_copy_bytes_to_smc(rdev, address,
3048 static int ni_init_driver_calculated_leakage_table(struct radeon_device *rdev,
3051 struct ni_power_info *ni_pi = ni_get_pi(rdev);
3052 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
3064 scaling_factor = ni_get_smc_power_scaling_factor(rdev);
3073 ni_calculate_leakage_for_v_and_t(rdev,
3095 static int ni_init_simplified_leakage_table(struct radeon_device *rdev,
3098 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
3100 &rdev->pm.dpm.dyn_state.cac_leakage_table;
3120 scaling_factor = ni_get_smc_power_scaling_factor(rdev);
3141 static int ni_initialize_smc_cac_tables(struct radeon_device *rdev)
3143 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
3144 struct ni_power_info *ni_pi = ni_get_pi(rdev);
3167 ni_pi->cac_data.i_leakage = rdev->pm.dpm.cac_leakage;
3179 ret = ni_init_driver_calculated_leakage_table(rdev, cac_tables);
3181 ret = ni_init_simplified_leakage_table(rdev, cac_tables);
3196 ret = rv770_copy_bytes_to_smc(rdev, ni_pi->cac_table_start, (u8 *)cac_tables,
3210 static int ni_initialize_hardware_cac_manager(struct radeon_device *rdev)
3212 struct ni_power_info *ni_pi = ni_get_pi(rdev);
3379 static int ni_enable_smc_cac(struct radeon_device *rdev,
3383 struct ni_power_info *ni_pi = ni_get_pi(rdev);
3390 smc_result = rv770_send_msg_to_smc(rdev, PPSMC_MSG_CollectCAC_PowerCorreln);
3393 smc_result = rv770_send_msg_to_smc(rdev, PPSMC_CACLongTermAvgEnable);
3398 smc_result = rv770_send_msg_to_smc(rdev, PPSMC_MSG_EnableCac);
3405 smc_result = rv770_send_msg_to_smc(rdev, PPSMC_MSG_DisableCac);
3410 smc_result = rv770_send_msg_to_smc(rdev, PPSMC_CACLongTermAvgDisable);
3420 static int ni_pcie_performance_request(struct radeon_device *rdev,
3424 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
3429 radeon_acpi_pcie_notify_device_ready(rdev);
3431 return radeon_acpi_pcie_performance_request(rdev, perf_req, advertise);
3435 return radeon_acpi_pcie_performance_request(rdev, perf_req, advertise);
3441 static int ni_advertise_gen2_capability(struct radeon_device *rdev)
3443 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
3455 ni_pcie_performance_request(rdev, PCIE_PERF_REQ_PECI_GEN2, true);
3460 static void ni_enable_bif_dynamic_pcie_gen2(struct radeon_device *rdev,
3463 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
3499 static void ni_enable_dynamic_pcie_gen2(struct radeon_device *rdev,
3502 ni_enable_bif_dynamic_pcie_gen2(rdev, enable);
3510 void ni_set_uvd_clock_before_set_eng_clock(struct radeon_device *rdev,
3525 radeon_set_uvd_clocks(rdev, new_ps->vclk, new_ps->dclk);
3528 void ni_set_uvd_clock_after_set_eng_clock(struct radeon_device *rdev,
3543 radeon_set_uvd_clocks(rdev, new_ps->vclk, new_ps->dclk);
3546 void ni_dpm_setup_asic(struct radeon_device *rdev)
3548 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
3551 r = ni_mc_load_microcode(rdev);
3554 ni_read_clock_registers(rdev);
3555 btc_read_arb_registers(rdev);
3556 rv770_get_memory_type(rdev);
3558 ni_advertise_gen2_capability(rdev);
3559 rv770_get_pcie_gen2_status(rdev);
3560 rv770_enable_acpi_pm(rdev);
3563 void ni_update_current_ps(struct radeon_device *rdev,
3567 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
3568 struct ni_power_info *ni_pi = ni_get_pi(rdev);
3575 void ni_update_requested_ps(struct radeon_device *rdev,
3579 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
3580 struct ni_power_info *ni_pi = ni_get_pi(rdev);
3587 int ni_dpm_enable(struct radeon_device *rdev)
3589 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
3590 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
3591 struct radeon_ps *boot_ps = rdev->pm.dpm.boot_ps;
3595 ni_cg_clockgating_default(rdev);
3596 if (btc_dpm_enabled(rdev))
3599 ni_mg_clockgating_default(rdev);
3601 ni_ls_clockgating_default(rdev);
3603 rv770_enable_voltage_control(rdev, true);
3604 ret = cypress_construct_voltage_tables(rdev);
3611 ret = ni_initialize_mc_reg_table(rdev);
3616 cypress_enable_spread_spectrum(rdev, true);
3618 rv770_enable_thermal_protection(rdev, true);
3619 rv770_setup_bsp(rdev);
3620 rv770_program_git(rdev);
3621 rv770_program_tp(rdev);
3622 rv770_program_tpp(rdev);
3623 rv770_program_sstp(rdev);
3624 cypress_enable_display_gap(rdev);
3625 rv770_program_vc(rdev);
3627 ni_enable_dynamic_pcie_gen2(rdev, true);
3628 ret = rv770_upload_firmware(rdev);
3633 ret = ni_process_firmware_header(rdev);
3638 ret = ni_initial_switch_from_arb_f0_to_f1(rdev);
3643 ret = ni_init_smc_table(rdev);
3648 ret = ni_init_smc_spll_table(rdev);
3653 ret = ni_init_arb_table_index(rdev);
3659 ret = ni_populate_mc_reg_table(rdev, boot_ps);
3665 ret = ni_initialize_smc_cac_tables(rdev);
3670 ret = ni_initialize_hardware_cac_manager(rdev);
3675 ret = ni_populate_smc_tdp_limits(rdev, boot_ps);
3680 ni_program_response_times(rdev);
3681 r7xx_start_smc(rdev);
3682 ret = cypress_notify_smc_display_change(rdev, false);
3687 cypress_enable_sclk_control(rdev, true);
3689 cypress_enable_mclk_control(rdev, true);
3690 cypress_start_dpm(rdev);
3692 ni_gfx_clockgating_enable(rdev, true);
3694 ni_mg_clockgating_enable(rdev, true);
3696 ni_ls_clockgating_enable(rdev, true);
3698 rv770_enable_auto_throttle_source(rdev, RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL, true);
3700 ni_update_current_ps(rdev, boot_ps);
3705 void ni_dpm_disable(struct radeon_device *rdev)
3707 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
3708 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
3709 struct radeon_ps *boot_ps = rdev->pm.dpm.boot_ps;
3711 if (!btc_dpm_enabled(rdev))
3713 rv770_clear_vc(rdev);
3715 rv770_enable_thermal_protection(rdev, false);
3716 ni_enable_power_containment(rdev, boot_ps, false);
3717 ni_enable_smc_cac(rdev, boot_ps, false);
3718 cypress_enable_spread_spectrum(rdev, false);
3719 rv770_enable_auto_throttle_source(rdev, RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL, false);
3721 ni_enable_dynamic_pcie_gen2(rdev, false);
3723 if (rdev->irq.installed &&
3724 r600_is_internal_thermal_sensor(rdev->pm.int_thermal_type)) {
3725 rdev->irq.dpm_thermal = false;
3726 radeon_irq_set(rdev);
3730 ni_gfx_clockgating_enable(rdev, false);
3732 ni_mg_clockgating_enable(rdev, false);
3734 ni_ls_clockgating_enable(rdev, false);
3735 ni_stop_dpm(rdev);
3736 btc_reset_to_default(rdev);
3737 ni_stop_smc(rdev);
3738 ni_force_switch_to_arb_f0(rdev);
3740 ni_update_current_ps(rdev, boot_ps);
3743 static int ni_power_control_set_level(struct radeon_device *rdev)
3745 struct radeon_ps *new_ps = rdev->pm.dpm.requested_ps;
3748 ret = ni_restrict_performance_levels_before_switch(rdev);
3751 ret = rv770_halt_smc(rdev);
3754 ret = ni_populate_smc_tdp_limits(rdev, new_ps);
3757 ret = rv770_resume_smc(rdev);
3760 ret = rv770_set_sw_state(rdev);
3767 int ni_dpm_pre_set_power_state(struct radeon_device *rdev)
3769 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
3770 struct radeon_ps requested_ps = *rdev->pm.dpm.requested_ps;
3773 ni_update_requested_ps(rdev, new_ps);
3775 ni_apply_state_adjust_rules(rdev, &eg_pi->requested_rps);
3780 int ni_dpm_set_power_state(struct radeon_device *rdev)
3782 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
3787 ret = ni_restrict_performance_levels_before_switch(rdev);
3792 ni_set_uvd_clock_before_set_eng_clock(rdev, new_ps, old_ps);
3793 ret = ni_enable_power_containment(rdev, new_ps, false);
3798 ret = ni_enable_smc_cac(rdev, new_ps, false);
3803 ret = rv770_halt_smc(rdev);
3809 btc_notify_uvd_to_smc(rdev, new_ps);
3810 ret = ni_upload_sw_state(rdev, new_ps);
3816 ret = ni_upload_mc_reg_table(rdev, new_ps);
3822 ret = ni_program_memory_timing_parameters(rdev, new_ps);
3827 ret = rv770_resume_smc(rdev);
3832 ret = rv770_set_sw_state(rdev);
3837 ni_set_uvd_clock_after_set_eng_clock(rdev, new_ps, old_ps);
3838 ret = ni_enable_smc_cac(rdev, new_ps, true);
3843 ret = ni_enable_power_containment(rdev, new_ps, true);
3850 ret = ni_power_control_set_level(rdev);
3859 void ni_dpm_post_set_power_state(struct radeon_device *rdev)
3861 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
3864 ni_update_current_ps(rdev, new_ps);
3868 void ni_dpm_reset_asic(struct radeon_device *rdev)
3870 ni_restrict_performance_levels_before_switch(rdev);
3871 rv770_set_boot_state(rdev);
3896 static void ni_parse_pplib_non_clock_info(struct radeon_device *rdev,
3917 rdev->pm.dpm.boot_ps = rps;
3919 rdev->pm.dpm.uvd_ps = rps;
3922 static void ni_parse_pplib_clock_info(struct radeon_device *rdev,
3926 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
3927 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
3971 radeon_atombios_get_default_voltages(rdev, &vddc, &vddci, &mvdd);
3972 pl->mclk = rdev->clock.default_mclk;
3973 pl->sclk = rdev->clock.default_sclk;
3980 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.sclk = pl->sclk;
3981 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.mclk = pl->mclk;
3982 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.vddc = pl->vddc;
3983 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.vddci = pl->vddci;
3987 static int ni_parse_power_table(struct radeon_device *rdev)
3989 struct radeon_mode_info *mode_info = &rdev->mode_info;
4005 rdev->pm.dpm.ps = kcalloc(power_info->pplib.ucNumStates,
4008 if (!rdev->pm.dpm.ps)
4025 kfree(rdev->pm.dpm.ps);
4028 rdev->pm.dpm.ps[i].ps_priv = ps;
4029 ni_parse_pplib_non_clock_info(rdev, &rdev->pm.dpm.ps[i],
4038 ni_parse_pplib_clock_info(rdev,
4039 &rdev->pm.dpm.ps[i], j,
4044 rdev->pm.dpm.num_ps = power_info->pplib.ucNumStates;
4048 int ni_dpm_init(struct radeon_device *rdev)
4059 rdev->pm.dpm.priv = ni_pi;
4063 rv770_get_max_vddc(rdev);
4071 ret = r600_get_platform_caps(rdev);
4075 ret = ni_parse_power_table(rdev);
4078 ret = r600_parse_extended_power_table(rdev);
4082 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries =
4086 if (!rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries) {
4087 r600_free_extended_power_table(rdev);
4090 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.count = 4;
4091 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[0].clk = 0;
4092 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[0].v = 0;
4093 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[1].clk = 36000;
4094 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[1].v = 720;
4095 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[2].clk = 54000;
4096 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[2].v = 810;
4097 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[3].clk = 72000;
4098 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[3].v = 900;
4100 ni_patch_dependency_tables_based_on_leakage(rdev);
4102 if (rdev->pm.dpm.voltage_response_time == 0)
4103 rdev->pm.dpm.voltage_response_time = R600_VOLTAGERESPONSETIME_DFLT;
4104 if (rdev->pm.dpm.backbias_response_time == 0)
4105 rdev->pm.dpm.backbias_response_time = R600_BACKBIASRESPONSETIME_DFLT;
4107 ret = radeon_atom_get_clock_dividers(rdev, COMPUTE_ENGINE_PLL_PARAM,
4131 if (rdev->pdev->device == 0x6707) {
4143 radeon_atom_is_voltage_gpio(rdev, SET_VOLTAGE_TYPE_ASIC_VDDC, 0);
4146 radeon_atom_is_voltage_gpio(rdev, SET_VOLTAGE_TYPE_ASIC_MVDDC, 0);
4149 radeon_atom_is_voltage_gpio(rdev, SET_VOLTAGE_TYPE_ASIC_VDDCI, 0);
4151 rv770_get_engine_memory_ss(rdev);
4168 if (rdev->pm.int_thermal_type != THERMAL_TYPE_NONE)
4186 radeon_acpi_is_pcie_performance_request_supported(rdev);
4199 rdev->pm.dpm.dyn_state.mclk_sclk_ratio = 3;
4200 rdev->pm.dpm.dyn_state.vddc_vddci_delta = 200;
4201 rdev->pm.dpm.dyn_state.min_vddc_for_pcie_gen2 = 900;
4202 rdev->pm.dpm.dyn_state.valid_sclk_values.count = ARRAY_SIZE(btc_valid_sclk);
4203 rdev->pm.dpm.dyn_state.valid_sclk_values.values = btc_valid_sclk;
4204 rdev->pm.dpm.dyn_state.valid_mclk_values.count = 0;
4205 rdev->pm.dpm.dyn_state.valid_mclk_values.values = NULL;
4206 rdev->pm.dpm.dyn_state.sclk_mclk_delta = 12500;
4213 switch (rdev->pdev->device) {
4263 if ((rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc.sclk == 0) ||
4264 (rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc.mclk == 0))
4265 rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc =
4266 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac;
4271 void ni_dpm_fini(struct radeon_device *rdev)
4275 for (i = 0; i < rdev->pm.dpm.num_ps; i++) {
4276 kfree(rdev->pm.dpm.ps[i].ps_priv);
4278 kfree(rdev->pm.dpm.ps);
4279 kfree(rdev->pm.dpm.priv);
4280 kfree(rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries);
4281 r600_free_extended_power_table(rdev);
4284 void ni_dpm_print_power_state(struct radeon_device *rdev,
4296 if (rdev->family >= CHIP_TAHITI)
4303 r600_dpm_print_ps_status(rdev, rps);
4306 void ni_dpm_debugfs_print_current_performance_level(struct radeon_device *rdev,
4309 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
4327 u32 ni_dpm_get_current_sclk(struct radeon_device *rdev)
4329 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
4345 u32 ni_dpm_get_current_mclk(struct radeon_device *rdev)
4347 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
4363 u32 ni_dpm_get_sclk(struct radeon_device *rdev, bool low)
4365 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
4374 u32 ni_dpm_get_mclk(struct radeon_device *rdev, bool low)
4376 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);