Lines Matching refs:ib
118 * @ib: IB object to schedule
123 struct radeon_ib *ib)
125 struct radeon_ring *ring = &rdev->ring[ib->ring];
126 unsigned vm_id = ib->vm ? ib->vm->ids[ib->ring].id : 0;
145 radeon_ring_write(ring, (ib->gpu_addr & 0xFFFFFFE0));
146 radeon_ring_write(ring, (ib->length_dw << 12) | (upper_32_bits(ib->gpu_addr) & 0xFF));
308 * @ib: indirect buffer to fill with commands
316 struct radeon_ib *ib,
327 ib->ptr[ib->length_dw++] = DMA_PACKET(DMA_PACKET_COPY,
329 ib->ptr[ib->length_dw++] = lower_32_bits(pe);
330 ib->ptr[ib->length_dw++] = lower_32_bits(src);
331 ib->ptr[ib->length_dw++] = upper_32_bits(pe) & 0xff;
332 ib->ptr[ib->length_dw++] = upper_32_bits(src) & 0xff;
344 * @ib: indirect buffer to fill with commands
354 struct radeon_ib *ib,
368 ib->ptr[ib->length_dw++] = DMA_PACKET(DMA_PACKET_WRITE,
370 ib->ptr[ib->length_dw++] = pe;
371 ib->ptr[ib->length_dw++] = upper_32_bits(pe) & 0xff;
382 ib->ptr[ib->length_dw++] = value;
383 ib->ptr[ib->length_dw++] = upper_32_bits(value);
392 * @ib: indirect buffer to fill with commands
402 struct radeon_ib *ib,
421 ib->ptr[ib->length_dw++] = DMA_PTE_PDE_PACKET(ndw);
422 ib->ptr[ib->length_dw++] = pe; /* dst addr */
423 ib->ptr[ib->length_dw++] = upper_32_bits(pe) & 0xff;
424 ib->ptr[ib->length_dw++] = flags; /* mask */
425 ib->ptr[ib->length_dw++] = 0;
426 ib->ptr[ib->length_dw++] = value; /* value */
427 ib->ptr[ib->length_dw++] = upper_32_bits(value);
428 ib->ptr[ib->length_dw++] = incr; /* increment size */
429 ib->ptr[ib->length_dw++] = 0;
440 * @ib: indirect buffer to fill with padding
443 void cayman_dma_vm_pad_ib(struct radeon_ib *ib)
445 while (ib->length_dw & 0x7)
446 ib->ptr[ib->length_dw++] = DMA_PACKET(DMA_PACKET_NOP, 0, 0, 0);