Lines Matching defs:tmp
900 u32 tmp;
1022 tmp = (mc_arb_ramcfg & NOOFCOLS_MASK) >> NOOFCOLS_SHIFT;
1023 rdev->config.cayman.mem_row_size_in_kb = (4 * (1 << (8 + tmp))) / 1024;
1031 tmp = (gb_addr_config & NUM_PIPES_MASK) >> NUM_PIPES_SHIFT;
1032 rdev->config.cayman.num_tile_pipes = (1 << tmp);
1033 tmp = (gb_addr_config & PIPE_INTERLEAVE_SIZE_MASK) >> PIPE_INTERLEAVE_SIZE_SHIFT;
1034 rdev->config.cayman.mem_max_burst_length_bytes = (tmp + 1) * 256;
1035 tmp = (gb_addr_config & NUM_SHADER_ENGINES_MASK) >> NUM_SHADER_ENGINES_SHIFT;
1036 rdev->config.cayman.num_shader_engines = tmp + 1;
1037 tmp = (gb_addr_config & NUM_GPUS_MASK) >> NUM_GPUS_SHIFT;
1038 rdev->config.cayman.num_gpus = tmp + 1;
1039 tmp = (gb_addr_config & MULTI_GPU_TILE_SIZE_MASK) >> MULTI_GPU_TILE_SIZE_SHIFT;
1040 rdev->config.cayman.multi_gpu_tile_size = 1 << tmp;
1041 tmp = (gb_addr_config & ROW_SIZE_MASK) >> ROW_SIZE_SHIFT;
1042 rdev->config.cayman.mem_row_size_in_kb = 1 << tmp;
1091 tmp = 0;
1098 tmp <<= 4;
1099 tmp |= rb_disable_bitmap;
1102 disabled_rb_mask = tmp;
1103 tmp = 0;
1105 tmp |= (1 << i);
1107 if ((disabled_rb_mask & tmp) == tmp) {
1119 tmp <<= 16;
1120 tmp |= simd_disable_bitmap;
1122 rdev->config.cayman.active_simds = hweight32(~tmp);
1142 tmp = 0x00000000;
1145 tmp = 0x11111111;
1148 tmp = gb_addr_config & NUM_PIPES_MASK;
1149 tmp = r6xx_remap_render_backend(rdev, tmp,
1154 rdev->config.cayman.backend_map = tmp;
1155 WREG32(GB_BACKEND_MAP, tmp);
1240 tmp = RREG32(HDP_MISC_CNTL);
1241 tmp |= HDP_FLUSH_INVALIDATE_CACHE;
1242 WREG32(HDP_MISC_CNTL, tmp);
1253 tmp = RREG32_CG(CG_CGTT_LOCAL_0);
1254 tmp &= ~0x00380000;
1255 WREG32_CG(CG_CGTT_LOCAL_0, tmp);
1256 tmp = RREG32_CG(CG_CGTT_LOCAL_1);
1257 tmp &= ~0x0e000000;
1258 WREG32_CG(CG_CGTT_LOCAL_1, tmp);
1749 u32 tmp;
1752 tmp = RREG32(GRBM_STATUS);
1753 if (tmp & (PA_BUSY | SC_BUSY |
1761 if (tmp & (CF_RQ_PENDING | PF_RQ_PENDING |
1765 if (tmp & GRBM_EE_BUSY)
1769 tmp = RREG32(DMA_STATUS_REG + DMA0_REGISTER_OFFSET);
1770 if (!(tmp & DMA_IDLE))
1774 tmp = RREG32(DMA_STATUS_REG + DMA1_REGISTER_OFFSET);
1775 if (!(tmp & DMA_IDLE))
1779 tmp = RREG32(SRBM_STATUS2);
1780 if (tmp & DMA_BUSY)
1783 if (tmp & DMA1_BUSY)
1787 tmp = RREG32(SRBM_STATUS);
1788 if (tmp & (RLC_RQ_PENDING | RLC_BUSY))
1791 if (tmp & IH_BUSY)
1794 if (tmp & SEM_BUSY)
1797 if (tmp & GRBM_RQ_PENDING)
1800 if (tmp & VMC_BUSY)
1803 if (tmp & (MCB_BUSY | MCB_NON_DISPLAY_BUSY |
1811 tmp = RREG32(VM_L2_STATUS);
1812 if (tmp & L2_BUSY)
1828 u32 tmp;
1850 tmp = RREG32(DMA_RB_CNTL + DMA0_REGISTER_OFFSET);
1851 tmp &= ~DMA_RB_ENABLE;
1852 WREG32(DMA_RB_CNTL + DMA0_REGISTER_OFFSET, tmp);
1857 tmp = RREG32(DMA_RB_CNTL + DMA1_REGISTER_OFFSET);
1858 tmp &= ~DMA_RB_ENABLE;
1859 WREG32(DMA_RB_CNTL + DMA1_REGISTER_OFFSET, tmp);
1920 tmp = RREG32(GRBM_SOFT_RESET);
1921 tmp |= grbm_soft_reset;
1922 dev_info(rdev->dev, "GRBM_SOFT_RESET=0x%08X\n", tmp);
1923 WREG32(GRBM_SOFT_RESET, tmp);
1924 tmp = RREG32(GRBM_SOFT_RESET);
1928 tmp &= ~grbm_soft_reset;
1929 WREG32(GRBM_SOFT_RESET, tmp);
1930 tmp = RREG32(GRBM_SOFT_RESET);
1934 tmp = RREG32(SRBM_SOFT_RESET);
1935 tmp |= srbm_soft_reset;
1936 dev_info(rdev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
1937 WREG32(SRBM_SOFT_RESET, tmp);
1938 tmp = RREG32(SRBM_SOFT_RESET);
1942 tmp &= ~srbm_soft_reset;
1943 WREG32(SRBM_SOFT_RESET, tmp);
1944 tmp = RREG32(SRBM_SOFT_RESET);
2512 u64 tmp = RREG32(FUS_MC_VM_FB_OFFSET);
2513 tmp <<= 22;
2514 rdev->vm_manager.vram_base_offset = tmp;