Lines Matching refs:pi
252 struct kv_power_info *pi = rdev->pm.dpm.priv;
254 return pi;
334 struct kv_power_info *pi = kv_get_pi(rdev);
337 if (pi->caps_sq_ramping) {
346 if (pi->caps_db_ramping) {
355 if (pi->caps_td_ramping) {
364 if (pi->caps_tcp_ramping) {
376 struct kv_power_info *pi = kv_get_pi(rdev);
379 if (pi->caps_sq_ramping ||
380 pi->caps_db_ramping ||
381 pi->caps_td_ramping ||
382 pi->caps_tcp_ramping) {
404 struct kv_power_info *pi = kv_get_pi(rdev);
406 if (pi->caps_cac) {
436 struct kv_power_info *pi = kv_get_pi(rdev);
439 if (pi->caps_cac) {
443 pi->cac_enabled = false;
445 pi->cac_enabled = true;
446 } else if (pi->cac_enabled) {
448 pi->cac_enabled = false;
457 struct kv_power_info *pi = kv_get_pi(rdev);
463 &tmp, pi->sram_end);
466 pi->dpm_table_start = tmp;
470 &tmp, pi->sram_end);
473 pi->soft_regs_start = tmp;
480 struct kv_power_info *pi = kv_get_pi(rdev);
483 pi->graphics_voltage_change_enable = 1;
486 pi->dpm_table_start +
488 &pi->graphics_voltage_change_enable,
489 sizeof(u8), pi->sram_end);
496 struct kv_power_info *pi = kv_get_pi(rdev);
499 pi->graphics_interval = 1;
502 pi->dpm_table_start +
504 &pi->graphics_interval,
505 sizeof(u8), pi->sram_end);
512 struct kv_power_info *pi = kv_get_pi(rdev);
516 pi->dpm_table_start +
518 &pi->graphics_boot_level,
519 sizeof(u8), pi->sram_end);
537 struct kv_power_info *pi = kv_get_pi(rdev);
546 pi->graphics_level[index].SclkDid = (u8)dividers.post_div;
547 pi->graphics_level[index].SclkFrequency = cpu_to_be32(sclk);
607 struct kv_power_info *pi = kv_get_pi(rdev);
609 &pi->sys_info.vid_mapping_table,
618 struct kv_power_info *pi = kv_get_pi(rdev);
620 pi->graphics_level[index].VoltageDownH = (u8)pi->voltage_drop_t;
621 pi->graphics_level[index].MinVddNb =
629 struct kv_power_info *pi = kv_get_pi(rdev);
631 pi->graphics_level[index].AT = cpu_to_be16((u16)at);
639 struct kv_power_info *pi = kv_get_pi(rdev);
641 pi->graphics_level[index].EnabledForActivity = enable ? 1 : 0;
699 struct kv_power_info *pi = kv_get_pi(rdev);
703 if (pi->caps_sclk_throttle_low_notification) {
704 low_sclk_interrupt_t = cpu_to_be32(pi->low_sclk_interrupt_t);
707 pi->dpm_table_start +
710 sizeof(u32), pi->sram_end);
717 struct kv_power_info *pi = kv_get_pi(rdev);
723 for (i = pi->graphics_dpm_level_count - 1; i > 0; i--) {
724 if (table->entries[i].clk == pi->boot_pl.sclk)
728 pi->graphics_boot_level = (u8)i;
732 &pi->sys_info.sclk_voltage_mapping_table;
737 for (i = pi->graphics_dpm_level_count - 1; i > 0; i--) {
738 if (table->entries[i].sclk_frequency == pi->boot_pl.sclk)
742 pi->graphics_boot_level = (u8)i;
750 struct kv_power_info *pi = kv_get_pi(rdev);
753 pi->graphics_therm_throttle_enable = 1;
756 pi->dpm_table_start +
758 &pi->graphics_therm_throttle_enable,
759 sizeof(u8), pi->sram_end);
766 struct kv_power_info *pi = kv_get_pi(rdev);
770 pi->dpm_table_start +
772 (u8 *)&pi->graphics_level,
774 pi->sram_end);
780 pi->dpm_table_start +
782 &pi->graphics_dpm_level_count,
783 sizeof(u8), pi->sram_end);
795 struct kv_power_info *pi = kv_get_pi(rdev);
798 if (pi->caps_enable_dfs_bypass) {
820 struct kv_power_info *pi = kv_get_pi(rdev);
830 pi->uvd_level_count = 0;
832 if (pi->high_voltage_t &&
833 (pi->high_voltage_t < table->entries[i].v))
836 pi->uvd_level[i].VclkFrequency = cpu_to_be32(table->entries[i].vclk);
837 pi->uvd_level[i].DclkFrequency = cpu_to_be32(table->entries[i].dclk);
838 pi->uvd_level[i].MinVddNb = cpu_to_be16(table->entries[i].v);
840 pi->uvd_level[i].VClkBypassCntl =
842 pi->uvd_level[i].DClkBypassCntl =
849 pi->uvd_level[i].VclkDivider = (u8)dividers.post_div;
855 pi->uvd_level[i].DclkDivider = (u8)dividers.post_div;
857 pi->uvd_level_count++;
861 pi->dpm_table_start +
863 (u8 *)&pi->uvd_level_count,
864 sizeof(u8), pi->sram_end);
868 pi->uvd_interval = 1;
871 pi->dpm_table_start +
873 &pi->uvd_interval,
874 sizeof(u8), pi->sram_end);
879 pi->dpm_table_start +
881 (u8 *)&pi->uvd_level,
883 pi->sram_end);
891 struct kv_power_info *pi = kv_get_pi(rdev);
901 pi->vce_level_count = 0;
903 if (pi->high_voltage_t &&
904 pi->high_voltage_t < table->entries[i].v)
907 pi->vce_level[i].Frequency = cpu_to_be32(table->entries[i].evclk);
908 pi->vce_level[i].MinVoltage = cpu_to_be16(table->entries[i].v);
910 pi->vce_level[i].ClkBypassCntl =
917 pi->vce_level[i].Divider = (u8)dividers.post_div;
919 pi->vce_level_count++;
923 pi->dpm_table_start +
925 (u8 *)&pi->vce_level_count,
927 pi->sram_end);
931 pi->vce_interval = 1;
934 pi->dpm_table_start +
936 (u8 *)&pi->vce_interval,
938 pi->sram_end);
943 pi->dpm_table_start +
945 (u8 *)&pi->vce_level,
947 pi->sram_end);
954 struct kv_power_info *pi = kv_get_pi(rdev);
964 pi->samu_level_count = 0;
966 if (pi->high_voltage_t &&
967 pi->high_voltage_t < table->entries[i].v)
970 pi->samu_level[i].Frequency = cpu_to_be32(table->entries[i].clk);
971 pi->samu_level[i].MinVoltage = cpu_to_be16(table->entries[i].v);
973 pi->samu_level[i].ClkBypassCntl =
980 pi->samu_level[i].Divider = (u8)dividers.post_div;
982 pi->samu_level_count++;
986 pi->dpm_table_start +
988 (u8 *)&pi->samu_level_count,
990 pi->sram_end);
994 pi->samu_interval = 1;
997 pi->dpm_table_start +
999 (u8 *)&pi->samu_interval,
1001 pi->sram_end);
1006 pi->dpm_table_start +
1008 (u8 *)&pi->samu_level,
1010 pi->sram_end);
1020 struct kv_power_info *pi = kv_get_pi(rdev);
1030 pi->acp_level_count = 0;
1032 pi->acp_level[i].Frequency = cpu_to_be32(table->entries[i].clk);
1033 pi->acp_level[i].MinVoltage = cpu_to_be16(table->entries[i].v);
1039 pi->acp_level[i].Divider = (u8)dividers.post_div;
1041 pi->acp_level_count++;
1045 pi->dpm_table_start +
1047 (u8 *)&pi->acp_level_count,
1049 pi->sram_end);
1053 pi->acp_interval = 1;
1056 pi->dpm_table_start +
1058 (u8 *)&pi->acp_interval,
1060 pi->sram_end);
1065 pi->dpm_table_start +
1067 (u8 *)&pi->acp_level,
1069 pi->sram_end);
1078 struct kv_power_info *pi = kv_get_pi(rdev);
1084 for (i = 0; i < pi->graphics_dpm_level_count; i++) {
1085 if (pi->caps_enable_dfs_bypass) {
1087 pi->graphics_level[i].ClkBypassCntl = 3;
1089 pi->graphics_level[i].ClkBypassCntl = 2;
1091 pi->graphics_level[i].ClkBypassCntl = 7;
1093 pi->graphics_level[i].ClkBypassCntl = 6;
1095 pi->graphics_level[i].ClkBypassCntl = 8;
1097 pi->graphics_level[i].ClkBypassCntl = 0;
1099 pi->graphics_level[i].ClkBypassCntl = 0;
1104 &pi->sys_info.sclk_voltage_mapping_table;
1105 for (i = 0; i < pi->graphics_dpm_level_count; i++) {
1106 if (pi->caps_enable_dfs_bypass) {
1108 pi->graphics_level[i].ClkBypassCntl = 3;
1110 pi->graphics_level[i].ClkBypassCntl = 2;
1112 pi->graphics_level[i].ClkBypassCntl = 7;
1114 pi->graphics_level[i].ClkBypassCntl = 6;
1116 pi->graphics_level[i].ClkBypassCntl = 8;
1118 pi->graphics_level[i].ClkBypassCntl = 0;
1120 pi->graphics_level[i].ClkBypassCntl = 0;
1134 struct kv_power_info *pi = kv_get_pi(rdev);
1136 pi->acp_boot_level = 0xff;
1143 struct kv_power_info *pi = kv_get_pi(rdev);
1145 pi->current_rps = *rps;
1146 pi->current_ps = *new_ps;
1147 pi->current_rps.ps_priv = &pi->current_ps;
1154 struct kv_power_info *pi = kv_get_pi(rdev);
1156 pi->requested_rps = *rps;
1157 pi->requested_ps = *new_ps;
1158 pi->requested_rps.ps_priv = &pi->requested_ps;
1163 struct kv_power_info *pi = kv_get_pi(rdev);
1166 if (pi->bapm_enable) {
1188 struct kv_power_info *pi = kv_get_pi(rdev);
1234 if (pi->enable_auto_thermal_throttling) {
1337 struct kv_power_info *pi = kv_get_pi(rdev);
1339 return kv_copy_bytes_to_smc(rdev, pi->soft_regs_start + reg_offset,
1340 (u8 *)&value, sizeof(u16), pi->sram_end);
1346 struct kv_power_info *pi = kv_get_pi(rdev);
1348 return kv_read_smc_sram_dword(rdev, pi->soft_regs_start + reg_offset,
1349 value, pi->sram_end);
1355 struct kv_power_info *pi = kv_get_pi(rdev);
1357 pi->low_sclk_interrupt_t = 0;
1362 struct kv_power_info *pi = kv_get_pi(rdev);
1365 if (pi->caps_fps) {
1369 pi->fps_high_t = cpu_to_be16(tmp);
1371 pi->dpm_table_start +
1373 (u8 *)&pi->fps_high_t,
1374 sizeof(u16), pi->sram_end);
1377 pi->fps_low_t = cpu_to_be16(tmp);
1380 pi->dpm_table_start +
1382 (u8 *)&pi->fps_low_t,
1383 sizeof(u16), pi->sram_end);
1391 struct kv_power_info *pi = kv_get_pi(rdev);
1393 pi->uvd_power_gated = false;
1394 pi->vce_power_gated = false;
1395 pi->samu_power_gated = false;
1396 pi->acp_power_gated = false;
1426 struct kv_power_info *pi = kv_get_pi(rdev);
1434 pi->uvd_boot_level = table->count - 1;
1436 pi->uvd_boot_level = 0;
1438 if (!pi->caps_uvd_dpm || pi->caps_stable_p_state) {
1439 mask = 1 << pi->uvd_boot_level;
1445 pi->dpm_table_start +
1447 (uint8_t *)&pi->uvd_boot_level,
1448 sizeof(u8), pi->sram_end);
1478 struct kv_power_info *pi = kv_get_pi(rdev);
1487 if (pi->caps_stable_p_state)
1488 pi->vce_boot_level = table->count - 1;
1490 pi->vce_boot_level = kv_get_vce_boot_level(rdev, radeon_new_state->evclk);
1493 pi->dpm_table_start +
1495 (u8 *)&pi->vce_boot_level,
1497 pi->sram_end);
1501 if (pi->caps_stable_p_state)
1504 (1 << pi->vce_boot_level));
1519 struct kv_power_info *pi = kv_get_pi(rdev);
1525 if (pi->caps_stable_p_state)
1526 pi->samu_boot_level = table->count - 1;
1528 pi->samu_boot_level = 0;
1531 pi->dpm_table_start +
1533 (u8 *)&pi->samu_boot_level,
1535 pi->sram_end);
1539 if (pi->caps_stable_p_state)
1542 (1 << pi->samu_boot_level));
1567 struct kv_power_info *pi = kv_get_pi(rdev);
1570 if (!pi->caps_stable_p_state) {
1572 if (acp_boot_level != pi->acp_boot_level) {
1573 pi->acp_boot_level = acp_boot_level;
1576 (1 << pi->acp_boot_level));
1583 struct kv_power_info *pi = kv_get_pi(rdev);
1589 if (pi->caps_stable_p_state)
1590 pi->acp_boot_level = table->count - 1;
1592 pi->acp_boot_level = kv_get_acp_boot_level(rdev);
1595 pi->dpm_table_start +
1597 (u8 *)&pi->acp_boot_level,
1599 pi->sram_end);
1603 if (pi->caps_stable_p_state)
1606 (1 << pi->acp_boot_level));
1614 struct kv_power_info *pi = kv_get_pi(rdev);
1616 if (pi->uvd_power_gated == gate)
1619 pi->uvd_power_gated = gate;
1622 if (pi->caps_uvd_pg) {
1627 if (pi->caps_uvd_pg)
1630 if (pi->caps_uvd_pg) {
1642 struct kv_power_info *pi = kv_get_pi(rdev);
1644 if (pi->vce_power_gated == gate)
1647 pi->vce_power_gated = gate;
1650 if (pi->caps_vce_pg) {
1655 if (pi->caps_vce_pg) {
1665 struct kv_power_info *pi = kv_get_pi(rdev);
1667 if (pi->samu_power_gated == gate)
1670 pi->samu_power_gated = gate;
1674 if (pi->caps_samu_pg)
1677 if (pi->caps_samu_pg)
1685 struct kv_power_info *pi = kv_get_pi(rdev);
1687 if (pi->acp_power_gated == gate)
1693 pi->acp_power_gated = gate;
1697 if (pi->caps_acp_pg)
1700 if (pi->caps_acp_pg)
1710 struct kv_power_info *pi = kv_get_pi(rdev);
1716 for (i = 0; i < pi->graphics_dpm_level_count; i++) {
1718 (i == (pi->graphics_dpm_level_count - 1))) {
1719 pi->lowest_valid = i;
1724 for (i = pi->graphics_dpm_level_count - 1; i > 0; i--) {
1728 pi->highest_valid = i;
1730 if (pi->lowest_valid > pi->highest_valid) {
1731 if ((new_ps->levels[0].sclk - table->entries[pi->highest_valid].clk) >
1732 (table->entries[pi->lowest_valid].clk - new_ps->levels[new_ps->num_levels - 1].sclk))
1733 pi->highest_valid = pi->lowest_valid;
1735 pi->lowest_valid = pi->highest_valid;
1739 &pi->sys_info.sclk_voltage_mapping_table;
1741 for (i = 0; i < (int)pi->graphics_dpm_level_count; i++) {
1743 i == (int)(pi->graphics_dpm_level_count - 1)) {
1744 pi->lowest_valid = i;
1749 for (i = pi->graphics_dpm_level_count - 1; i > 0; i--) {
1754 pi->highest_valid = i;
1756 if (pi->lowest_valid > pi->highest_valid) {
1758 table->entries[pi->highest_valid].sclk_frequency) >
1759 (table->entries[pi->lowest_valid].sclk_frequency -
1761 pi->highest_valid = pi->lowest_valid;
1763 pi->lowest_valid = pi->highest_valid;
1772 struct kv_power_info *pi = kv_get_pi(rdev);
1776 if (pi->caps_enable_dfs_bypass) {
1778 pi->graphics_level[pi->graphics_boot_level].ClkBypassCntl : 0;
1780 (pi->dpm_table_start +
1782 (pi->graphics_boot_level * sizeof(SMU7_Fusion_GraphicsLevel)) +
1785 sizeof(u8), pi->sram_end);
1794 struct kv_power_info *pi = kv_get_pi(rdev);
1798 if (pi->enable_nb_dpm && !pi->nb_dpm_enabled) {
1801 pi->nb_dpm_enabled = true;
1804 if (pi->enable_nb_dpm && pi->nb_dpm_enabled) {
1807 pi->nb_dpm_enabled = false;
1840 struct kv_power_info *pi = kv_get_pi(rdev);
1847 &pi->requested_rps,
1848 &pi->current_rps);
1855 struct kv_power_info *pi = kv_get_pi(rdev);
1856 struct radeon_ps *new_ps = &pi->requested_rps;
1857 struct radeon_ps *old_ps = &pi->current_rps;
1860 if (pi->bapm_enable) {
1869 if (pi->enable_dpm) {
1898 if (pi->enable_dpm) {
1929 struct kv_power_info *pi = kv_get_pi(rdev);
1930 struct radeon_ps *new_ps = &pi->requested_rps;
1945 struct kv_power_info *pi = kv_get_pi(rdev);
1960 kv_set_enabled_level(rdev, pi->graphics_boot_level);
1970 struct kv_power_info *pi = kv_get_pi(rdev);
1972 if (pi->sys_info.sclk_voltage_mapping_table.num_max_dpm_entries > 0) {
1973 int idx = pi->sys_info.sclk_voltage_mapping_table.num_max_dpm_entries - 1;
1975 pi->sys_info.sclk_voltage_mapping_table.entries[idx].sclk_frequency;
1978 pi->sys_info.sclk_voltage_mapping_table.entries[idx].vid_2bit);
1981 table->mclk = pi->sys_info.nbp_memory_clock[0];
2028 struct kv_power_info *pi = kv_get_pi(rdev);
2030 pi->boot_pl.sclk = pi->sys_info.bootup_sclk;
2031 pi->boot_pl.vddc_index = pi->sys_info.bootup_nb_voltage_index;
2032 pi->boot_pl.ds_divider_index = 0;
2033 pi->boot_pl.ss_divider_index = 0;
2034 pi->boot_pl.allow_gnb_slow = 1;
2035 pi->boot_pl.force_nbp_state = 0;
2036 pi->boot_pl.display_wm = 0;
2037 pi->boot_pl.vce_wm = 0;
2083 struct kv_power_info *pi = kv_get_pi(rdev);
2092 if (!pi->caps_sclk_ds)
2106 struct kv_power_info *pi = kv_get_pi(rdev);
2113 if (pi->high_voltage_t &&
2115 pi->high_voltage_t)) {
2122 &pi->sys_info.sclk_voltage_mapping_table;
2125 if (pi->high_voltage_t &&
2127 pi->high_voltage_t)) {
2143 struct kv_power_info *pi = kv_get_pi(rdev);
2165 if (pi->caps_stable_p_state) {
2195 if (pi->high_voltage_t &&
2196 (pi->high_voltage_t <
2204 &pi->sys_info.sclk_voltage_mapping_table;
2207 if (pi->high_voltage_t &&
2208 (pi->high_voltage_t <
2216 if (pi->caps_stable_p_state) {
2222 pi->video_start = new_rps->dclk || new_rps->vclk ||
2227 pi->battery_state = true;
2229 pi->battery_state = false;
2242 if (pi->sys_info.nb_dpm_enable) {
2243 force_high = (mclk >= pi->sys_info.nbp_memory_clock[3]) ||
2244 pi->video_start || (rdev->pm.dpm.new_active_crtc_count >= 3) ||
2245 pi->disable_nb_ps3_in_battery;
2257 struct kv_power_info *pi = kv_get_pi(rdev);
2259 pi->graphics_level[index].EnabledForThrottle = enable ? 1 : 0;
2264 struct kv_power_info *pi = kv_get_pi(rdev);
2268 if (pi->lowest_valid > pi->highest_valid)
2271 for (i = pi->lowest_valid; i <= pi->highest_valid; i++) {
2272 pi->graphics_level[i].DeepSleepDivId =
2274 be32_to_cpu(pi->graphics_level[i].SclkFrequency),
2282 struct kv_power_info *pi = kv_get_pi(rdev);
2289 if (pi->lowest_valid > pi->highest_valid)
2293 for (i = pi->lowest_valid; i <= pi->highest_valid; i++) {
2294 pi->graphics_level[i].GnbSlow = 1;
2295 pi->graphics_level[i].ForceNbPs1 = 0;
2296 pi->graphics_level[i].UpH = 0;
2299 if (!pi->sys_info.nb_dpm_enable)
2302 force_high = ((mclk >= pi->sys_info.nbp_memory_clock[3]) ||
2303 (rdev->pm.dpm.new_active_crtc_count >= 3) || pi->video_start);
2306 for (i = pi->lowest_valid; i <= pi->highest_valid; i++)
2307 pi->graphics_level[i].GnbSlow = 0;
2309 if (pi->battery_state)
2310 pi->graphics_level[0].ForceNbPs1 = 1;
2312 pi->graphics_level[1].GnbSlow = 0;
2313 pi->graphics_level[2].GnbSlow = 0;
2314 pi->graphics_level[3].GnbSlow = 0;
2315 pi->graphics_level[4].GnbSlow = 0;
2318 for (i = pi->lowest_valid; i <= pi->highest_valid; i++) {
2319 pi->graphics_level[i].GnbSlow = 1;
2320 pi->graphics_level[i].ForceNbPs1 = 0;
2321 pi->graphics_level[i].UpH = 0;
2324 if (pi->sys_info.nb_dpm_enable && pi->battery_state) {
2325 pi->graphics_level[pi->lowest_valid].UpH = 0x28;
2326 pi->graphics_level[pi->lowest_valid].GnbSlow = 0;
2327 if (pi->lowest_valid != pi->highest_valid)
2328 pi->graphics_level[pi->lowest_valid].ForceNbPs1 = 1;
2336 struct kv_power_info *pi = kv_get_pi(rdev);
2339 if (pi->lowest_valid > pi->highest_valid)
2342 for (i = pi->lowest_valid; i <= pi->highest_valid; i++)
2343 pi->graphics_level[i].DisplayWatermark = (i == pi->highest_valid) ? 1 : 0;
2350 struct kv_power_info *pi = kv_get_pi(rdev);
2358 pi->graphics_dpm_level_count = 0;
2360 if (pi->high_voltage_t &&
2361 (pi->high_voltage_t <
2367 &pi->sys_info.vid_mapping_table,
2370 kv_set_at(rdev, i, pi->at[i]);
2372 pi->graphics_dpm_level_count++;
2376 &pi->sys_info.sclk_voltage_mapping_table;
2378 pi->graphics_dpm_level_count = 0;
2380 if (pi->high_voltage_t &&
2381 pi->high_voltage_t <
2387 kv_set_at(rdev, i, pi->at[i]);
2389 pi->graphics_dpm_level_count++;
2399 struct kv_power_info *pi = kv_get_pi(rdev);
2403 if (i >= pi->lowest_valid && i <= pi->highest_valid)
2419 struct kv_power_info *pi = kv_get_pi(rdev);
2422 for (i = pi->lowest_valid; i <= pi->highest_valid; i++)
2434 struct kv_power_info *pi = kv_get_pi(rdev);
2440 if (pi->sys_info.nb_dpm_enable) {
2491 struct kv_power_info *pi = kv_get_pi(rdev);
2508 pi->sys_info.bootup_sclk = le32_to_cpu(igp_info->info_8.ulBootUpEngineClock);
2509 pi->sys_info.bootup_uma_clk = le32_to_cpu(igp_info->info_8.ulBootUpUMAClock);
2510 pi->sys_info.bootup_nb_voltage_index =
2513 pi->sys_info.htc_tmp_lmt = 203;
2515 pi->sys_info.htc_tmp_lmt = igp_info->info_8.ucHtcTmpLmt;
2517 pi->sys_info.htc_hyst_lmt = 5;
2519 pi->sys_info.htc_hyst_lmt = igp_info->info_8.ucHtcHystLmt;
2520 if (pi->sys_info.htc_tmp_lmt <= pi->sys_info.htc_hyst_lmt) {
2525 pi->sys_info.nb_dpm_enable = true;
2527 pi->sys_info.nb_dpm_enable = false;
2530 pi->sys_info.nbp_memory_clock[i] =
2532 pi->sys_info.nbp_n_clock[i] =
2537 pi->caps_enable_dfs_bypass = true;
2540 &pi->sys_info.sclk_voltage_mapping_table,
2544 &pi->sys_info.vid_mapping_table,
2577 struct kv_power_info *pi = kv_get_pi(rdev);
2580 ps->levels[0] = pi->boot_pl;
2614 struct kv_power_info *pi = kv_get_pi(rdev);
2626 if (pi->caps_sclk_ds) {
2724 struct kv_power_info *pi;
2727 pi = kzalloc(sizeof(struct kv_power_info), GFP_KERNEL);
2728 if (pi == NULL)
2730 rdev->pm.dpm.priv = pi;
2741 pi->at[i] = TRINITY_AT_DFLT;
2743 pi->sram_end = SMC_RAM_END;
2747 pi->enable_nb_dpm = false;
2749 pi->enable_nb_dpm = true;
2751 pi->caps_power_containment = true;
2752 pi->caps_cac = true;
2753 pi->enable_didt = false;
2754 if (pi->enable_didt) {
2755 pi->caps_sq_ramping = true;
2756 pi->caps_db_ramping = true;
2757 pi->caps_td_ramping = true;
2758 pi->caps_tcp_ramping = true;
2761 pi->caps_sclk_ds = true;
2762 pi->enable_auto_thermal_throttling = true;
2763 pi->disable_nb_ps3_in_battery = false;
2767 pi->bapm_enable = true;
2769 pi->bapm_enable = false;
2771 pi->bapm_enable = false;
2773 pi->bapm_enable = true;
2775 pi->voltage_drop_t = 0;
2776 pi->caps_sclk_throttle_low_notification = false;
2777 pi->caps_fps = false; /* true? */
2778 pi->caps_uvd_pg = true;
2779 pi->caps_uvd_dpm = true;
2780 pi->caps_vce_pg = false; /* XXX true */
2781 pi->caps_samu_pg = false;
2782 pi->caps_acp_pg = false;
2783 pi->caps_stable_p_state = false;
2796 pi->enable_dpm = true;
2804 struct kv_power_info *pi = kv_get_pi(rdev);
2814 sclk = be32_to_cpu(pi->graphics_level[current_index].SclkFrequency);
2818 seq_printf(m, "uvd %sabled\n", pi->uvd_power_gated ? "dis" : "en");
2819 seq_printf(m, "vce %sabled\n", pi->vce_power_gated ? "dis" : "en");
2827 struct kv_power_info *pi = kv_get_pi(rdev);
2836 sclk = be32_to_cpu(pi->graphics_level[current_index].SclkFrequency);
2843 struct kv_power_info *pi = kv_get_pi(rdev);
2845 return pi->sys_info.bootup_uma_clk;
2885 struct kv_power_info *pi = kv_get_pi(rdev);
2886 struct kv_ps *requested_state = kv_get_ps(&pi->requested_rps);
2896 struct kv_power_info *pi = kv_get_pi(rdev);
2898 return pi->sys_info.bootup_uma_clk;