Lines Matching defs:rdev
37 static int kv_enable_nb_dpm(struct radeon_device *rdev,
39 static void kv_init_graphics_levels(struct radeon_device *rdev);
40 static int kv_calculate_ds_divider(struct radeon_device *rdev);
41 static int kv_calculate_nbps_level_settings(struct radeon_device *rdev);
42 static int kv_calculate_dpm_settings(struct radeon_device *rdev);
43 static void kv_enable_new_levels(struct radeon_device *rdev);
44 static void kv_program_nbps_index_settings(struct radeon_device *rdev,
46 static int kv_set_enabled_level(struct radeon_device *rdev, u32 level);
47 static int kv_set_enabled_levels(struct radeon_device *rdev);
48 static int kv_force_dpm_highest(struct radeon_device *rdev);
49 static int kv_force_dpm_lowest(struct radeon_device *rdev);
50 static void kv_apply_state_adjust_rules(struct radeon_device *rdev,
53 static int kv_set_thermal_temperature_range(struct radeon_device *rdev,
55 static int kv_init_fps_limits(struct radeon_device *rdev);
57 void kv_dpm_powergate_uvd(struct radeon_device *rdev, bool gate);
58 static void kv_dpm_powergate_vce(struct radeon_device *rdev, bool gate);
59 static void kv_dpm_powergate_samu(struct radeon_device *rdev, bool gate);
60 static void kv_dpm_powergate_acp(struct radeon_device *rdev, bool gate);
62 extern void cik_enter_rlc_safe_mode(struct radeon_device *rdev);
63 extern void cik_exit_rlc_safe_mode(struct radeon_device *rdev);
64 extern void cik_update_cg(struct radeon_device *rdev,
250 static struct kv_power_info *kv_get_pi(struct radeon_device *rdev)
252 struct kv_power_info *pi = rdev->pm.dpm.priv;
258 static void kv_program_local_cac_table(struct radeon_device *rdev,
283 static int kv_program_pt_config_registers(struct radeon_device *rdev,
332 static void kv_do_enable_didt(struct radeon_device *rdev, bool enable)
334 struct kv_power_info *pi = kv_get_pi(rdev);
374 static int kv_enable_didt(struct radeon_device *rdev, bool enable)
376 struct kv_power_info *pi = kv_get_pi(rdev);
383 cik_enter_rlc_safe_mode(rdev);
386 ret = kv_program_pt_config_registers(rdev, didt_config_kv);
388 cik_exit_rlc_safe_mode(rdev);
393 kv_do_enable_didt(rdev, enable);
395 cik_exit_rlc_safe_mode(rdev);
402 static void kv_initialize_hardware_cac_manager(struct radeon_device *rdev)
404 struct kv_power_info *pi = kv_get_pi(rdev);
409 kv_program_local_cac_table(rdev, sx_local_cac_cfg_kv, sx0_cac_config_reg);
413 kv_program_local_cac_table(rdev, mc0_local_cac_cfg_kv, mc0_cac_config_reg);
417 kv_program_local_cac_table(rdev, mc1_local_cac_cfg_kv, mc1_cac_config_reg);
421 kv_program_local_cac_table(rdev, mc2_local_cac_cfg_kv, mc2_cac_config_reg);
425 kv_program_local_cac_table(rdev, mc3_local_cac_cfg_kv, mc3_cac_config_reg);
429 kv_program_local_cac_table(rdev, cpl_local_cac_cfg_kv, cpl_cac_config_reg);
434 static int kv_enable_smc_cac(struct radeon_device *rdev, bool enable)
436 struct kv_power_info *pi = kv_get_pi(rdev);
441 ret = kv_notify_message_to_smu(rdev, PPSMC_MSG_EnableCac);
447 kv_notify_message_to_smu(rdev, PPSMC_MSG_DisableCac);
455 static int kv_process_firmware_header(struct radeon_device *rdev)
457 struct kv_power_info *pi = kv_get_pi(rdev);
461 ret = kv_read_smc_sram_dword(rdev, SMU7_FIRMWARE_HEADER_LOCATION +
468 ret = kv_read_smc_sram_dword(rdev, SMU7_FIRMWARE_HEADER_LOCATION +
478 static int kv_enable_dpm_voltage_scaling(struct radeon_device *rdev)
480 struct kv_power_info *pi = kv_get_pi(rdev);
485 ret = kv_copy_bytes_to_smc(rdev,
494 static int kv_set_dpm_interval(struct radeon_device *rdev)
496 struct kv_power_info *pi = kv_get_pi(rdev);
501 ret = kv_copy_bytes_to_smc(rdev,
510 static int kv_set_dpm_boot_state(struct radeon_device *rdev)
512 struct kv_power_info *pi = kv_get_pi(rdev);
515 ret = kv_copy_bytes_to_smc(rdev,
524 static void kv_program_vc(struct radeon_device *rdev)
529 static void kv_clear_vc(struct radeon_device *rdev)
534 static int kv_set_divider_value(struct radeon_device *rdev,
537 struct kv_power_info *pi = kv_get_pi(rdev);
541 ret = radeon_atom_get_clock_dividers(rdev, COMPUTE_ENGINE_PLL_PARAM,
552 static u32 kv_convert_vid2_to_vid7(struct radeon_device *rdev,
557 &rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk;
574 static u32 kv_convert_vid7_to_vid2(struct radeon_device *rdev,
579 &rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk;
598 static u16 kv_convert_8bit_index_to_voltage(struct radeon_device *rdev,
604 static u16 kv_convert_2bit_index_to_voltage(struct radeon_device *rdev,
607 struct kv_power_info *pi = kv_get_pi(rdev);
608 u32 vid_8bit = kv_convert_vid2_to_vid7(rdev,
612 return kv_convert_8bit_index_to_voltage(rdev, (u16)vid_8bit);
616 static int kv_set_vid(struct radeon_device *rdev, u32 index, u32 vid)
618 struct kv_power_info *pi = kv_get_pi(rdev);
622 cpu_to_be32(kv_convert_2bit_index_to_voltage(rdev, vid));
627 static int kv_set_at(struct radeon_device *rdev, u32 index, u32 at)
629 struct kv_power_info *pi = kv_get_pi(rdev);
636 static void kv_dpm_power_level_enable(struct radeon_device *rdev,
639 struct kv_power_info *pi = kv_get_pi(rdev);
644 static void kv_start_dpm(struct radeon_device *rdev)
651 kv_smc_dpm_enable(rdev, true);
654 static void kv_stop_dpm(struct radeon_device *rdev)
656 kv_smc_dpm_enable(rdev, false);
659 static void kv_start_am(struct radeon_device *rdev)
669 static void kv_reset_am(struct radeon_device *rdev)
678 static int kv_freeze_sclk_dpm(struct radeon_device *rdev, bool freeze)
680 return kv_notify_message_to_smu(rdev, freeze ?
684 static int kv_force_lowest_valid(struct radeon_device *rdev)
686 return kv_force_dpm_lowest(rdev);
689 static int kv_unforce_levels(struct radeon_device *rdev)
691 if (rdev->family == CHIP_KABINI || rdev->family == CHIP_MULLINS)
692 return kv_notify_message_to_smu(rdev, PPSMC_MSG_NoForcedLevel);
694 return kv_set_enabled_levels(rdev);
697 static int kv_update_sclk_t(struct radeon_device *rdev)
699 struct kv_power_info *pi = kv_get_pi(rdev);
706 ret = kv_copy_bytes_to_smc(rdev,
715 static int kv_program_bootup_state(struct radeon_device *rdev)
717 struct kv_power_info *pi = kv_get_pi(rdev);
720 &rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk;
729 kv_dpm_power_level_enable(rdev, i, true);
743 kv_dpm_power_level_enable(rdev, i, true);
748 static int kv_enable_auto_thermal_throttling(struct radeon_device *rdev)
750 struct kv_power_info *pi = kv_get_pi(rdev);
755 ret = kv_copy_bytes_to_smc(rdev,
764 static int kv_upload_dpm_settings(struct radeon_device *rdev)
766 struct kv_power_info *pi = kv_get_pi(rdev);
769 ret = kv_copy_bytes_to_smc(rdev,
779 ret = kv_copy_bytes_to_smc(rdev,
793 static u32 kv_get_clk_bypass(struct radeon_device *rdev, u32 clk)
795 struct kv_power_info *pi = kv_get_pi(rdev);
818 static int kv_populate_uvd_table(struct radeon_device *rdev)
820 struct kv_power_info *pi = kv_get_pi(rdev);
822 &rdev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table;
841 (u8)kv_get_clk_bypass(rdev, table->entries[i].vclk);
843 (u8)kv_get_clk_bypass(rdev, table->entries[i].dclk);
845 ret = radeon_atom_get_clock_dividers(rdev, COMPUTE_ENGINE_PLL_PARAM,
851 ret = radeon_atom_get_clock_dividers(rdev, COMPUTE_ENGINE_PLL_PARAM,
860 ret = kv_copy_bytes_to_smc(rdev,
870 ret = kv_copy_bytes_to_smc(rdev,
878 ret = kv_copy_bytes_to_smc(rdev,
889 static int kv_populate_vce_table(struct radeon_device *rdev)
891 struct kv_power_info *pi = kv_get_pi(rdev);
895 &rdev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table;
911 (u8)kv_get_clk_bypass(rdev, table->entries[i].evclk);
913 ret = radeon_atom_get_clock_dividers(rdev, COMPUTE_ENGINE_PLL_PARAM,
922 ret = kv_copy_bytes_to_smc(rdev,
933 ret = kv_copy_bytes_to_smc(rdev,
942 ret = kv_copy_bytes_to_smc(rdev,
952 static int kv_populate_samu_table(struct radeon_device *rdev)
954 struct kv_power_info *pi = kv_get_pi(rdev);
956 &rdev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table;
974 (u8)kv_get_clk_bypass(rdev, table->entries[i].clk);
976 ret = radeon_atom_get_clock_dividers(rdev, COMPUTE_ENGINE_PLL_PARAM,
985 ret = kv_copy_bytes_to_smc(rdev,
996 ret = kv_copy_bytes_to_smc(rdev,
1005 ret = kv_copy_bytes_to_smc(rdev,
1018 static int kv_populate_acp_table(struct radeon_device *rdev)
1020 struct kv_power_info *pi = kv_get_pi(rdev);
1022 &rdev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table;
1035 ret = radeon_atom_get_clock_dividers(rdev, COMPUTE_ENGINE_PLL_PARAM,
1044 ret = kv_copy_bytes_to_smc(rdev,
1055 ret = kv_copy_bytes_to_smc(rdev,
1064 ret = kv_copy_bytes_to_smc(rdev,
1076 static void kv_calculate_dfs_bypass_settings(struct radeon_device *rdev)
1078 struct kv_power_info *pi = kv_get_pi(rdev);
1081 &rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk;
1126 static int kv_enable_ulv(struct radeon_device *rdev, bool enable)
1128 return kv_notify_message_to_smu(rdev, enable ?
1132 static void kv_reset_acp_boot_level(struct radeon_device *rdev)
1134 struct kv_power_info *pi = kv_get_pi(rdev);
1139 static void kv_update_current_ps(struct radeon_device *rdev,
1143 struct kv_power_info *pi = kv_get_pi(rdev);
1150 static void kv_update_requested_ps(struct radeon_device *rdev,
1154 struct kv_power_info *pi = kv_get_pi(rdev);
1161 void kv_dpm_enable_bapm(struct radeon_device *rdev, bool enable)
1163 struct kv_power_info *pi = kv_get_pi(rdev);
1167 ret = kv_smc_bapm_enable(rdev, enable);
1173 static void kv_enable_thermal_int(struct radeon_device *rdev, bool enable)
1186 int kv_dpm_enable(struct radeon_device *rdev)
1188 struct kv_power_info *pi = kv_get_pi(rdev);
1191 ret = kv_process_firmware_header(rdev);
1196 kv_init_fps_limits(rdev);
1197 kv_init_graphics_levels(rdev);
1198 ret = kv_program_bootup_state(rdev);
1203 kv_calculate_dfs_bypass_settings(rdev);
1204 ret = kv_upload_dpm_settings(rdev);
1209 ret = kv_populate_uvd_table(rdev);
1214 ret = kv_populate_vce_table(rdev);
1219 ret = kv_populate_samu_table(rdev);
1224 ret = kv_populate_acp_table(rdev);
1229 kv_program_vc(rdev);
1231 kv_initialize_hardware_cac_manager(rdev);
1233 kv_start_am(rdev);
1235 ret = kv_enable_auto_thermal_throttling(rdev);
1241 ret = kv_enable_dpm_voltage_scaling(rdev);
1246 ret = kv_set_dpm_interval(rdev);
1251 ret = kv_set_dpm_boot_state(rdev);
1256 ret = kv_enable_ulv(rdev, true);
1261 kv_start_dpm(rdev);
1262 ret = kv_enable_didt(rdev, true);
1267 ret = kv_enable_smc_cac(rdev, true);
1273 kv_reset_acp_boot_level(rdev);
1275 ret = kv_smc_bapm_enable(rdev, false);
1281 kv_update_current_ps(rdev, rdev->pm.dpm.boot_ps);
1286 int kv_dpm_late_enable(struct radeon_device *rdev)
1290 if (rdev->irq.installed &&
1291 r600_is_internal_thermal_sensor(rdev->pm.int_thermal_type)) {
1292 ret = kv_set_thermal_temperature_range(rdev, R600_TEMP_RANGE_MIN, R600_TEMP_RANGE_MAX);
1297 kv_enable_thermal_int(rdev, true);
1301 kv_dpm_powergate_acp(rdev, true);
1302 kv_dpm_powergate_samu(rdev, true);
1303 kv_dpm_powergate_vce(rdev, true);
1304 kv_dpm_powergate_uvd(rdev, true);
1309 void kv_dpm_disable(struct radeon_device *rdev)
1311 kv_smc_bapm_enable(rdev, false);
1313 if (rdev->family == CHIP_MULLINS)
1314 kv_enable_nb_dpm(rdev, false);
1317 kv_dpm_powergate_acp(rdev, false);
1318 kv_dpm_powergate_samu(rdev, false);
1319 kv_dpm_powergate_vce(rdev, false);
1320 kv_dpm_powergate_uvd(rdev, false);
1322 kv_enable_smc_cac(rdev, false);
1323 kv_enable_didt(rdev, false);
1324 kv_clear_vc(rdev);
1325 kv_stop_dpm(rdev);
1326 kv_enable_ulv(rdev, false);
1327 kv_reset_am(rdev);
1328 kv_enable_thermal_int(rdev, false);
1330 kv_update_current_ps(rdev, rdev->pm.dpm.boot_ps);
1334 static int kv_write_smc_soft_register(struct radeon_device *rdev,
1337 struct kv_power_info *pi = kv_get_pi(rdev);
1339 return kv_copy_bytes_to_smc(rdev, pi->soft_regs_start + reg_offset,
1343 static int kv_read_smc_soft_register(struct radeon_device *rdev,
1346 struct kv_power_info *pi = kv_get_pi(rdev);
1348 return kv_read_smc_sram_dword(rdev, pi->soft_regs_start + reg_offset,
1353 static void kv_init_sclk_t(struct radeon_device *rdev)
1355 struct kv_power_info *pi = kv_get_pi(rdev);
1360 static int kv_init_fps_limits(struct radeon_device *rdev)
1362 struct kv_power_info *pi = kv_get_pi(rdev);
1370 ret = kv_copy_bytes_to_smc(rdev,
1379 ret = kv_copy_bytes_to_smc(rdev,
1389 static void kv_init_powergate_state(struct radeon_device *rdev)
1391 struct kv_power_info *pi = kv_get_pi(rdev);
1400 static int kv_enable_uvd_dpm(struct radeon_device *rdev, bool enable)
1402 return kv_notify_message_to_smu(rdev, enable ?
1406 static int kv_enable_vce_dpm(struct radeon_device *rdev, bool enable)
1408 return kv_notify_message_to_smu(rdev, enable ?
1412 static int kv_enable_samu_dpm(struct radeon_device *rdev, bool enable)
1414 return kv_notify_message_to_smu(rdev, enable ?
1418 static int kv_enable_acp_dpm(struct radeon_device *rdev, bool enable)
1420 return kv_notify_message_to_smu(rdev, enable ?
1424 static int kv_update_uvd_dpm(struct radeon_device *rdev, bool gate)
1426 struct kv_power_info *pi = kv_get_pi(rdev);
1428 &rdev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table;
1444 ret = kv_copy_bytes_to_smc(rdev,
1452 kv_send_msg_to_smc_with_parameter(rdev,
1457 return kv_enable_uvd_dpm(rdev, !gate);
1460 static u8 kv_get_vce_boot_level(struct radeon_device *rdev, u32 evclk)
1464 &rdev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table;
1474 static int kv_update_vce_dpm(struct radeon_device *rdev,
1478 struct kv_power_info *pi = kv_get_pi(rdev);
1480 &rdev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table;
1484 kv_dpm_powergate_vce(rdev, false);
1486 cik_update_cg(rdev, RADEON_CG_BLOCK_VCE, false);
1490 pi->vce_boot_level = kv_get_vce_boot_level(rdev, radeon_new_state->evclk);
1492 ret = kv_copy_bytes_to_smc(rdev,
1502 kv_send_msg_to_smc_with_parameter(rdev,
1506 kv_enable_vce_dpm(rdev, true);
1508 kv_enable_vce_dpm(rdev, false);
1510 cik_update_cg(rdev, RADEON_CG_BLOCK_VCE, true);
1511 kv_dpm_powergate_vce(rdev, true);
1517 static int kv_update_samu_dpm(struct radeon_device *rdev, bool gate)
1519 struct kv_power_info *pi = kv_get_pi(rdev);
1521 &rdev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table;
1530 ret = kv_copy_bytes_to_smc(rdev,
1540 kv_send_msg_to_smc_with_parameter(rdev,
1545 return kv_enable_samu_dpm(rdev, !gate);
1548 static u8 kv_get_acp_boot_level(struct radeon_device *rdev)
1552 &rdev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table;
1565 static void kv_update_acp_boot_level(struct radeon_device *rdev)
1567 struct kv_power_info *pi = kv_get_pi(rdev);
1571 acp_boot_level = kv_get_acp_boot_level(rdev);
1574 kv_send_msg_to_smc_with_parameter(rdev,
1581 static int kv_update_acp_dpm(struct radeon_device *rdev, bool gate)
1583 struct kv_power_info *pi = kv_get_pi(rdev);
1585 &rdev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table;
1592 pi->acp_boot_level = kv_get_acp_boot_level(rdev);
1594 ret = kv_copy_bytes_to_smc(rdev,
1604 kv_send_msg_to_smc_with_parameter(rdev,
1609 return kv_enable_acp_dpm(rdev, !gate);
1612 void kv_dpm_powergate_uvd(struct radeon_device *rdev, bool gate)
1614 struct kv_power_info *pi = kv_get_pi(rdev);
1623 uvd_v1_0_stop(rdev);
1624 cik_update_cg(rdev, RADEON_CG_BLOCK_UVD, false);
1626 kv_update_uvd_dpm(rdev, gate);
1628 kv_notify_message_to_smu(rdev, PPSMC_MSG_UVDPowerOFF);
1631 kv_notify_message_to_smu(rdev, PPSMC_MSG_UVDPowerON);
1632 uvd_v4_2_resume(rdev);
1633 uvd_v1_0_start(rdev);
1634 cik_update_cg(rdev, RADEON_CG_BLOCK_UVD, true);
1636 kv_update_uvd_dpm(rdev, gate);
1640 static void kv_dpm_powergate_vce(struct radeon_device *rdev, bool gate)
1642 struct kv_power_info *pi = kv_get_pi(rdev);
1652 kv_notify_message_to_smu(rdev, PPSMC_MSG_VCEPowerOFF);
1656 kv_notify_message_to_smu(rdev, PPSMC_MSG_VCEPowerON);
1657 vce_v2_0_resume(rdev);
1658 vce_v1_0_start(rdev);
1663 static void kv_dpm_powergate_samu(struct radeon_device *rdev, bool gate)
1665 struct kv_power_info *pi = kv_get_pi(rdev);
1673 kv_update_samu_dpm(rdev, true);
1675 kv_notify_message_to_smu(rdev, PPSMC_MSG_SAMPowerOFF);
1678 kv_notify_message_to_smu(rdev, PPSMC_MSG_SAMPowerON);
1679 kv_update_samu_dpm(rdev, false);
1683 static void kv_dpm_powergate_acp(struct radeon_device *rdev, bool gate)
1685 struct kv_power_info *pi = kv_get_pi(rdev);
1690 if (rdev->family == CHIP_KABINI || rdev->family == CHIP_MULLINS)
1696 kv_update_acp_dpm(rdev, true);
1698 kv_notify_message_to_smu(rdev, PPSMC_MSG_ACPPowerOFF);
1701 kv_notify_message_to_smu(rdev, PPSMC_MSG_ACPPowerON);
1702 kv_update_acp_dpm(rdev, false);
1706 static void kv_set_valid_clock_range(struct radeon_device *rdev,
1710 struct kv_power_info *pi = kv_get_pi(rdev);
1713 &rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk;
1768 static int kv_update_dfs_bypass_settings(struct radeon_device *rdev,
1772 struct kv_power_info *pi = kv_get_pi(rdev);
1779 ret = kv_copy_bytes_to_smc(rdev,
1791 static int kv_enable_nb_dpm(struct radeon_device *rdev,
1794 struct kv_power_info *pi = kv_get_pi(rdev);
1799 ret = kv_notify_message_to_smu(rdev, PPSMC_MSG_NBDPM_Enable);
1805 ret = kv_notify_message_to_smu(rdev, PPSMC_MSG_NBDPM_Disable);
1814 int kv_dpm_force_performance_level(struct radeon_device *rdev,
1820 ret = kv_force_dpm_highest(rdev);
1824 ret = kv_force_dpm_lowest(rdev);
1828 ret = kv_unforce_levels(rdev);
1833 rdev->pm.dpm.forced_level = level;
1838 int kv_dpm_pre_set_power_state(struct radeon_device *rdev)
1840 struct kv_power_info *pi = kv_get_pi(rdev);
1841 struct radeon_ps requested_ps = *rdev->pm.dpm.requested_ps;
1844 kv_update_requested_ps(rdev, new_ps);
1846 kv_apply_state_adjust_rules(rdev,
1853 int kv_dpm_set_power_state(struct radeon_device *rdev)
1855 struct kv_power_info *pi = kv_get_pi(rdev);
1861 ret = kv_smc_bapm_enable(rdev, rdev->pm.dpm.ac_power);
1868 if (rdev->family == CHIP_KABINI || rdev->family == CHIP_MULLINS) {
1870 kv_set_valid_clock_range(rdev, new_ps);
1871 kv_update_dfs_bypass_settings(rdev, new_ps);
1872 ret = kv_calculate_ds_divider(rdev);
1877 kv_calculate_nbps_level_settings(rdev);
1878 kv_calculate_dpm_settings(rdev);
1879 kv_force_lowest_valid(rdev);
1880 kv_enable_new_levels(rdev);
1881 kv_upload_dpm_settings(rdev);
1882 kv_program_nbps_index_settings(rdev, new_ps);
1883 kv_unforce_levels(rdev);
1884 kv_set_enabled_levels(rdev);
1885 kv_force_lowest_valid(rdev);
1886 kv_unforce_levels(rdev);
1888 ret = kv_update_vce_dpm(rdev, new_ps, old_ps);
1893 kv_update_sclk_t(rdev);
1894 if (rdev->family == CHIP_MULLINS)
1895 kv_enable_nb_dpm(rdev, true);
1899 kv_set_valid_clock_range(rdev, new_ps);
1900 kv_update_dfs_bypass_settings(rdev, new_ps);
1901 ret = kv_calculate_ds_divider(rdev);
1906 kv_calculate_nbps_level_settings(rdev);
1907 kv_calculate_dpm_settings(rdev);
1908 kv_freeze_sclk_dpm(rdev, true);
1909 kv_upload_dpm_settings(rdev);
1910 kv_program_nbps_index_settings(rdev, new_ps);
1911 kv_freeze_sclk_dpm(rdev, false);
1912 kv_set_enabled_levels(rdev);
1913 ret = kv_update_vce_dpm(rdev, new_ps, old_ps);
1918 kv_update_acp_boot_level(rdev);
1919 kv_update_sclk_t(rdev);
1920 kv_enable_nb_dpm(rdev, true);
1927 void kv_dpm_post_set_power_state(struct radeon_device *rdev)
1929 struct kv_power_info *pi = kv_get_pi(rdev);
1932 kv_update_current_ps(rdev, new_ps);
1935 void kv_dpm_setup_asic(struct radeon_device *rdev)
1937 sumo_take_smu_control(rdev, true);
1938 kv_init_powergate_state(rdev);
1939 kv_init_sclk_t(rdev);
1943 void kv_dpm_reset_asic(struct radeon_device *rdev)
1945 struct kv_power_info *pi = kv_get_pi(rdev);
1947 if (rdev->family == CHIP_KABINI || rdev->family == CHIP_MULLINS) {
1948 kv_force_lowest_valid(rdev);
1949 kv_init_graphics_levels(rdev);
1950 kv_program_bootup_state(rdev);
1951 kv_upload_dpm_settings(rdev);
1952 kv_force_lowest_valid(rdev);
1953 kv_unforce_levels(rdev);
1955 kv_init_graphics_levels(rdev);
1956 kv_program_bootup_state(rdev);
1957 kv_freeze_sclk_dpm(rdev, true);
1958 kv_upload_dpm_settings(rdev);
1959 kv_freeze_sclk_dpm(rdev, false);
1960 kv_set_enabled_level(rdev, pi->graphics_boot_level);
1967 static void kv_construct_max_power_limits_table(struct radeon_device *rdev,
1970 struct kv_power_info *pi = kv_get_pi(rdev);
1977 kv_convert_2bit_index_to_voltage(rdev,
1984 static void kv_patch_voltage_values(struct radeon_device *rdev)
1988 &rdev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table;
1990 &rdev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table;
1992 &rdev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table;
1994 &rdev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table;
1999 kv_convert_8bit_index_to_voltage(rdev,
2006 kv_convert_8bit_index_to_voltage(rdev,
2013 kv_convert_8bit_index_to_voltage(rdev,
2020 kv_convert_8bit_index_to_voltage(rdev,
2026 static void kv_construct_boot_state(struct radeon_device *rdev)
2028 struct kv_power_info *pi = kv_get_pi(rdev);
2040 static int kv_force_dpm_highest(struct radeon_device *rdev)
2045 ret = kv_dpm_get_enable_mask(rdev, &enable_mask);
2054 if (rdev->family == CHIP_KABINI || rdev->family == CHIP_MULLINS)
2055 return kv_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_DPM_ForceState, i);
2057 return kv_set_enabled_level(rdev, i);
2060 static int kv_force_dpm_lowest(struct radeon_device *rdev)
2065 ret = kv_dpm_get_enable_mask(rdev, &enable_mask);
2074 if (rdev->family == CHIP_KABINI || rdev->family == CHIP_MULLINS)
2075 return kv_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_DPM_ForceState, i);
2077 return kv_set_enabled_level(rdev, i);
2080 static u8 kv_get_sleep_divider_id_from_clock(struct radeon_device *rdev,
2083 struct kv_power_info *pi = kv_get_pi(rdev);
2104 static int kv_get_high_voltage_limit(struct radeon_device *rdev, int *limit)
2106 struct kv_power_info *pi = kv_get_pi(rdev);
2108 &rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk;
2114 (kv_convert_8bit_index_to_voltage(rdev, table->entries[i].v) <=
2126 (kv_convert_2bit_index_to_voltage(rdev, table->entries[i].vid_2bit) <=
2138 static void kv_apply_state_adjust_rules(struct radeon_device *rdev,
2143 struct kv_power_info *pi = kv_get_pi(rdev);
2149 &rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk;
2152 &rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac;
2155 new_rps->evclk = rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].evclk;
2156 new_rps->ecclk = rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].ecclk;
2182 if (sclk < rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].sclk)
2183 sclk = rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].sclk;
2197 kv_convert_8bit_index_to_voltage(rdev, ps->levels[i].vddc_index))) {
2198 kv_get_high_voltage_limit(rdev, &limit);
2209 kv_convert_8bit_index_to_voltage(rdev, ps->levels[i].vddc_index))) {
2210 kv_get_high_voltage_limit(rdev, &limit);
2231 if (rdev->family == CHIP_KABINI || rdev->family == CHIP_MULLINS) {
2244 pi->video_start || (rdev->pm.dpm.new_active_crtc_count >= 3) ||
2254 static void kv_dpm_power_level_enabled_for_throttle(struct radeon_device *rdev,
2257 struct kv_power_info *pi = kv_get_pi(rdev);
2262 static int kv_calculate_ds_divider(struct radeon_device *rdev)
2264 struct kv_power_info *pi = kv_get_pi(rdev);
2273 kv_get_sleep_divider_id_from_clock(rdev,
2280 static int kv_calculate_nbps_level_settings(struct radeon_device *rdev)
2282 struct kv_power_info *pi = kv_get_pi(rdev);
2286 &rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac;
2292 if (rdev->family == CHIP_KABINI || rdev->family == CHIP_MULLINS) {
2303 (rdev->pm.dpm.new_active_crtc_count >= 3) || pi->video_start);
2334 static int kv_calculate_dpm_settings(struct radeon_device *rdev)
2336 struct kv_power_info *pi = kv_get_pi(rdev);
2348 static void kv_init_graphics_levels(struct radeon_device *rdev)
2350 struct kv_power_info *pi = kv_get_pi(rdev);
2353 &rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk;
2362 kv_convert_8bit_index_to_voltage(rdev, table->entries[i].v)))
2365 kv_set_divider_value(rdev, i, table->entries[i].clk);
2366 vid_2bit = kv_convert_vid7_to_vid2(rdev,
2369 kv_set_vid(rdev, i, vid_2bit);
2370 kv_set_at(rdev, i, pi->at[i]);
2371 kv_dpm_power_level_enabled_for_throttle(rdev, i, true);
2382 kv_convert_2bit_index_to_voltage(rdev, table->entries[i].vid_2bit))
2385 kv_set_divider_value(rdev, i, table->entries[i].sclk_frequency);
2386 kv_set_vid(rdev, i, table->entries[i].vid_2bit);
2387 kv_set_at(rdev, i, pi->at[i]);
2388 kv_dpm_power_level_enabled_for_throttle(rdev, i, true);
2394 kv_dpm_power_level_enable(rdev, i, false);
2397 static void kv_enable_new_levels(struct radeon_device *rdev)
2399 struct kv_power_info *pi = kv_get_pi(rdev);
2404 kv_dpm_power_level_enable(rdev, i, true);
2408 static int kv_set_enabled_level(struct radeon_device *rdev, u32 level)
2412 return kv_send_msg_to_smc_with_parameter(rdev,
2417 static int kv_set_enabled_levels(struct radeon_device *rdev)
2419 struct kv_power_info *pi = kv_get_pi(rdev);
2425 return kv_send_msg_to_smc_with_parameter(rdev,
2430 static void kv_program_nbps_index_settings(struct radeon_device *rdev,
2434 struct kv_power_info *pi = kv_get_pi(rdev);
2437 if (rdev->family == CHIP_KABINI || rdev->family == CHIP_MULLINS)
2452 static int kv_set_thermal_temperature_range(struct radeon_device *rdev,
2474 rdev->pm.dpm.thermal.min_temp = low_temp;
2475 rdev->pm.dpm.thermal.max_temp = high_temp;
2489 static int kv_parse_sys_info_table(struct radeon_device *rdev)
2491 struct kv_power_info *pi = kv_get_pi(rdev);
2492 struct radeon_mode_info *mode_info = &rdev->mode_info;
2539 sumo_construct_sclk_voltage_mapping_table(rdev,
2543 sumo_construct_vid_mapping_table(rdev,
2547 kv_construct_max_power_limits_table(rdev,
2548 &rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac);
2574 static void kv_patch_boot_state(struct radeon_device *rdev,
2577 struct kv_power_info *pi = kv_get_pi(rdev);
2583 static void kv_parse_pplib_non_clock_info(struct radeon_device *rdev,
2603 rdev->pm.dpm.boot_ps = rps;
2604 kv_patch_boot_state(rdev, ps);
2607 rdev->pm.dpm.uvd_ps = rps;
2610 static void kv_parse_pplib_clock_info(struct radeon_device *rdev,
2614 struct kv_power_info *pi = kv_get_pi(rdev);
2632 static int kv_parse_power_table(struct radeon_device *rdev)
2634 struct radeon_mode_info *mode_info = &rdev->mode_info;
2664 rdev->pm.dpm.ps = kcalloc(state_array->ucNumEntries,
2667 if (!rdev->pm.dpm.ps)
2676 if (!rdev->pm.power_state[i].clock_info)
2680 kfree(rdev->pm.dpm.ps);
2683 rdev->pm.dpm.ps[i].ps_priv = ps;
2695 kv_parse_pplib_clock_info(rdev,
2696 &rdev->pm.dpm.ps[i], k,
2700 kv_parse_pplib_non_clock_info(rdev, &rdev->pm.dpm.ps[i],
2705 rdev->pm.dpm.num_ps = state_array->ucNumEntries;
2710 clock_array_index = rdev->pm.dpm.vce_states[i].clk_idx;
2715 rdev->pm.dpm.vce_states[i].sclk = sclk;
2716 rdev->pm.dpm.vce_states[i].mclk = 0;
2722 int kv_dpm_init(struct radeon_device *rdev)
2730 rdev->pm.dpm.priv = pi;
2732 ret = r600_get_platform_caps(rdev);
2736 ret = r600_parse_extended_power_table(rdev);
2746 if (rdev->pdev->subsystem_vendor == 0x1849)
2766 if (rdev->family == CHIP_KABINI || rdev->family == CHIP_MULLINS)
2785 ret = kv_parse_sys_info_table(rdev);
2789 kv_patch_voltage_values(rdev);
2790 kv_construct_boot_state(rdev);
2792 ret = kv_parse_power_table(rdev);
2801 void kv_dpm_debugfs_print_current_performance_level(struct radeon_device *rdev,
2804 struct kv_power_info *pi = kv_get_pi(rdev);
2817 vddc = kv_convert_8bit_index_to_voltage(rdev, (u16)tmp);
2825 u32 kv_dpm_get_current_sclk(struct radeon_device *rdev)
2827 struct kv_power_info *pi = kv_get_pi(rdev);
2841 u32 kv_dpm_get_current_mclk(struct radeon_device *rdev)
2843 struct kv_power_info *pi = kv_get_pi(rdev);
2848 void kv_dpm_print_power_state(struct radeon_device *rdev,
2861 kv_convert_8bit_index_to_voltage(rdev, pl->vddc_index));
2863 r600_dpm_print_ps_status(rdev, rps);
2866 void kv_dpm_fini(struct radeon_device *rdev)
2870 for (i = 0; i < rdev->pm.dpm.num_ps; i++) {
2871 kfree(rdev->pm.dpm.ps[i].ps_priv);
2873 kfree(rdev->pm.dpm.ps);
2874 kfree(rdev->pm.dpm.priv);
2875 r600_free_extended_power_table(rdev);
2878 void kv_dpm_display_configuration_changed(struct radeon_device *rdev)
2883 u32 kv_dpm_get_sclk(struct radeon_device *rdev, bool low)
2885 struct kv_power_info *pi = kv_get_pi(rdev);
2894 u32 kv_dpm_get_mclk(struct radeon_device *rdev, bool low)
2896 struct kv_power_info *pi = kv_get_pi(rdev);