Lines Matching refs:track
47 /* value we track */
118 static void evergreen_cs_track_init(struct evergreen_cs_track *track)
123 track->cb_color_fmask_bo[i] = NULL;
124 track->cb_color_cmask_bo[i] = NULL;
125 track->cb_color_cmask_slice[i] = 0;
126 track->cb_color_fmask_slice[i] = 0;
130 track->cb_color_bo[i] = NULL;
131 track->cb_color_bo_offset[i] = 0xFFFFFFFF;
132 track->cb_color_info[i] = 0;
133 track->cb_color_view[i] = 0xFFFFFFFF;
134 track->cb_color_pitch[i] = 0;
135 track->cb_color_slice[i] = 0xfffffff;
136 track->cb_color_slice_idx[i] = 0;
138 track->cb_target_mask = 0xFFFFFFFF;
139 track->cb_shader_mask = 0xFFFFFFFF;
140 track->cb_dirty = true;
142 track->db_depth_slice = 0xffffffff;
143 track->db_depth_view = 0xFFFFC000;
144 track->db_depth_size = 0xFFFFFFFF;
145 track->db_depth_control = 0xFFFFFFFF;
146 track->db_z_info = 0xFFFFFFFF;
147 track->db_z_read_offset = 0xFFFFFFFF;
148 track->db_z_write_offset = 0xFFFFFFFF;
149 track->db_z_read_bo = NULL;
150 track->db_z_write_bo = NULL;
151 track->db_s_info = 0xFFFFFFFF;
152 track->db_s_read_offset = 0xFFFFFFFF;
153 track->db_s_write_offset = 0xFFFFFFFF;
154 track->db_s_read_bo = NULL;
155 track->db_s_write_bo = NULL;
156 track->db_dirty = true;
157 track->htile_bo = NULL;
158 track->htile_offset = 0xFFFFFFFF;
159 track->htile_surface = 0;
162 track->vgt_strmout_size[i] = 0;
163 track->vgt_strmout_bo[i] = NULL;
164 track->vgt_strmout_bo_offset[i] = 0xFFFFFFFF;
166 track->streamout_dirty = true;
167 track->sx_misc_kill_all_prims = false;
205 struct evergreen_cs_track *track = p->track;
208 palign = MAX(64, track->group_size / surf->bpe);
210 surf->base_align = track->group_size;
227 struct evergreen_cs_track *track = p->track;
230 palign = track->group_size / (8 * surf->bpe * surf->nsamples);
233 surf->base_align = track->group_size;
240 track->group_size, surf->bpe, surf->nsamples);
258 struct evergreen_cs_track *track = p->track;
269 palign = (8 * surf->bankw * track->npipes) * surf->mtilea;
396 struct evergreen_cs_track *track = p->track;
402 mslice = G_028C6C_SLICE_MAX(track->cb_color_view[id]) + 1;
403 pitch = track->cb_color_pitch[id];
404 slice = track->cb_color_slice[id];
407 surf.mode = G_028C70_ARRAY_MODE(track->cb_color_info[id]);
408 surf.format = G_028C70_FORMAT(track->cb_color_info[id]);
409 surf.tsplit = G_028C74_TILE_SPLIT(track->cb_color_attrib[id]);
410 surf.nbanks = G_028C74_NUM_BANKS(track->cb_color_attrib[id]);
411 surf.bankw = G_028C74_BANK_WIDTH(track->cb_color_attrib[id]);
412 surf.bankh = G_028C74_BANK_HEIGHT(track->cb_color_attrib[id]);
413 surf.mtilea = G_028C74_MACRO_TILE_ASPECT(track->cb_color_attrib[id]);
419 id, track->cb_color_info[id]);
431 __func__, __LINE__, id, track->cb_color_pitch[id],
432 track->cb_color_slice[id], track->cb_color_attrib[id],
433 track->cb_color_info[id]);
437 offset = track->cb_color_bo_offset[id] << 8;
445 if (offset > radeon_bo_size(track->cb_color_bo[id])) {
458 bsize = radeon_bo_size(track->cb_color_bo[id]);
459 tmp = track->cb_color_bo_offset[id] << 8;
473 ib[track->cb_color_slice_idx[id]] = slice;
482 track->cb_color_bo_offset[id] << 8, mslice,
483 radeon_bo_size(track->cb_color_bo[id]), slice);
499 struct evergreen_cs_track *track = p->track;
502 if (track->htile_bo == NULL) {
504 __func__, __LINE__, track->db_z_info);
508 if (G_028ABC_LINEAR(track->htile_surface)) {
512 nby = round_up(nby, track->npipes * 8);
518 switch (track->npipes) {
541 __func__, __LINE__, track->npipes);
549 size = roundup(nbx * nby * 4, track->npipes * (2 << 10));
550 size += track->htile_offset;
552 if (size > radeon_bo_size(track->htile_bo)) {
554 __func__, __LINE__, radeon_bo_size(track->htile_bo),
563 struct evergreen_cs_track *track = p->track;
569 mslice = G_028008_SLICE_MAX(track->db_depth_view) + 1;
570 pitch = G_028058_PITCH_TILE_MAX(track->db_depth_size);
571 slice = track->db_depth_slice;
574 surf.mode = G_028040_ARRAY_MODE(track->db_z_info);
575 surf.format = G_028044_FORMAT(track->db_s_info);
576 surf.tsplit = G_028044_TILE_SPLIT(track->db_s_info);
577 surf.nbanks = G_028040_NUM_BANKS(track->db_z_info);
578 surf.bankw = G_028040_BANK_WIDTH(track->db_z_info);
579 surf.bankh = G_028040_BANK_HEIGHT(track->db_z_info);
580 surf.mtilea = G_028040_MACRO_TILE_ASPECT(track->db_z_info);
606 __func__, __LINE__, track->db_depth_size,
607 track->db_depth_slice, track->db_s_info, track->db_z_info);
612 offset = track->db_s_read_offset << 8;
619 if (offset > radeon_bo_size(track->db_s_read_bo)) {
623 (unsigned long)track->db_s_read_offset << 8, mslice,
624 radeon_bo_size(track->db_s_read_bo));
626 __func__, __LINE__, track->db_depth_size,
627 track->db_depth_slice, track->db_s_info, track->db_z_info);
631 offset = track->db_s_write_offset << 8;
638 if (offset > radeon_bo_size(track->db_s_write_bo)) {
642 (unsigned long)track->db_s_write_offset << 8, mslice,
643 radeon_bo_size(track->db_s_write_bo));
648 if (G_028040_TILE_SURFACE_ENABLE(track->db_z_info)) {
660 struct evergreen_cs_track *track = p->track;
666 mslice = G_028008_SLICE_MAX(track->db_depth_view) + 1;
667 pitch = G_028058_PITCH_TILE_MAX(track->db_depth_size);
668 slice = track->db_depth_slice;
671 surf.mode = G_028040_ARRAY_MODE(track->db_z_info);
672 surf.format = G_028040_FORMAT(track->db_z_info);
673 surf.tsplit = G_028040_TILE_SPLIT(track->db_z_info);
674 surf.nbanks = G_028040_NUM_BANKS(track->db_z_info);
675 surf.bankw = G_028040_BANK_WIDTH(track->db_z_info);
676 surf.bankh = G_028040_BANK_HEIGHT(track->db_z_info);
677 surf.mtilea = G_028040_MACRO_TILE_ASPECT(track->db_z_info);
697 __func__, __LINE__, track->db_depth_size,
698 track->db_depth_slice, track->db_z_info);
705 __func__, __LINE__, track->db_depth_size,
706 track->db_depth_slice, track->db_z_info);
710 offset = track->db_z_read_offset << 8;
717 if (offset > radeon_bo_size(track->db_z_read_bo)) {
721 (unsigned long)track->db_z_read_offset << 8, mslice,
722 radeon_bo_size(track->db_z_read_bo));
726 offset = track->db_z_write_offset << 8;
733 if (offset > radeon_bo_size(track->db_z_write_bo)) {
737 (unsigned long)track->db_z_write_offset << 8, mslice,
738 radeon_bo_size(track->db_z_write_bo));
743 if (G_028040_TILE_SURFACE_ENABLE(track->db_z_info)) {
934 struct evergreen_cs_track *track = p->track;
940 if (track->streamout_dirty && track->vgt_strmout_config) {
942 if (track->vgt_strmout_config & (1 << i)) {
943 buffer_mask |= (track->vgt_strmout_buffer_config >> (i * 4)) & 0xf;
949 if (track->vgt_strmout_bo[i]) {
950 u64 offset = (u64)track->vgt_strmout_bo_offset[i] +
951 (u64)track->vgt_strmout_size[i];
952 if (offset > radeon_bo_size(track->vgt_strmout_bo[i])) {
955 radeon_bo_size(track->vgt_strmout_bo[i]));
964 track->streamout_dirty = false;
967 if (track->sx_misc_kill_all_prims)
972 if (track->cb_dirty) {
973 tmp = track->cb_target_mask;
975 u32 format = G_028C70_FORMAT(track->cb_color_info[i]);
980 if (track->cb_color_bo[i] == NULL) {
982 __func__, __LINE__, track->cb_target_mask, track->cb_shader_mask, i);
992 track->cb_dirty = false;
995 if (track->db_dirty) {
997 if (G_028044_FORMAT(track->db_s_info) != V_028044_STENCIL_INVALID &&
998 G_028800_STENCIL_ENABLE(track->db_depth_control)) {
1004 if (G_028040_FORMAT(track->db_z_info) != V_028040_Z_INVALID &&
1005 G_028800_Z_ENABLE(track->db_depth_control)) {
1010 track->db_dirty = false;
1096 struct evergreen_cs_track *track = (struct evergreen_cs_track *)p->track;
1152 track->db_depth_control = radeon_get_ib_value(p, idx);
1153 track->db_dirty = true;
1170 track->db_z_info = radeon_get_ib_value(p, idx);
1179 track->db_z_info &= ~Z_ARRAY_MODE(0xf);
1181 track->db_z_info |= Z_ARRAY_MODE(evergreen_cs_get_aray_mode(reloc->tiling_flags));
1188 ib[idx] |= DB_NUM_BANKS(evergreen_cs_get_num_banks(track->nbanks));
1195 track->db_dirty = true;
1198 track->db_s_info = radeon_get_ib_value(p, idx);
1199 track->db_dirty = true;
1202 track->db_depth_view = radeon_get_ib_value(p, idx);
1203 track->db_dirty = true;
1206 track->db_depth_size = radeon_get_ib_value(p, idx);
1207 track->db_dirty = true;
1210 track->db_depth_slice = radeon_get_ib_value(p, idx);
1211 track->db_dirty = true;
1220 track->db_z_read_offset = radeon_get_ib_value(p, idx);
1222 track->db_z_read_bo = reloc->robj;
1223 track->db_dirty = true;
1232 track->db_z_write_offset = radeon_get_ib_value(p, idx);
1234 track->db_z_write_bo = reloc->robj;
1235 track->db_dirty = true;
1244 track->db_s_read_offset = radeon_get_ib_value(p, idx);
1246 track->db_s_read_bo = reloc->robj;
1247 track->db_dirty = true;
1256 track->db_s_write_offset = radeon_get_ib_value(p, idx);
1258 track->db_s_write_bo = reloc->robj;
1259 track->db_dirty = true;
1262 track->vgt_strmout_config = radeon_get_ib_value(p, idx);
1263 track->streamout_dirty = true;
1266 track->vgt_strmout_buffer_config = radeon_get_ib_value(p, idx);
1267 track->streamout_dirty = true;
1280 track->vgt_strmout_bo_offset[tmp] = radeon_get_ib_value(p, idx) << 8;
1282 track->vgt_strmout_bo[tmp] = reloc->robj;
1283 track->streamout_dirty = true;
1291 track->vgt_strmout_size[tmp] = radeon_get_ib_value(p, idx) * 4;
1292 track->streamout_dirty = true;
1304 track->cb_target_mask = radeon_get_ib_value(p, idx);
1305 track->cb_dirty = true;
1308 track->cb_shader_mask = radeon_get_ib_value(p, idx);
1309 track->cb_dirty = true;
1318 track->nsamples = 1 << tmp;
1327 track->nsamples = 1 << tmp;
1338 track->cb_color_view[tmp] = radeon_get_ib_value(p, idx);
1339 track->cb_dirty = true;
1346 track->cb_color_view[tmp] = radeon_get_ib_value(p, idx);
1347 track->cb_dirty = true;
1358 track->cb_color_info[tmp] = radeon_get_ib_value(p, idx);
1367 track->cb_color_info[tmp] |= CB_ARRAY_MODE(evergreen_cs_get_aray_mode(reloc->tiling_flags));
1369 track->cb_dirty = true;
1376 track->cb_color_info[tmp] = radeon_get_ib_value(p, idx);
1385 track->cb_color_info[tmp] |= CB_ARRAY_MODE(evergreen_cs_get_aray_mode(reloc->tiling_flags));
1387 track->cb_dirty = true;
1398 track->cb_color_pitch[tmp] = radeon_get_ib_value(p, idx);
1399 track->cb_dirty = true;
1406 track->cb_color_pitch[tmp] = radeon_get_ib_value(p, idx);
1407 track->cb_dirty = true;
1418 track->cb_color_slice[tmp] = radeon_get_ib_value(p, idx);
1419 track->cb_color_slice_idx[tmp] = idx;
1420 track->cb_dirty = true;
1427 track->cb_color_slice[tmp] = radeon_get_ib_value(p, idx);
1428 track->cb_color_slice_idx[tmp] = idx;
1429 track->cb_dirty = true;
1452 ib[idx] |= CB_NUM_BANKS(evergreen_cs_get_num_banks(track->nbanks));
1460 track->cb_color_attrib[tmp] = ib[idx];
1461 track->cb_dirty = true;
1480 ib[idx] |= CB_NUM_BANKS(evergreen_cs_get_num_banks(track->nbanks));
1488 track->cb_color_attrib[tmp] = ib[idx];
1489 track->cb_dirty = true;
1506 track->cb_color_fmask_bo[tmp] = reloc->robj;
1523 track->cb_color_cmask_bo[tmp] = reloc->robj;
1534 track->cb_color_fmask_slice[tmp] = radeon_get_ib_value(p, idx);
1545 track->cb_color_cmask_slice[tmp] = radeon_get_ib_value(p, idx);
1562 track->cb_color_bo_offset[tmp] = radeon_get_ib_value(p, idx);
1564 track->cb_color_bo[tmp] = reloc->robj;
1565 track->cb_dirty = true;
1578 track->cb_color_bo_offset[tmp] = radeon_get_ib_value(p, idx);
1580 track->cb_color_bo[tmp] = reloc->robj;
1581 track->cb_dirty = true;
1590 track->htile_offset = radeon_get_ib_value(p, idx);
1592 track->htile_bo = reloc->robj;
1593 track->db_dirty = true;
1597 track->htile_surface = radeon_get_ib_value(p, idx);
1600 track->db_dirty = true;
1739 track->sx_misc_kill_all_prims = (radeon_get_ib_value(p, idx) & 0x1) != 0;
1758 struct evergreen_cs_track *track = p->track;
1766 if (!(track->reg_safe_bm[i] & m))
1776 struct evergreen_cs_track *track;
1784 track = (struct evergreen_cs_track *)p->track;
2023 track->indirect_draw_buffer_size = radeon_bo_size(reloc->robj);
2045 if (idx_value + size > track->indirect_draw_buffer_size) {
2047 idx_value, size, track->indirect_draw_buffer_size);
2374 TEX_NUM_BANKS(evergreen_cs_get_num_banks(track->nbanks));
2675 struct evergreen_cs_track *track;
2679 if (p->track == NULL) {
2681 track = kzalloc(sizeof(*track), GFP_KERNEL);
2682 if (track == NULL)
2684 evergreen_cs_track_init(track);
2687 track->reg_safe_bm = cayman_reg_safe_bm;
2690 track->reg_safe_bm = evergreen_reg_safe_bm;
2696 track->npipes = 1;
2700 track->npipes = 2;
2703 track->npipes = 4;
2706 track->npipes = 8;
2712 track->nbanks = 4;
2716 track->nbanks = 8;
2719 track->nbanks = 16;
2725 track->group_size = 256;
2729 track->group_size = 512;
2735 track->row_size = 1;
2739 track->row_size = 2;
2742 track->row_size = 4;
2746 p->track = track;
2751 kfree(p->track);
2752 p->track = NULL;
2767 kfree(p->track);
2768 p->track = NULL;
2772 kfree(p->track);
2773 p->track = NULL;
2783 kfree(p->track);
2784 p->track = NULL;