Lines Matching defs:tmp
452 unsigned long tmp, nby, bsize, size, min = 0;
459 tmp = track->cb_color_bo_offset[id] << 8;
462 if ((tmp + size * mslice) <= bsize) {
471 tmp += surf.layer_size * mslice;
472 if (tmp <= bsize) {
935 unsigned tmp, i;
973 tmp = track->cb_target_mask;
978 (tmp >> (i * 4)) & 0xF) {
1098 u32 tmp, *ib;
1132 /*tmp =radeon_get_ib_value(p, idx);
1279 tmp = (reg - VGT_STRMOUT_BUFFER_BASE_0) / 16;
1280 track->vgt_strmout_bo_offset[tmp] = radeon_get_ib_value(p, idx) << 8;
1282 track->vgt_strmout_bo[tmp] = reloc->robj;
1289 tmp = (reg - VGT_STRMOUT_BUFFER_SIZE_0) / 16;
1291 track->vgt_strmout_size[tmp] = radeon_get_ib_value(p, idx) * 4;
1317 tmp = radeon_get_ib_value(p, idx) & MSAA_NUM_SAMPLES_MASK;
1318 track->nsamples = 1 << tmp;
1326 tmp = radeon_get_ib_value(p, idx) & CAYMAN_MSAA_NUM_SAMPLES_MASK;
1327 track->nsamples = 1 << tmp;
1337 tmp = (reg - CB_COLOR0_VIEW) / 0x3c;
1338 track->cb_color_view[tmp] = radeon_get_ib_value(p, idx);
1345 tmp = ((reg - CB_COLOR8_VIEW) / 0x1c) + 8;
1346 track->cb_color_view[tmp] = radeon_get_ib_value(p, idx);
1357 tmp = (reg - CB_COLOR0_INFO) / 0x3c;
1358 track->cb_color_info[tmp] = radeon_get_ib_value(p, idx);
1367 track->cb_color_info[tmp] |= CB_ARRAY_MODE(evergreen_cs_get_aray_mode(reloc->tiling_flags));
1375 tmp = ((reg - CB_COLOR8_INFO) / 0x1c) + 8;
1376 track->cb_color_info[tmp] = radeon_get_ib_value(p, idx);
1385 track->cb_color_info[tmp] |= CB_ARRAY_MODE(evergreen_cs_get_aray_mode(reloc->tiling_flags));
1397 tmp = (reg - CB_COLOR0_PITCH) / 0x3c;
1398 track->cb_color_pitch[tmp] = radeon_get_ib_value(p, idx);
1405 tmp = ((reg - CB_COLOR8_PITCH) / 0x1c) + 8;
1406 track->cb_color_pitch[tmp] = radeon_get_ib_value(p, idx);
1417 tmp = (reg - CB_COLOR0_SLICE) / 0x3c;
1418 track->cb_color_slice[tmp] = radeon_get_ib_value(p, idx);
1419 track->cb_color_slice_idx[tmp] = idx;
1426 tmp = ((reg - CB_COLOR8_SLICE) / 0x1c) + 8;
1427 track->cb_color_slice[tmp] = radeon_get_ib_value(p, idx);
1428 track->cb_color_slice_idx[tmp] = idx;
1459 tmp = ((reg - CB_COLOR0_ATTRIB) / 0x3c);
1460 track->cb_color_attrib[tmp] = ib[idx];
1487 tmp = ((reg - CB_COLOR8_ATTRIB) / 0x1c) + 8;
1488 track->cb_color_attrib[tmp] = ib[idx];
1499 tmp = (reg - CB_COLOR0_FMASK) / 0x3c;
1506 track->cb_color_fmask_bo[tmp] = reloc->robj;
1516 tmp = (reg - CB_COLOR0_CMASK) / 0x3c;
1523 track->cb_color_cmask_bo[tmp] = reloc->robj;
1533 tmp = (reg - CB_COLOR0_FMASK_SLICE) / 0x3c;
1534 track->cb_color_fmask_slice[tmp] = radeon_get_ib_value(p, idx);
1544 tmp = (reg - CB_COLOR0_CMASK_SLICE) / 0x3c;
1545 track->cb_color_cmask_slice[tmp] = radeon_get_ib_value(p, idx);
1561 tmp = (reg - CB_COLOR0_BASE) / 0x3c;
1562 track->cb_color_bo_offset[tmp] = radeon_get_ib_value(p, idx);
1564 track->cb_color_bo[tmp] = reloc->robj;
1577 tmp = ((reg - CB_COLOR8_BASE) / 0x1c) + 8;
1578 track->cb_color_bo_offset[tmp] = radeon_get_ib_value(p, idx);
1580 track->cb_color_bo[tmp] = reloc->robj;
1793 int tmp;
1801 tmp = radeon_get_ib_value(p, idx + 1);
1802 pred_op = (tmp >> 16) & 0x7;
1821 ((u64)(tmp & 0xff) << 32);
1824 ib[idx + 1] = (tmp & 0xffffff00) | (upper_32_bits(offset) & 0xff);
2115 u64 offset, tmp;
2155 tmp = radeon_get_ib_value(p, idx) +
2158 offset = reloc->gpu_offset + tmp;
2160 if ((tmp + size) > radeon_bo_size(reloc->robj)) {
2162 tmp + size, radeon_bo_size(reloc->robj));
2193 tmp = radeon_get_ib_value(p, idx+2) +
2196 offset = reloc->gpu_offset + tmp;
2198 if ((tmp + size) > radeon_bo_size(reloc->robj)) {
2200 tmp + size, radeon_bo_size(reloc->robj));
2676 u32 tmp;
2686 tmp = p->rdev->config.cayman.tile_config;
2689 tmp = p->rdev->config.evergreen.tile_config;
2694 switch (tmp & 0xf) {
2710 switch ((tmp & 0xf0) >> 4) {
2723 switch ((tmp & 0xf00) >> 8) {
2733 switch ((tmp & 0xf000) >> 12) {