Lines Matching defs:reloc
1058 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1097 struct radeon_bo_list *reloc;
1143 r = radeon_cs_packet_next_reloc(p, &reloc, 0);
1149 ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff);
1172 r = radeon_cs_packet_next_reloc(p, &reloc, 0);
1180 ib[idx] |= Z_ARRAY_MODE(evergreen_cs_get_aray_mode(reloc->tiling_flags));
1181 track->db_z_info |= Z_ARRAY_MODE(evergreen_cs_get_aray_mode(reloc->tiling_flags));
1182 if (reloc->tiling_flags & RADEON_TILING_MACRO) {
1185 evergreen_tiling_fields(reloc->tiling_flags,
1214 r = radeon_cs_packet_next_reloc(p, &reloc, 0);
1221 ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff);
1222 track->db_z_read_bo = reloc->robj;
1226 r = radeon_cs_packet_next_reloc(p, &reloc, 0);
1233 ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff);
1234 track->db_z_write_bo = reloc->robj;
1238 r = radeon_cs_packet_next_reloc(p, &reloc, 0);
1245 ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff);
1246 track->db_s_read_bo = reloc->robj;
1250 r = radeon_cs_packet_next_reloc(p, &reloc, 0);
1257 ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff);
1258 track->db_s_write_bo = reloc->robj;
1273 r = radeon_cs_packet_next_reloc(p, &reloc, 0);
1281 ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff);
1282 track->vgt_strmout_bo[tmp] = reloc->robj;
1295 r = radeon_cs_packet_next_reloc(p, &reloc, 0);
1297 dev_warn(p->dev, "missing reloc for CP_COHER_BASE "
1301 ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff);
1360 r = radeon_cs_packet_next_reloc(p, &reloc, 0);
1366 ib[idx] |= CB_ARRAY_MODE(evergreen_cs_get_aray_mode(reloc->tiling_flags));
1367 track->cb_color_info[tmp] |= CB_ARRAY_MODE(evergreen_cs_get_aray_mode(reloc->tiling_flags));
1378 r = radeon_cs_packet_next_reloc(p, &reloc, 0);
1384 ib[idx] |= CB_ARRAY_MODE(evergreen_cs_get_aray_mode(reloc->tiling_flags));
1385 track->cb_color_info[tmp] |= CB_ARRAY_MODE(evergreen_cs_get_aray_mode(reloc->tiling_flags));
1439 r = radeon_cs_packet_next_reloc(p, &reloc, 0);
1446 if (reloc->tiling_flags & RADEON_TILING_MACRO) {
1449 evergreen_tiling_fields(reloc->tiling_flags,
1467 r = radeon_cs_packet_next_reloc(p, &reloc, 0);
1474 if (reloc->tiling_flags & RADEON_TILING_MACRO) {
1477 evergreen_tiling_fields(reloc->tiling_flags,
1500 r = radeon_cs_packet_next_reloc(p, &reloc, 0);
1505 ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff);
1506 track->cb_color_fmask_bo[tmp] = reloc->robj;
1517 r = radeon_cs_packet_next_reloc(p, &reloc, 0);
1522 ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff);
1523 track->cb_color_cmask_bo[tmp] = reloc->robj;
1555 r = radeon_cs_packet_next_reloc(p, &reloc, 0);
1563 ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff);
1564 track->cb_color_bo[tmp] = reloc->robj;
1571 r = radeon_cs_packet_next_reloc(p, &reloc, 0);
1579 ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff);
1580 track->cb_color_bo[tmp] = reloc->robj;
1584 r = radeon_cs_packet_next_reloc(p, &reloc, 0);
1591 ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff);
1592 track->htile_bo = reloc->robj;
1702 r = radeon_cs_packet_next_reloc(p, &reloc, 0);
1708 ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff);
1716 r = radeon_cs_packet_next_reloc(p, &reloc, 0);
1722 ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff);
1730 r = radeon_cs_packet_next_reloc(p, &reloc, 0);
1736 ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff);
1775 struct radeon_bo_list *reloc;
1813 r = radeon_cs_packet_next_reloc(p, &reloc, 0);
1819 offset = reloc->gpu_offset +
1859 r = radeon_cs_packet_next_reloc(p, &reloc, 0);
1865 offset = reloc->gpu_offset +
1894 r = radeon_cs_packet_next_reloc(p, &reloc, 0);
1900 offset = reloc->gpu_offset +
1922 r = radeon_cs_packet_next_reloc(p, &reloc, 0);
1928 offset = reloc->gpu_offset +
2017 r = radeon_cs_packet_next_reloc(p, &reloc, 0);
2023 track->indirect_draw_buffer_size = radeon_bo_size(reloc->robj);
2025 ib[idx+1] = reloc->gpu_offset;
2026 ib[idx+2] = upper_32_bits(reloc->gpu_offset) & 0xff;
2074 r = radeon_cs_packet_next_reloc(p, &reloc, 0);
2079 ib[idx+0] = idx_value + (u32)(reloc->gpu_offset & 0xffffffff);
2095 r = radeon_cs_packet_next_reloc(p, &reloc, 0);
2101 offset = reloc->gpu_offset +
2149 r = radeon_cs_packet_next_reloc(p, &reloc, 0);
2158 offset = reloc->gpu_offset + tmp;
2160 if ((tmp + size) > radeon_bo_size(reloc->robj)) {
2162 tmp + size, radeon_bo_size(reloc->robj));
2187 r = radeon_cs_packet_next_reloc(p, &reloc, 0);
2196 offset = reloc->gpu_offset + tmp;
2198 if ((tmp + size) > radeon_bo_size(reloc->robj)) {
2200 tmp + size, radeon_bo_size(reloc->robj));
2227 r = radeon_cs_packet_next_reloc(p, &reloc, 0);
2232 ib[idx+2] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff);
2243 r = radeon_cs_packet_next_reloc(p, &reloc, 0);
2248 offset = reloc->gpu_offset +
2264 r = radeon_cs_packet_next_reloc(p, &reloc, 0);
2270 offset = reloc->gpu_offset +
2286 r = radeon_cs_packet_next_reloc(p, &reloc, 0);
2292 offset = reloc->gpu_offset +
2355 r = radeon_cs_packet_next_reloc(p, &reloc, 0);
2362 TEX_ARRAY_MODE(evergreen_cs_get_aray_mode(reloc->tiling_flags));
2363 if (reloc->tiling_flags & RADEON_TILING_MACRO) {
2366 evergreen_tiling_fields(reloc->tiling_flags,
2377 texture = reloc->robj;
2378 toffset = (u32)((reloc->gpu_offset >> 8) & 0xffffffff);
2392 r = radeon_cs_packet_next_reloc(p, &reloc, 0);
2397 moffset = (u32)((reloc->gpu_offset >> 8) & 0xffffffff);
2398 mipmap = reloc->robj;
2411 r = radeon_cs_packet_next_reloc(p, &reloc, 0);
2418 if (p->rdev && (size + offset) > radeon_bo_size(reloc->robj)) {
2421 ib[idx+1+(i*8)+1] = radeon_bo_size(reloc->robj) - offset;
2424 offset64 = reloc->gpu_offset + offset;
2493 r = radeon_cs_packet_next_reloc(p, &reloc, 0);
2495 DRM_ERROR("bad STRMOUT_BUFFER_UPDATE (missing dst reloc)\n");
2500 if ((offset + 4) > radeon_bo_size(reloc->robj)) {
2502 offset + 4, radeon_bo_size(reloc->robj));
2505 offset += reloc->gpu_offset;
2512 r = radeon_cs_packet_next_reloc(p, &reloc, 0);
2514 DRM_ERROR("bad STRMOUT_BUFFER_UPDATE (missing src reloc)\n");
2519 if ((offset + 4) > radeon_bo_size(reloc->robj)) {
2521 offset + 4, radeon_bo_size(reloc->robj));
2524 offset += reloc->gpu_offset;
2537 r = radeon_cs_packet_next_reloc(p, &reloc, 0);
2539 DRM_ERROR("bad MEM_WRITE (missing reloc)\n");
2548 if ((offset + 8) > radeon_bo_size(reloc->robj)) {
2550 offset + 8, radeon_bo_size(reloc->robj));
2553 offset += reloc->gpu_offset;
2566 r = radeon_cs_packet_next_reloc(p, &reloc, 0);
2568 DRM_ERROR("bad COPY_DW (missing src reloc)\n");
2573 if ((offset + 4) > radeon_bo_size(reloc->robj)) {
2575 offset + 4, radeon_bo_size(reloc->robj));
2578 offset += reloc->gpu_offset;
2593 r = radeon_cs_packet_next_reloc(p, &reloc, 0);
2595 DRM_ERROR("bad COPY_DW (missing dst reloc)\n");
2600 if ((offset + 4) > radeon_bo_size(reloc->robj)) {
2602 offset + 4, radeon_bo_size(reloc->robj));
2605 offset += reloc->gpu_offset;
2643 r = radeon_cs_packet_next_reloc(p, &reloc, 0);
2645 DRM_ERROR("bad SET_APPEND_CNT (missing reloc)\n");
2654 offset += reloc->gpu_offset;
2793 * the GPU addresses based on the reloc information and