Lines Matching defs:rdev
49 u32 eg_cg_rreg(struct radeon_device *rdev, u32 reg)
54 spin_lock_irqsave(&rdev->cg_idx_lock, flags);
57 spin_unlock_irqrestore(&rdev->cg_idx_lock, flags);
61 void eg_cg_wreg(struct radeon_device *rdev, u32 reg, u32 v)
65 spin_lock_irqsave(&rdev->cg_idx_lock, flags);
68 spin_unlock_irqrestore(&rdev->cg_idx_lock, flags);
71 u32 eg_pif_phy0_rreg(struct radeon_device *rdev, u32 reg)
76 spin_lock_irqsave(&rdev->pif_idx_lock, flags);
79 spin_unlock_irqrestore(&rdev->pif_idx_lock, flags);
83 void eg_pif_phy0_wreg(struct radeon_device *rdev, u32 reg, u32 v)
87 spin_lock_irqsave(&rdev->pif_idx_lock, flags);
90 spin_unlock_irqrestore(&rdev->pif_idx_lock, flags);
93 u32 eg_pif_phy1_rreg(struct radeon_device *rdev, u32 reg)
98 spin_lock_irqsave(&rdev->pif_idx_lock, flags);
101 spin_unlock_irqrestore(&rdev->pif_idx_lock, flags);
105 void eg_pif_phy1_wreg(struct radeon_device *rdev, u32 reg, u32 v)
109 spin_lock_irqsave(&rdev->pif_idx_lock, flags);
112 spin_unlock_irqrestore(&rdev->pif_idx_lock, flags);
212 static void evergreen_gpu_init(struct radeon_device *rdev);
213 void evergreen_fini(struct radeon_device *rdev);
214 void evergreen_pcie_gen2_enable(struct radeon_device *rdev);
215 void evergreen_program_aspm(struct radeon_device *rdev);
216 extern void cayman_cp_int_cntl_setup(struct radeon_device *rdev,
218 extern void cayman_vm_decode_fault(struct radeon_device *rdev,
220 void cik_init_cp_pg_table(struct radeon_device *rdev);
222 extern u32 si_get_csb_size(struct radeon_device *rdev);
223 extern void si_get_csb_buffer(struct radeon_device *rdev, volatile u32 *buffer);
224 extern u32 cik_get_csb_size(struct radeon_device *rdev);
225 extern void cik_get_csb_buffer(struct radeon_device *rdev, volatile u32 *buffer);
226 extern void rv770_set_clk_bypass_mode(struct radeon_device *rdev);
1000 static void evergreen_init_golden_registers(struct radeon_device *rdev)
1002 switch (rdev->family) {
1005 radeon_program_register_sequence(rdev,
1008 radeon_program_register_sequence(rdev,
1011 radeon_program_register_sequence(rdev,
1016 radeon_program_register_sequence(rdev,
1019 radeon_program_register_sequence(rdev,
1022 radeon_program_register_sequence(rdev,
1027 radeon_program_register_sequence(rdev,
1030 radeon_program_register_sequence(rdev,
1033 radeon_program_register_sequence(rdev,
1038 radeon_program_register_sequence(rdev,
1041 radeon_program_register_sequence(rdev,
1044 radeon_program_register_sequence(rdev,
1049 radeon_program_register_sequence(rdev,
1054 radeon_program_register_sequence(rdev,
1059 radeon_program_register_sequence(rdev,
1062 radeon_program_register_sequence(rdev,
1067 radeon_program_register_sequence(rdev,
1072 radeon_program_register_sequence(rdev,
1077 radeon_program_register_sequence(rdev,
1089 * @rdev: radeon_device pointer
1096 int evergreen_get_allowed_info_register(struct radeon_device *rdev,
1145 static int sumo_set_uvd_clock(struct radeon_device *rdev, u32 clock,
1151 r = radeon_atom_get_clock_dividers(rdev, COMPUTE_ENGINE_PLL_PARAM,
1169 int sumo_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk)
1174 r = sumo_set_uvd_clock(rdev, vclk, CG_VCLK_CNTL, CG_VCLK_STATUS);
1180 r = sumo_set_uvd_clock(rdev, dclk, CG_DCLK_CNTL, CG_DCLK_STATUS);
1192 int evergreen_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk)
1212 r = radeon_uvd_calc_upll_dividers(rdev, vclk, dclk, 125000, 250000,
1230 r = radeon_uvd_send_upll_ctlreq(rdev, CG_UPLL_FUNC_CNTL);
1267 r = radeon_uvd_send_upll_ctlreq(rdev, CG_UPLL_FUNC_CNTL);
1281 void evergreen_fix_pci_max_read_req_size(struct radeon_device *rdev)
1286 readrq = pcie_get_readrq(rdev->pdev);
1292 pcie_set_readrq(rdev->pdev, 512);
1298 struct radeon_device *rdev = dev->dev_private;
1351 static bool dce4_is_in_vblank(struct radeon_device *rdev, int crtc)
1359 static bool dce4_is_counter_moving(struct radeon_device *rdev, int crtc)
1375 * @rdev: radeon_device pointer
1380 void dce4_wait_for_vblank(struct radeon_device *rdev, int crtc)
1384 if (crtc >= rdev->num_crtc)
1393 while (dce4_is_in_vblank(rdev, crtc)) {
1395 if (!dce4_is_counter_moving(rdev, crtc))
1400 while (!dce4_is_in_vblank(rdev, crtc)) {
1402 if (!dce4_is_counter_moving(rdev, crtc))
1411 * @rdev: radeon_device pointer
1418 void evergreen_page_flip(struct radeon_device *rdev, int crtc_id, u64 crtc_base,
1421 struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id];
1437 * @rdev: radeon_device pointer
1442 bool evergreen_page_flip_pending(struct radeon_device *rdev, int crtc_id)
1444 struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id];
1452 int evergreen_get_temp(struct radeon_device *rdev)
1457 if (rdev->family == CHIP_JUNIPER) {
1490 int sumo_get_temp(struct radeon_device *rdev)
1501 * @rdev: radeon_device pointer
1507 void sumo_pm_init_profile(struct radeon_device *rdev)
1512 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
1513 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
1514 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0;
1515 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0;
1518 if (rdev->flags & RADEON_IS_MOBILITY)
1519 idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_BATTERY, 0);
1521 idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 0);
1523 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = idx;
1524 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = idx;
1525 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
1526 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
1528 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = idx;
1529 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = idx;
1530 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
1531 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
1533 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = idx;
1534 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = idx;
1535 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
1536 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0;
1538 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = idx;
1539 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = idx;
1540 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
1541 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0;
1544 idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 0);
1545 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = idx;
1546 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = idx;
1547 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0;
1548 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx =
1549 rdev->pm.power_state[idx].num_clock_modes - 1;
1551 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = idx;
1552 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = idx;
1553 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0;
1554 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx =
1555 rdev->pm.power_state[idx].num_clock_modes - 1;
1561 * @rdev: radeon_device pointer
1567 void btc_pm_init_profile(struct radeon_device *rdev)
1572 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
1573 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
1574 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0;
1575 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 2;
1580 if (rdev->flags & RADEON_IS_MOBILITY)
1581 idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_BATTERY, 0);
1583 idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 0);
1585 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = idx;
1586 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = idx;
1587 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
1588 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
1590 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = idx;
1591 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = idx;
1592 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
1593 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 1;
1595 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = idx;
1596 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = idx;
1597 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0;
1598 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 2;
1600 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = idx;
1601 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = idx;
1602 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
1603 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
1605 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = idx;
1606 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = idx;
1607 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
1608 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 1;
1610 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = idx;
1611 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = idx;
1612 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0;
1613 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 2;
1619 * @rdev: radeon_device pointer
1624 void evergreen_pm_misc(struct radeon_device *rdev)
1626 int req_ps_idx = rdev->pm.requested_power_state_index;
1627 int req_cm_idx = rdev->pm.requested_clock_mode_index;
1628 struct radeon_power_state *ps = &rdev->pm.power_state[req_ps_idx];
1635 if (voltage->voltage && (voltage->voltage != rdev->pm.current_vddc)) {
1636 radeon_atom_set_voltage(rdev, voltage->voltage, SET_VOLTAGE_TYPE_ASIC_VDDC);
1637 rdev->pm.current_vddc = voltage->voltage;
1645 if ((rdev->pm.pm_method == PM_METHOD_PROFILE) &&
1646 (rdev->family >= CHIP_BARTS) &&
1647 rdev->pm.active_crtc_count &&
1648 ((rdev->pm.profile_index == PM_PROFILE_MID_MH_IDX) ||
1649 (rdev->pm.profile_index == PM_PROFILE_LOW_MH_IDX)))
1650 voltage = &rdev->pm.power_state[req_ps_idx].
1651 clock_info[rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx].voltage;
1656 if (voltage->vddci && (voltage->vddci != rdev->pm.current_vddci)) {
1657 radeon_atom_set_voltage(rdev, voltage->vddci, SET_VOLTAGE_TYPE_ASIC_VDDCI);
1658 rdev->pm.current_vddci = voltage->vddci;
1667 * @rdev: radeon_device pointer
1671 void evergreen_pm_prepare(struct radeon_device *rdev)
1673 struct drm_device *ddev = rdev->ddev;
1692 * @rdev: radeon_device pointer
1696 void evergreen_pm_finish(struct radeon_device *rdev)
1698 struct drm_device *ddev = rdev->ddev;
1717 * @rdev: radeon_device pointer
1723 bool evergreen_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd)
1734 * @rdev: radeon_device pointer
1739 void evergreen_hpd_set_polarity(struct radeon_device *rdev,
1742 bool connected = evergreen_hpd_sense(rdev, hpd);
1756 * @rdev: radeon_device pointer
1761 void evergreen_hpd_init(struct radeon_device *rdev)
1763 struct drm_device *dev = rdev->ddev;
1789 radeon_hpd_set_polarity(rdev, hpd);
1791 radeon_irq_kms_enable_hpd(rdev, enabled);
1797 * @rdev: radeon_device pointer
1802 void evergreen_hpd_fini(struct radeon_device *rdev)
1804 struct drm_device *dev = rdev->ddev;
1818 radeon_irq_kms_disable_hpd(rdev, disabled);
1823 static u32 evergreen_line_buffer_adjust(struct radeon_device *rdev,
1869 if (ASIC_IS_DCE41(rdev) || ASIC_IS_DCE5(rdev)) {
1872 for (i = 0; i < rdev->usec_timeout; i++) {
1885 if (ASIC_IS_DCE5(rdev))
1891 if (ASIC_IS_DCE5(rdev))
1897 if (ASIC_IS_DCE5(rdev))
1903 if (ASIC_IS_DCE5(rdev))
1914 u32 evergreen_get_number_of_dram_channels(struct radeon_device *rdev)
2152 static void evergreen_program_watermarks(struct radeon_device *rdev,
2177 dram_channels = evergreen_get_number_of_dram_channels(rdev);
2180 if ((rdev->pm.pm_method == PM_METHOD_DPM) && rdev->pm.dpm_enabled) {
2182 radeon_dpm_get_mclk(rdev, false) * 10;
2184 radeon_dpm_get_sclk(rdev, false) * 10;
2186 wm_high.yclk = rdev->pm.current_mclk * 10;
2187 wm_high.sclk = rdev->pm.current_sclk * 10;
2207 if ((rdev->pm.pm_method == PM_METHOD_DPM) && rdev->pm.dpm_enabled) {
2209 radeon_dpm_get_mclk(rdev, true) * 10;
2211 radeon_dpm_get_sclk(rdev, true) * 10;
2213 wm_low.yclk = rdev->pm.current_mclk * 10;
2214 wm_low.sclk = rdev->pm.current_sclk * 10;
2243 (rdev->disp_priority == 2)) {
2250 (rdev->disp_priority == 2)) {
2316 * @rdev: radeon_device pointer
2321 void evergreen_bandwidth_update(struct radeon_device *rdev)
2328 if (!rdev->mode_info.mode_config_initialized)
2331 radeon_update_display_priority(rdev);
2333 for (i = 0; i < rdev->num_crtc; i++) {
2334 if (rdev->mode_info.crtcs[i]->base.enabled)
2337 for (i = 0; i < rdev->num_crtc; i += 2) {
2338 mode0 = &rdev->mode_info.crtcs[i]->base.mode;
2339 mode1 = &rdev->mode_info.crtcs[i+1]->base.mode;
2340 lb_size = evergreen_line_buffer_adjust(rdev, rdev->mode_info.crtcs[i], mode0, mode1);
2341 evergreen_program_watermarks(rdev, rdev->mode_info.crtcs[i], lb_size, num_heads);
2342 lb_size = evergreen_line_buffer_adjust(rdev, rdev->mode_info.crtcs[i+1], mode1, mode0);
2343 evergreen_program_watermarks(rdev, rdev->mode_info.crtcs[i+1], lb_size, num_heads);
2350 * @rdev: radeon_device pointer
2356 int evergreen_mc_wait_for_idle(struct radeon_device *rdev)
2361 for (i = 0; i < rdev->usec_timeout; i++) {
2374 void evergreen_pcie_gart_tlb_flush(struct radeon_device *rdev)
2382 for (i = 0; i < rdev->usec_timeout; i++) {
2397 static int evergreen_pcie_gart_enable(struct radeon_device *rdev)
2402 if (rdev->gart.robj == NULL) {
2403 dev_err(rdev->dev, "No VRAM object for PCIE GART.\n");
2406 r = radeon_gart_table_vram_pin(rdev);
2420 if (rdev->flags & RADEON_IS_IGP) {
2428 if ((rdev->family == CHIP_JUNIPER) ||
2429 (rdev->family == CHIP_CYPRESS) ||
2430 (rdev->family == CHIP_HEMLOCK) ||
2431 (rdev->family == CHIP_BARTS))
2438 WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR, rdev->mc.gtt_start >> 12);
2439 WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR, rdev->mc.gtt_end >> 12);
2440 WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, rdev->gart.table_addr >> 12);
2444 (u32)(rdev->dummy_page.addr >> 12));
2447 evergreen_pcie_gart_tlb_flush(rdev);
2449 (unsigned)(rdev->mc.gtt_size >> 20),
2450 (unsigned long long)rdev->gart.table_addr);
2451 rdev->gart.ready = true;
2455 static void evergreen_pcie_gart_disable(struct radeon_device *rdev)
2477 radeon_gart_table_vram_unpin(rdev);
2480 static void evergreen_pcie_gart_fini(struct radeon_device *rdev)
2482 evergreen_pcie_gart_disable(rdev);
2483 radeon_gart_table_vram_free(rdev);
2484 radeon_gart_fini(rdev);
2488 static void evergreen_agp_enable(struct radeon_device *rdev)
2564 static bool evergreen_is_dp_sst_stream_enabled(struct radeon_device *rdev,
2624 static void evergreen_blank_dp_output(struct radeon_device *rdev,
2664 void evergreen_mc_stop(struct radeon_device *rdev, struct evergreen_mc_save *save)
2670 if (!ASIC_IS_NODCE(rdev)) {
2678 for (i = 0; i < rdev->num_crtc; i++) {
2682 if (ASIC_IS_DCE6(rdev)) {
2685 radeon_wait_for_vblank(rdev, i);
2694 radeon_wait_for_vblank(rdev, i);
2702 frame_count = radeon_get_vblank_counter(rdev, i);
2703 for (j = 0; j < rdev->usec_timeout; j++) {
2704 if (radeon_get_vblank_counter(rdev, i) != frame_count)
2715 if (ASIC_IS_DCE5(rdev) &&
2716 evergreen_is_dp_sst_stream_enabled(rdev, i ,&dig_fe))
2717 evergreen_blank_dp_output(rdev, dig_fe);
2732 radeon_mc_wait_for_idle(rdev);
2746 for (i = 0; i < rdev->num_crtc; i++) {
2762 void evergreen_mc_resume(struct radeon_device *rdev, struct evergreen_mc_save *save)
2768 for (i = 0; i < rdev->num_crtc; i++) {
2770 upper_32_bits(rdev->mc.vram_start));
2772 upper_32_bits(rdev->mc.vram_start));
2774 (u32)rdev->mc.vram_start);
2776 (u32)rdev->mc.vram_start);
2779 if (!ASIC_IS_NODCE(rdev)) {
2780 WREG32(EVERGREEN_VGA_MEMORY_BASE_ADDRESS_HIGH, upper_32_bits(rdev->mc.vram_start));
2781 WREG32(EVERGREEN_VGA_MEMORY_BASE_ADDRESS, (u32)rdev->mc.vram_start);
2785 for (i = 0; i < rdev->num_crtc; i++) {
2802 for (j = 0; j < rdev->usec_timeout; j++) {
2818 for (i = 0; i < rdev->num_crtc; i++) {
2820 if (ASIC_IS_DCE6(rdev)) {
2834 frame_count = radeon_get_vblank_counter(rdev, i);
2835 for (j = 0; j < rdev->usec_timeout; j++) {
2836 if (radeon_get_vblank_counter(rdev, i) != frame_count)
2842 if (!ASIC_IS_NODCE(rdev)) {
2850 void evergreen_mc_program(struct radeon_device *rdev)
2866 evergreen_mc_stop(rdev, &save);
2867 if (evergreen_mc_wait_for_idle(rdev)) {
2868 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
2873 if (rdev->flags & RADEON_IS_AGP) {
2874 if (rdev->mc.vram_start < rdev->mc.gtt_start) {
2877 rdev->mc.vram_start >> 12);
2879 rdev->mc.gtt_end >> 12);
2883 rdev->mc.gtt_start >> 12);
2885 rdev->mc.vram_end >> 12);
2889 rdev->mc.vram_start >> 12);
2891 rdev->mc.vram_end >> 12);
2893 WREG32(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR, rdev->vram_scratch.gpu_addr >> 12);
2895 if ((rdev->family == CHIP_PALM) ||
2896 (rdev->family == CHIP_SUMO) ||
2897 (rdev->family == CHIP_SUMO2)) {
2899 tmp |= ((rdev->mc.vram_end >> 20) & 0xF) << 24;
2900 tmp |= ((rdev->mc.vram_start >> 20) & 0xF) << 20;
2903 tmp = ((rdev->mc.vram_end >> 24) & 0xFFFF) << 16;
2904 tmp |= ((rdev->mc.vram_start >> 24) & 0xFFFF);
2906 WREG32(HDP_NONSURFACE_BASE, (rdev->mc.vram_start >> 8));
2909 if (rdev->flags & RADEON_IS_AGP) {
2910 WREG32(MC_VM_AGP_TOP, rdev->mc.gtt_end >> 16);
2911 WREG32(MC_VM_AGP_BOT, rdev->mc.gtt_start >> 16);
2912 WREG32(MC_VM_AGP_BASE, rdev->mc.agp_base >> 22);
2918 if (evergreen_mc_wait_for_idle(rdev)) {
2919 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
2921 evergreen_mc_resume(rdev, &save);
2924 rv515_vga_render_disable(rdev);
2930 void evergreen_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib)
2932 struct radeon_ring *ring = &rdev->ring[ib->ring];
2945 } else if (rdev->wb.enabled) {
2965 static int evergreen_cp_load_microcode(struct radeon_device *rdev)
2970 if (!rdev->me_fw || !rdev->pfp_fw)
2973 r700_cp_stop(rdev);
2980 fw_data = (const __be32 *)rdev->pfp_fw->data;
2986 fw_data = (const __be32 *)rdev->me_fw->data;
2997 static int evergreen_cp_start(struct radeon_device *rdev)
2999 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
3003 r = radeon_ring_lock(rdev, ring, 7);
3011 radeon_ring_write(ring, rdev->config.evergreen.max_hw_contexts - 1);
3015 radeon_ring_unlock_commit(rdev, ring, false);
3020 r = radeon_ring_lock(rdev, ring, evergreen_default_size + 19);
3058 radeon_ring_unlock_commit(rdev, ring, false);
3063 static int evergreen_cp_resume(struct radeon_device *rdev)
3065 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
3103 ((rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFFFFFFFC));
3104 WREG32(CP_RB_RPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFF);
3105 WREG32(SCRATCH_ADDR, ((rdev->wb.gpu_addr + RADEON_WB_SCRATCH_OFFSET) >> 8) & 0xFFFFFFFF);
3107 if (rdev->wb.enabled)
3120 evergreen_cp_start(rdev);
3122 r = radeon_ring_test(rdev, RADEON_RING_TYPE_GFX_INDEX, ring);
3133 static void evergreen_gpu_init(struct radeon_device *rdev)
3154 switch (rdev->family) {
3157 rdev->config.evergreen.num_ses = 2;
3158 rdev->config.evergreen.max_pipes = 4;
3159 rdev->config.evergreen.max_tile_pipes = 8;
3160 rdev->config.evergreen.max_simds = 10;
3161 rdev->config.evergreen.max_backends = 4 * rdev->config.evergreen.num_ses;
3162 rdev->config.evergreen.max_gprs = 256;
3163 rdev->config.evergreen.max_threads = 248;
3164 rdev->config.evergreen.max_gs_threads = 32;
3165 rdev->config.evergreen.max_stack_entries = 512;
3166 rdev->config.evergreen.sx_num_of_sets = 4;
3167 rdev->config.evergreen.sx_max_export_size = 256;
3168 rdev->config.evergreen.sx_max_export_pos_size = 64;
3169 rdev->config.evergreen.sx_max_export_smx_size = 192;
3170 rdev->config.evergreen.max_hw_contexts = 8;
3171 rdev->config.evergreen.sq_num_cf_insts = 2;
3173 rdev->config.evergreen.sc_prim_fifo_size = 0x100;
3174 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;
3175 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;
3179 rdev->config.evergreen.num_ses = 1;
3180 rdev->config.evergreen.max_pipes = 4;
3181 rdev->config.evergreen.max_tile_pipes = 4;
3182 rdev->config.evergreen.max_simds = 10;
3183 rdev->config.evergreen.max_backends = 4 * rdev->config.evergreen.num_ses;
3184 rdev->config.evergreen.max_gprs = 256;
3185 rdev->config.evergreen.max_threads = 248;
3186 rdev->config.evergreen.max_gs_threads = 32;
3187 rdev->config.evergreen.max_stack_entries = 512;
3188 rdev->config.evergreen.sx_num_of_sets = 4;
3189 rdev->config.evergreen.sx_max_export_size = 256;
3190 rdev->config.evergreen.sx_max_export_pos_size = 64;
3191 rdev->config.evergreen.sx_max_export_smx_size = 192;
3192 rdev->config.evergreen.max_hw_contexts = 8;
3193 rdev->config.evergreen.sq_num_cf_insts = 2;
3195 rdev->config.evergreen.sc_prim_fifo_size = 0x100;
3196 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;
3197 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;
3201 rdev->config.evergreen.num_ses = 1;
3202 rdev->config.evergreen.max_pipes = 4;
3203 rdev->config.evergreen.max_tile_pipes = 4;
3204 rdev->config.evergreen.max_simds = 5;
3205 rdev->config.evergreen.max_backends = 2 * rdev->config.evergreen.num_ses;
3206 rdev->config.evergreen.max_gprs = 256;
3207 rdev->config.evergreen.max_threads = 248;
3208 rdev->config.evergreen.max_gs_threads = 32;
3209 rdev->config.evergreen.max_stack_entries = 256;
3210 rdev->config.evergreen.sx_num_of_sets = 4;
3211 rdev->config.evergreen.sx_max_export_size = 256;
3212 rdev->config.evergreen.sx_max_export_pos_size = 64;
3213 rdev->config.evergreen.sx_max_export_smx_size = 192;
3214 rdev->config.evergreen.max_hw_contexts = 8;
3215 rdev->config.evergreen.sq_num_cf_insts = 2;
3217 rdev->config.evergreen.sc_prim_fifo_size = 0x100;
3218 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;
3219 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;
3224 rdev->config.evergreen.num_ses = 1;
3225 rdev->config.evergreen.max_pipes = 2;
3226 rdev->config.evergreen.max_tile_pipes = 2;
3227 rdev->config.evergreen.max_simds = 2;
3228 rdev->config.evergreen.max_backends = 1 * rdev->config.evergreen.num_ses;
3229 rdev->config.evergreen.max_gprs = 256;
3230 rdev->config.evergreen.max_threads = 192;
3231 rdev->config.evergreen.max_gs_threads = 16;
3232 rdev->config.evergreen.max_stack_entries = 256;
3233 rdev->config.evergreen.sx_num_of_sets = 4;
3234 rdev->config.evergreen.sx_max_export_size = 128;
3235 rdev->config.evergreen.sx_max_export_pos_size = 32;
3236 rdev->config.evergreen.sx_max_export_smx_size = 96;
3237 rdev->config.evergreen.max_hw_contexts = 4;
3238 rdev->config.evergreen.sq_num_cf_insts = 1;
3240 rdev->config.evergreen.sc_prim_fifo_size = 0x40;
3241 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;
3242 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;
3246 rdev->config.evergreen.num_ses = 1;
3247 rdev->config.evergreen.max_pipes = 2;
3248 rdev->config.evergreen.max_tile_pipes = 2;
3249 rdev->config.evergreen.max_simds = 2;
3250 rdev->config.evergreen.max_backends = 1 * rdev->config.evergreen.num_ses;
3251 rdev->config.evergreen.max_gprs = 256;
3252 rdev->config.evergreen.max_threads = 192;
3253 rdev->config.evergreen.max_gs_threads = 16;
3254 rdev->config.evergreen.max_stack_entries = 256;
3255 rdev->config.evergreen.sx_num_of_sets = 4;
3256 rdev->config.evergreen.sx_max_export_size = 128;
3257 rdev->config.evergreen.sx_max_export_pos_size = 32;
3258 rdev->config.evergreen.sx_max_export_smx_size = 96;
3259 rdev->config.evergreen.max_hw_contexts = 4;
3260 rdev->config.evergreen.sq_num_cf_insts = 1;
3262 rdev->config.evergreen.sc_prim_fifo_size = 0x40;
3263 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;
3264 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;
3268 rdev->config.evergreen.num_ses = 1;
3269 rdev->config.evergreen.max_pipes = 4;
3270 rdev->config.evergreen.max_tile_pipes = 4;
3271 if (rdev->pdev->device == 0x9648)
3272 rdev->config.evergreen.max_simds = 3;
3273 else if ((rdev->pdev->device == 0x9647) ||
3274 (rdev->pdev->device == 0x964a))
3275 rdev->config.evergreen.max_simds = 4;
3277 rdev->config.evergreen.max_simds = 5;
3278 rdev->config.evergreen.max_backends = 2 * rdev->config.evergreen.num_ses;
3279 rdev->config.evergreen.max_gprs = 256;
3280 rdev->config.evergreen.max_threads = 248;
3281 rdev->config.evergreen.max_gs_threads = 32;
3282 rdev->config.evergreen.max_stack_entries = 256;
3283 rdev->config.evergreen.sx_num_of_sets = 4;
3284 rdev->config.evergreen.sx_max_export_size = 256;
3285 rdev->config.evergreen.sx_max_export_pos_size = 64;
3286 rdev->config.evergreen.sx_max_export_smx_size = 192;
3287 rdev->config.evergreen.max_hw_contexts = 8;
3288 rdev->config.evergreen.sq_num_cf_insts = 2;
3290 rdev->config.evergreen.sc_prim_fifo_size = 0x40;
3291 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;
3292 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;
3296 rdev->config.evergreen.num_ses = 1;
3297 rdev->config.evergreen.max_pipes = 4;
3298 rdev->config.evergreen.max_tile_pipes = 4;
3299 rdev->config.evergreen.max_simds = 2;
3300 rdev->config.evergreen.max_backends = 1 * rdev->config.evergreen.num_ses;
3301 rdev->config.evergreen.max_gprs = 256;
3302 rdev->config.evergreen.max_threads = 248;
3303 rdev->config.evergreen.max_gs_threads = 32;
3304 rdev->config.evergreen.max_stack_entries = 512;
3305 rdev->config.evergreen.sx_num_of_sets = 4;
3306 rdev->config.evergreen.sx_max_export_size = 256;
3307 rdev->config.evergreen.sx_max_export_pos_size = 64;
3308 rdev->config.evergreen.sx_max_export_smx_size = 192;
3309 rdev->config.evergreen.max_hw_contexts = 4;
3310 rdev->config.evergreen.sq_num_cf_insts = 2;
3312 rdev->config.evergreen.sc_prim_fifo_size = 0x40;
3313 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;
3314 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;
3318 rdev->config.evergreen.num_ses = 2;
3319 rdev->config.evergreen.max_pipes = 4;
3320 rdev->config.evergreen.max_tile_pipes = 8;
3321 rdev->config.evergreen.max_simds = 7;
3322 rdev->config.evergreen.max_backends = 4 * rdev->config.evergreen.num_ses;
3323 rdev->config.evergreen.max_gprs = 256;
3324 rdev->config.evergreen.max_threads = 248;
3325 rdev->config.evergreen.max_gs_threads = 32;
3326 rdev->config.evergreen.max_stack_entries = 512;
3327 rdev->config.evergreen.sx_num_of_sets = 4;
3328 rdev->config.evergreen.sx_max_export_size = 256;
3329 rdev->config.evergreen.sx_max_export_pos_size = 64;
3330 rdev->config.evergreen.sx_max_export_smx_size = 192;
3331 rdev->config.evergreen.max_hw_contexts = 8;
3332 rdev->config.evergreen.sq_num_cf_insts = 2;
3334 rdev->config.evergreen.sc_prim_fifo_size = 0x100;
3335 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;
3336 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;
3340 rdev->config.evergreen.num_ses = 1;
3341 rdev->config.evergreen.max_pipes = 4;
3342 rdev->config.evergreen.max_tile_pipes = 4;
3343 rdev->config.evergreen.max_simds = 6;
3344 rdev->config.evergreen.max_backends = 2 * rdev->config.evergreen.num_ses;
3345 rdev->config.evergreen.max_gprs = 256;
3346 rdev->config.evergreen.max_threads = 248;
3347 rdev->config.evergreen.max_gs_threads = 32;
3348 rdev->config.evergreen.max_stack_entries = 256;
3349 rdev->config.evergreen.sx_num_of_sets = 4;
3350 rdev->config.evergreen.sx_max_export_size = 256;
3351 rdev->config.evergreen.sx_max_export_pos_size = 64;
3352 rdev->config.evergreen.sx_max_export_smx_size = 192;
3353 rdev->config.evergreen.max_hw_contexts = 8;
3354 rdev->config.evergreen.sq_num_cf_insts = 2;
3356 rdev->config.evergreen.sc_prim_fifo_size = 0x100;
3357 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;
3358 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;
3362 rdev->config.evergreen.num_ses = 1;
3363 rdev->config.evergreen.max_pipes = 2;
3364 rdev->config.evergreen.max_tile_pipes = 2;
3365 rdev->config.evergreen.max_simds = 2;
3366 rdev->config.evergreen.max_backends = 1 * rdev->config.evergreen.num_ses;
3367 rdev->config.evergreen.max_gprs = 256;
3368 rdev->config.evergreen.max_threads = 192;
3369 rdev->config.evergreen.max_gs_threads = 16;
3370 rdev->config.evergreen.max_stack_entries = 256;
3371 rdev->config.evergreen.sx_num_of_sets = 4;
3372 rdev->config.evergreen.sx_max_export_size = 128;
3373 rdev->config.evergreen.sx_max_export_pos_size = 32;
3374 rdev->config.evergreen.sx_max_export_smx_size = 96;
3375 rdev->config.evergreen.max_hw_contexts = 4;
3376 rdev->config.evergreen.sq_num_cf_insts = 1;
3378 rdev->config.evergreen.sc_prim_fifo_size = 0x40;
3379 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;
3380 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;
3398 evergreen_fix_pci_max_read_req_size(rdev);
3401 if ((rdev->family == CHIP_PALM) ||
3402 (rdev->family == CHIP_SUMO) ||
3403 (rdev->family == CHIP_SUMO2))
3415 rdev->config.evergreen.tile_config = 0;
3416 switch (rdev->config.evergreen.max_tile_pipes) {
3419 rdev->config.evergreen.tile_config |= (0 << 0);
3422 rdev->config.evergreen.tile_config |= (1 << 0);
3425 rdev->config.evergreen.tile_config |= (2 << 0);
3428 rdev->config.evergreen.tile_config |= (3 << 0);
3432 if (rdev->flags & RADEON_IS_IGP)
3433 rdev->config.evergreen.tile_config |= 1 << 4;
3437 rdev->config.evergreen.tile_config |= 0 << 4;
3440 rdev->config.evergreen.tile_config |= 1 << 4;
3444 rdev->config.evergreen.tile_config |= 2 << 4;
3448 rdev->config.evergreen.tile_config |= 0 << 8;
3449 rdev->config.evergreen.tile_config |=
3452 if ((rdev->family >= CHIP_CEDAR) && (rdev->family <= CHIP_HEMLOCK)) {
3462 for (i = (rdev->config.evergreen.num_ses - 1); i >= 0; i--) {
3475 for (i = 0; i < rdev->config.evergreen.max_backends; i++)
3479 for (i = 0; i < rdev->config.evergreen.max_backends; i++)
3483 for (i = 0; i < rdev->config.evergreen.num_ses; i++) {
3489 simd_disable_bitmap |= 0xffffffff << rdev->config.evergreen.max_simds;
3493 rdev->config.evergreen.active_simds = hweight32(~tmp);
3506 if ((rdev->config.evergreen.max_backends == 1) &&
3507 (rdev->flags & RADEON_IS_IGP)) {
3517 tmp = r6xx_remap_render_backend(rdev, tmp, rdev->config.evergreen.max_backends,
3520 rdev->config.evergreen.backend_map = tmp;
3546 smx_dc_ctl0 |= NUMBER_OF_SETS(rdev->config.evergreen.sx_num_of_sets);
3549 if (rdev->family <= CHIP_SUMO2)
3552 WREG32(SX_EXPORT_BUFFER_SIZES, (COLOR_BUFFER_SIZE((rdev->config.evergreen.sx_max_export_size / 4) - 1) |
3553 POSITION_BUFFER_SIZE((rdev->config.evergreen.sx_max_export_pos_size / 4) - 1) |
3554 SMX_BUFFER_SIZE((rdev->config.evergreen.sx_max_export_smx_size / 4) - 1)));
3556 WREG32(PA_SC_FIFO_SIZE, (SC_PRIM_FIFO_SIZE(rdev->config.evergreen.sc_prim_fifo_size) |
3557 SC_HIZ_TILE_FIFO_SIZE(rdev->config.evergreen.sc_hiz_tile_fifo_size) |
3558 SC_EARLYZ_TILE_FIFO_SIZE(rdev->config.evergreen.sc_earlyz_tile_fifo_size)));
3565 WREG32(SQ_MS_FIFO_SIZES, (CACHE_FIFO_SIZE(16 * rdev->config.evergreen.sq_num_cf_insts) |
3582 switch (rdev->family) {
3597 sq_gpr_resource_mgmt_1 = NUM_PS_GPRS((rdev->config.evergreen.max_gprs - (4 * 2))* 12 / 32);
3598 sq_gpr_resource_mgmt_1 |= NUM_VS_GPRS((rdev->config.evergreen.max_gprs - (4 * 2)) * 6 / 32);
3600 sq_gpr_resource_mgmt_2 = NUM_GS_GPRS((rdev->config.evergreen.max_gprs - (4 * 2)) * 4 / 32);
3601 sq_gpr_resource_mgmt_2 |= NUM_ES_GPRS((rdev->config.evergreen.max_gprs - (4 * 2)) * 4 / 32);
3602 sq_gpr_resource_mgmt_3 = NUM_HS_GPRS((rdev->config.evergreen.max_gprs - (4 * 2)) * 3 / 32);
3603 sq_gpr_resource_mgmt_3 |= NUM_LS_GPRS((rdev->config.evergreen.max_gprs - (4 * 2)) * 3 / 32);
3605 switch (rdev->family) {
3618 sq_thread_resource_mgmt |= NUM_VS_THREADS((((rdev->config.evergreen.max_threads - ps_thread_count) / 6) / 8) * 8);
3619 sq_thread_resource_mgmt |= NUM_GS_THREADS((((rdev->config.evergreen.max_threads - ps_thread_count) / 6) / 8) * 8);
3620 sq_thread_resource_mgmt |= NUM_ES_THREADS((((rdev->config.evergreen.max_threads - ps_thread_count) / 6) / 8) * 8);
3621 sq_thread_resource_mgmt_2 = NUM_HS_THREADS((((rdev->config.evergreen.max_threads - ps_thread_count) / 6) / 8) * 8);
3622 sq_thread_resource_mgmt_2 |= NUM_LS_THREADS((((rdev->config.evergreen.max_threads - ps_thread_count) / 6) / 8) * 8);
3624 sq_stack_resource_mgmt_1 = NUM_PS_STACK_ENTRIES((rdev->config.evergreen.max_stack_entries * 1) / 6);
3625 sq_stack_resource_mgmt_1 |= NUM_VS_STACK_ENTRIES((rdev->config.evergreen.max_stack_entries * 1) / 6);
3626 sq_stack_resource_mgmt_2 = NUM_GS_STACK_ENTRIES((rdev->config.evergreen.max_stack_entries * 1) / 6);
3627 sq_stack_resource_mgmt_2 |= NUM_ES_STACK_ENTRIES((rdev->config.evergreen.max_stack_entries * 1) / 6);
3628 sq_stack_resource_mgmt_3 = NUM_HS_STACK_ENTRIES((rdev->config.evergreen.max_stack_entries * 1) / 6);
3629 sq_stack_resource_mgmt_3 |= NUM_LS_STACK_ENTRIES((rdev->config.evergreen.max_stack_entries * 1) / 6);
3646 switch (rdev->family) {
3710 int evergreen_mc_init(struct radeon_device *rdev)
3716 rdev->mc.vram_is_ddr = true;
3717 if ((rdev->family == CHIP_PALM) ||
3718 (rdev->family == CHIP_SUMO) ||
3719 (rdev->family == CHIP_SUMO2))
3746 rdev->mc.vram_width = numchan * chansize;
3748 rdev->mc.aper_base = pci_resource_start(rdev->pdev, 0);
3749 rdev->mc.aper_size = pci_resource_len(rdev->pdev, 0);
3751 if ((rdev->family == CHIP_PALM) ||
3752 (rdev->family == CHIP_SUMO) ||
3753 (rdev->family == CHIP_SUMO2)) {
3755 rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE);
3756 rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE);
3759 rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE) * 1024ULL * 1024ULL;
3760 rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE) * 1024ULL * 1024ULL;
3762 rdev->mc.visible_vram_size = rdev->mc.aper_size;
3763 r700_vram_gtt_location(rdev, &rdev->mc);
3764 radeon_update_bandwidth_info(rdev);
3769 void evergreen_print_gpu_status_regs(struct radeon_device *rdev)
3771 dev_info(rdev->dev, " GRBM_STATUS = 0x%08X\n",
3773 dev_info(rdev->dev, " GRBM_STATUS_SE0 = 0x%08X\n",
3775 dev_info(rdev->dev, " GRBM_STATUS_SE1 = 0x%08X\n",
3777 dev_info(rdev->dev, " SRBM_STATUS = 0x%08X\n",
3779 dev_info(rdev->dev, " SRBM_STATUS2 = 0x%08X\n",
3781 dev_info(rdev->dev, " R_008674_CP_STALLED_STAT1 = 0x%08X\n",
3783 dev_info(rdev->dev, " R_008678_CP_STALLED_STAT2 = 0x%08X\n",
3785 dev_info(rdev->dev, " R_00867C_CP_BUSY_STAT = 0x%08X\n",
3787 dev_info(rdev->dev, " R_008680_CP_STAT = 0x%08X\n",
3789 dev_info(rdev->dev, " R_00D034_DMA_STATUS_REG = 0x%08X\n",
3791 if (rdev->family >= CHIP_CAYMAN) {
3792 dev_info(rdev->dev, " R_00D834_DMA_STATUS_REG = 0x%08X\n",
3797 bool evergreen_is_display_hung(struct radeon_device *rdev)
3803 for (i = 0; i < rdev->num_crtc; i++) {
3811 for (i = 0; i < rdev->num_crtc; i++) {
3826 u32 evergreen_gpu_check_soft_reset(struct radeon_device *rdev)
3878 if (evergreen_is_display_hung(rdev))
3895 static void evergreen_gpu_soft_reset(struct radeon_device *rdev, u32 reset_mask)
3904 dev_info(rdev->dev, "GPU softreset: 0x%08X\n", reset_mask);
3906 evergreen_print_gpu_status_regs(rdev);
3920 evergreen_mc_stop(rdev, &save);
3921 if (evergreen_mc_wait_for_idle(rdev)) {
3922 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
3967 if (!(rdev->flags & RADEON_IS_IGP)) {
3975 dev_info(rdev->dev, "GRBM_SOFT_RESET=0x%08X\n", tmp);
3989 dev_info(rdev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
4003 evergreen_mc_resume(rdev, &save);
4006 evergreen_print_gpu_status_regs(rdev);
4009 void evergreen_gpu_pci_config_reset(struct radeon_device *rdev)
4014 dev_info(rdev->dev, "GPU pci config reset\n");
4028 r600_rlc_stop(rdev);
4033 rv770_set_clk_bypass_mode(rdev);
4035 pci_clear_master(rdev->pdev);
4037 evergreen_mc_stop(rdev, &save);
4038 if (evergreen_mc_wait_for_idle(rdev)) {
4039 dev_warn(rdev->dev, "Wait for MC idle timed out !\n");
4042 radeon_pci_config_reset(rdev);
4044 for (i = 0; i < rdev->usec_timeout; i++) {
4051 int evergreen_asic_reset(struct radeon_device *rdev, bool hard)
4056 evergreen_gpu_pci_config_reset(rdev);
4060 reset_mask = evergreen_gpu_check_soft_reset(rdev);
4063 r600_set_bios_scratch_engine_hung(rdev, true);
4066 evergreen_gpu_soft_reset(rdev, reset_mask);
4068 reset_mask = evergreen_gpu_check_soft_reset(rdev);
4072 evergreen_gpu_pci_config_reset(rdev);
4074 reset_mask = evergreen_gpu_check_soft_reset(rdev);
4077 r600_set_bios_scratch_engine_hung(rdev, false);
4085 * @rdev: radeon_device pointer
4091 bool evergreen_gfx_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring)
4093 u32 reset_mask = evergreen_gpu_check_soft_reset(rdev);
4098 radeon_ring_lockup_update(rdev, ring);
4101 return radeon_ring_test_lockup(rdev, ring);
4110 void sumo_rlc_fini(struct radeon_device *rdev)
4115 if (rdev->rlc.save_restore_obj) {
4116 r = radeon_bo_reserve(rdev->rlc.save_restore_obj, false);
4118 dev_warn(rdev->dev, "(%d) reserve RLC sr bo failed\n", r);
4119 radeon_bo_unpin(rdev->rlc.save_restore_obj);
4120 radeon_bo_unreserve(rdev->rlc.save_restore_obj);
4122 radeon_bo_unref(&rdev->rlc.save_restore_obj);
4123 rdev->rlc.save_restore_obj = NULL;
4127 if (rdev->rlc.clear_state_obj) {
4128 r = radeon_bo_reserve(rdev->rlc.clear_state_obj, false);
4130 dev_warn(rdev->dev, "(%d) reserve RLC c bo failed\n", r);
4131 radeon_bo_unpin(rdev->rlc.clear_state_obj);
4132 radeon_bo_unreserve(rdev->rlc.clear_state_obj);
4134 radeon_bo_unref(&rdev->rlc.clear_state_obj);
4135 rdev->rlc.clear_state_obj = NULL;
4139 if (rdev->rlc.cp_table_obj) {
4140 r = radeon_bo_reserve(rdev->rlc.cp_table_obj, false);
4142 dev_warn(rdev->dev, "(%d) reserve RLC cp table bo failed\n", r);
4143 radeon_bo_unpin(rdev->rlc.cp_table_obj);
4144 radeon_bo_unreserve(rdev->rlc.cp_table_obj);
4146 radeon_bo_unref(&rdev->rlc.cp_table_obj);
4147 rdev->rlc.cp_table_obj = NULL;
4153 int sumo_rlc_init(struct radeon_device *rdev)
4163 src_ptr = rdev->rlc.reg_list;
4164 dws = rdev->rlc.reg_list_size;
4165 if (rdev->family >= CHIP_BONAIRE) {
4168 cs_data = rdev->rlc.cs_data;
4172 if (rdev->rlc.save_restore_obj == NULL) {
4173 r = radeon_bo_create(rdev, dws * 4, PAGE_SIZE, true,
4175 NULL, &rdev->rlc.save_restore_obj);
4177 dev_warn(rdev->dev, "(%d) create RLC sr bo failed\n", r);
4182 r = radeon_bo_reserve(rdev->rlc.save_restore_obj, false);
4184 sumo_rlc_fini(rdev);
4187 r = radeon_bo_pin(rdev->rlc.save_restore_obj, RADEON_GEM_DOMAIN_VRAM,
4188 &rdev->rlc.save_restore_gpu_addr);
4190 radeon_bo_unreserve(rdev->rlc.save_restore_obj);
4191 dev_warn(rdev->dev, "(%d) pin RLC sr bo failed\n", r);
4192 sumo_rlc_fini(rdev);
4196 r = radeon_bo_kmap(rdev->rlc.save_restore_obj, (void **)&rdev->rlc.sr_ptr);
4198 dev_warn(rdev->dev, "(%d) map RLC sr bo failed\n", r);
4199 sumo_rlc_fini(rdev);
4203 dst_ptr = rdev->rlc.sr_ptr;
4204 if (rdev->family >= CHIP_TAHITI) {
4206 for (i = 0; i < rdev->rlc.reg_list_size; i++)
4226 radeon_bo_kunmap(rdev->rlc.save_restore_obj);
4227 radeon_bo_unreserve(rdev->rlc.save_restore_obj);
4232 if (rdev->family >= CHIP_BONAIRE) {
4233 rdev->rlc.clear_state_size = dws = cik_get_csb_size(rdev);
4234 } else if (rdev->family >= CHIP_TAHITI) {
4235 rdev->rlc.clear_state_size = si_get_csb_size(rdev);
4236 dws = rdev->rlc.clear_state_size + (256 / 4);
4248 rdev->rlc.clear_state_size = dws;
4251 if (rdev->rlc.clear_state_obj == NULL) {
4252 r = radeon_bo_create(rdev, dws * 4, PAGE_SIZE, true,
4254 NULL, &rdev->rlc.clear_state_obj);
4256 dev_warn(rdev->dev, "(%d) create RLC c bo failed\n", r);
4257 sumo_rlc_fini(rdev);
4261 r = radeon_bo_reserve(rdev->rlc.clear_state_obj, false);
4263 sumo_rlc_fini(rdev);
4266 r = radeon_bo_pin(rdev->rlc.clear_state_obj, RADEON_GEM_DOMAIN_VRAM,
4267 &rdev->rlc.clear_state_gpu_addr);
4269 radeon_bo_unreserve(rdev->rlc.clear_state_obj);
4270 dev_warn(rdev->dev, "(%d) pin RLC c bo failed\n", r);
4271 sumo_rlc_fini(rdev);
4275 r = radeon_bo_kmap(rdev->rlc.clear_state_obj, (void **)&rdev->rlc.cs_ptr);
4277 dev_warn(rdev->dev, "(%d) map RLC c bo failed\n", r);
4278 sumo_rlc_fini(rdev);
4282 dst_ptr = rdev->rlc.cs_ptr;
4283 if (rdev->family >= CHIP_BONAIRE) {
4284 cik_get_csb_buffer(rdev, dst_ptr);
4285 } else if (rdev->family >= CHIP_TAHITI) {
4286 reg_list_mc_addr = rdev->rlc.clear_state_gpu_addr + 256;
4289 dst_ptr[2] = cpu_to_le32(rdev->rlc.clear_state_size);
4290 si_get_csb_buffer(rdev, &dst_ptr[(256/4)]);
4293 reg_list_mc_addr = rdev->rlc.clear_state_gpu_addr + (reg_list_blk_index * 4);
4322 radeon_bo_kunmap(rdev->rlc.clear_state_obj);
4323 radeon_bo_unreserve(rdev->rlc.clear_state_obj);
4326 if (rdev->rlc.cp_table_size) {
4327 if (rdev->rlc.cp_table_obj == NULL) {
4328 r = radeon_bo_create(rdev, rdev->rlc.cp_table_size,
4331 NULL, &rdev->rlc.cp_table_obj);
4333 dev_warn(rdev->dev, "(%d) create RLC cp table bo failed\n", r);
4334 sumo_rlc_fini(rdev);
4339 r = radeon_bo_reserve(rdev->rlc.cp_table_obj, false);
4341 dev_warn(rdev->dev, "(%d) reserve RLC cp table bo failed\n", r);
4342 sumo_rlc_fini(rdev);
4345 r = radeon_bo_pin(rdev->rlc.cp_table_obj, RADEON_GEM_DOMAIN_VRAM,
4346 &rdev->rlc.cp_table_gpu_addr);
4348 radeon_bo_unreserve(rdev->rlc.cp_table_obj);
4349 dev_warn(rdev->dev, "(%d) pin RLC cp_table bo failed\n", r);
4350 sumo_rlc_fini(rdev);
4353 r = radeon_bo_kmap(rdev->rlc.cp_table_obj, (void **)&rdev->rlc.cp_table_ptr);
4355 dev_warn(rdev->dev, "(%d) map RLC cp table bo failed\n", r);
4356 sumo_rlc_fini(rdev);
4360 cik_init_cp_pg_table(rdev);
4362 radeon_bo_kunmap(rdev->rlc.cp_table_obj);
4363 radeon_bo_unreserve(rdev->rlc.cp_table_obj);
4370 static void evergreen_rlc_start(struct radeon_device *rdev)
4374 if (rdev->flags & RADEON_IS_IGP) {
4381 int evergreen_rlc_resume(struct radeon_device *rdev)
4386 if (!rdev->rlc_fw)
4389 r600_rlc_stop(rdev);
4393 if (rdev->flags & RADEON_IS_IGP) {
4394 if (rdev->family == CHIP_ARUBA) {
4396 3 | (3 << (16 * rdev->config.cayman.max_shader_engines));
4399 tmp |= 0xffffffff << rdev->config.cayman.max_simds_per_se;
4401 if (tmp == rdev->config.cayman.max_simds_per_se) {
4412 WREG32(TN_RLC_SAVE_AND_RESTORE_BASE, rdev->rlc.save_restore_gpu_addr >> 8);
4413 WREG32(TN_RLC_CLEAR_STATE_RESTORE_BASE, rdev->rlc.clear_state_gpu_addr >> 8);
4424 fw_data = (const __be32 *)rdev->rlc_fw->data;
4425 if (rdev->family >= CHIP_ARUBA) {
4430 } else if (rdev->family >= CHIP_CAYMAN) {
4443 evergreen_rlc_start(rdev);
4450 u32 evergreen_get_vblank_counter(struct radeon_device *rdev, int crtc)
4452 if (crtc >= rdev->num_crtc)
4458 void evergreen_disable_interrupt_state(struct radeon_device *rdev)
4463 if (rdev->family >= CHIP_CAYMAN) {
4464 cayman_cp_int_cntl_setup(rdev, 0,
4466 cayman_cp_int_cntl_setup(rdev, 1, 0);
4467 cayman_cp_int_cntl_setup(rdev, 2, 0);
4476 for (i = 0; i < rdev->num_crtc; i++)
4478 for (i = 0; i < rdev->num_crtc; i++)
4482 if (!ASIC_IS_DCE5(rdev))
4491 int evergreen_irq_set(struct radeon_device *rdev)
4500 if (!rdev->irq.installed) {
4505 if (!rdev->ih.enabled) {
4506 r600_disable_interrupts(rdev);
4508 evergreen_disable_interrupt_state(rdev);
4512 if (rdev->family == CHIP_ARUBA)
4521 if (rdev->family >= CHIP_CAYMAN) {
4523 if (atomic_read(&rdev->irq.ring_int[RADEON_RING_TYPE_GFX_INDEX])) {
4527 if (atomic_read(&rdev->irq.ring_int[CAYMAN_RING_TYPE_CP1_INDEX])) {
4531 if (atomic_read(&rdev->irq.ring_int[CAYMAN_RING_TYPE_CP2_INDEX])) {
4536 if (atomic_read(&rdev->irq.ring_int[RADEON_RING_TYPE_GFX_INDEX])) {
4543 if (atomic_read(&rdev->irq.ring_int[R600_RING_TYPE_DMA_INDEX])) {
4548 if (rdev->family >= CHIP_CAYMAN) {
4550 if (atomic_read(&rdev->irq.ring_int[CAYMAN_RING_TYPE_DMA1_INDEX])) {
4556 if (rdev->irq.dpm_thermal) {
4561 if (rdev->family >= CHIP_CAYMAN) {
4562 cayman_cp_int_cntl_setup(rdev, 0, cp_int_cntl);
4563 cayman_cp_int_cntl_setup(rdev, 1, cp_int_cntl1);
4564 cayman_cp_int_cntl_setup(rdev, 2, cp_int_cntl2);
4570 if (rdev->family >= CHIP_CAYMAN)
4575 for (i = 0; i < rdev->num_crtc; i++) {
4577 rdev, INT_MASK + crtc_offsets[i],
4579 rdev->irq.crtc_vblank_int[i] ||
4580 atomic_read(&rdev->irq.pflip[i]), "vblank", i);
4583 for (i = 0; i < rdev->num_crtc; i++)
4588 rdev, DC_HPDx_INT_CONTROL(i),
4590 rdev->irq.hpd[i], "HPD", i);
4593 if (rdev->family == CHIP_ARUBA)
4600 rdev, AFMT_AUDIO_PACKET_CONTROL + crtc_offsets[i],
4602 rdev->irq.afmt[i], "HDMI", i);
4612 static void evergreen_irq_ack(struct radeon_device *rdev)
4615 u32 *grph_int = rdev->irq.stat_regs.evergreen.grph_int;
4616 u32 *disp_int = rdev->irq.stat_regs.evergreen.disp_int;
4617 u32 *afmt_status = rdev->irq.stat_regs.evergreen.afmt_status;
4622 if (i < rdev->num_crtc)
4627 for (i = 0; i < rdev->num_crtc; i += 2) {
4661 static void evergreen_irq_disable(struct radeon_device *rdev)
4663 r600_disable_interrupts(rdev);
4666 evergreen_irq_ack(rdev);
4667 evergreen_disable_interrupt_state(rdev);
4670 void evergreen_irq_suspend(struct radeon_device *rdev)
4672 evergreen_irq_disable(rdev);
4673 r600_rlc_stop(rdev);
4676 static u32 evergreen_get_ih_wptr(struct radeon_device *rdev)
4680 if (rdev->wb.enabled)
4681 wptr = le32_to_cpu(rdev->wb.wb[R600_WB_IH_WPTR_OFFSET/4]);
4691 dev_warn(rdev->dev, "IH ring buffer overflow (0x%08X, 0x%08X, 0x%08X)\n",
4692 wptr, rdev->ih.rptr, (wptr + 16) & rdev->ih.ptr_mask);
4693 rdev->ih.rptr = (wptr + 16) & rdev->ih.ptr_mask;
4698 return (wptr & rdev->ih.ptr_mask);
4701 int evergreen_irq_process(struct radeon_device *rdev)
4703 u32 *disp_int = rdev->irq.stat_regs.evergreen.disp_int;
4704 u32 *afmt_status = rdev->irq.stat_regs.evergreen.afmt_status;
4718 if (!rdev->ih.enabled || rdev->shutdown)
4721 wptr = evergreen_get_ih_wptr(rdev);
4725 if (atomic_xchg(&rdev->ih.lock, 1))
4728 rptr = rdev->ih.rptr;
4735 evergreen_irq_ack(rdev);
4740 src_id = le32_to_cpu(rdev->ih.ring[ring_index]) & 0xff;
4741 src_data = le32_to_cpu(rdev->ih.ring[ring_index + 1]) & 0xfffffff;
4756 if (rdev->irq.crtc_vblank_int[crtc_idx]) {
4757 drm_handle_vblank(rdev->ddev, crtc_idx);
4758 rdev->pm.vblank_sync = true;
4759 wake_up(&rdev->irq.vblank_queue);
4761 if (atomic_read(&rdev->irq.pflip[crtc_idx])) {
4762 radeon_crtc_handle_vblank(rdev,
4792 radeon_crtc_handle_flip(rdev, (src_id - 8) >> 1);
4841 radeon_fence_process(rdev, R600_RING_TYPE_UVD_INDEX);
4851 dev_err(rdev->dev, "GPU fault detected: %d 0x%08x\n", src_id, src_data);
4852 dev_err(rdev->dev, " VM_CONTEXT1_PROTECTION_FAULT_ADDR 0x%08X\n",
4854 dev_err(rdev->dev, " VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x%08X\n",
4856 cayman_vm_decode_fault(rdev, status, addr);
4862 radeon_fence_process(rdev, RADEON_RING_TYPE_GFX_INDEX);
4866 if (rdev->family >= CHIP_CAYMAN) {
4869 radeon_fence_process(rdev, RADEON_RING_TYPE_GFX_INDEX);
4872 radeon_fence_process(rdev, CAYMAN_RING_TYPE_CP1_INDEX);
4875 radeon_fence_process(rdev, CAYMAN_RING_TYPE_CP2_INDEX);
4879 radeon_fence_process(rdev, RADEON_RING_TYPE_GFX_INDEX);
4883 radeon_fence_process(rdev, R600_RING_TYPE_DMA_INDEX);
4887 rdev->pm.dpm.thermal.high_to_low = false;
4892 rdev->pm.dpm.thermal.high_to_low = true;
4899 if (rdev->family >= CHIP_CAYMAN) {
4901 radeon_fence_process(rdev, CAYMAN_RING_TYPE_DMA1_INDEX);
4911 rptr &= rdev->ih.ptr_mask;
4915 schedule_work(&rdev->dp_work);
4917 schedule_delayed_work(&rdev->hotplug_work, 0);
4919 schedule_work(&rdev->audio_work);
4920 if (queue_thermal && rdev->pm.dpm_enabled)
4921 schedule_work(&rdev->pm.dpm.thermal.work);
4922 rdev->ih.rptr = rptr;
4924 atomic_set(&rdev->ih.lock, 0);
4927 wptr = evergreen_get_ih_wptr(rdev);
4934 static void evergreen_uvd_init(struct radeon_device *rdev)
4938 if (!rdev->has_uvd)
4941 r = radeon_uvd_init(rdev);
4943 dev_err(rdev->dev, "failed UVD (%d) init.\n", r);
4945 * At this point rdev->uvd.vcpu_bo is NULL which trickles down
4950 rdev->has_uvd = false;
4953 rdev->ring[R600_RING_TYPE_UVD_INDEX].ring_obj = NULL;
4954 r600_ring_init(rdev, &rdev->ring[R600_RING_TYPE_UVD_INDEX], 4096);
4957 static void evergreen_uvd_start(struct radeon_device *rdev)
4961 if (!rdev->has_uvd)
4964 r = uvd_v2_2_resume(rdev);
4966 dev_err(rdev->dev, "failed UVD resume (%d).\n", r);
4969 r = radeon_fence_driver_start_ring(rdev, R600_RING_TYPE_UVD_INDEX);
4971 dev_err(rdev->dev, "failed initializing UVD fences (%d).\n", r);
4977 rdev->ring[R600_RING_TYPE_UVD_INDEX].ring_size = 0;
4980 static void evergreen_uvd_resume(struct radeon_device *rdev)
4985 if (!rdev->has_uvd || !rdev->ring[R600_RING_TYPE_UVD_INDEX].ring_size)
4988 ring = &rdev->ring[R600_RING_TYPE_UVD_INDEX];
4989 r = radeon_ring_init(rdev, ring, ring->ring_size, 0, PACKET0(UVD_NO_OP, 0));
4991 dev_err(rdev->dev, "failed initializing UVD ring (%d).\n", r);
4994 r = uvd_v1_0_init(rdev);
4996 dev_err(rdev->dev, "failed initializing UVD (%d).\n", r);
5001 static int evergreen_startup(struct radeon_device *rdev)
5007 evergreen_pcie_gen2_enable(rdev);
5009 evergreen_program_aspm(rdev);
5012 r = r600_vram_scratch_init(rdev);
5016 evergreen_mc_program(rdev);
5018 if (ASIC_IS_DCE5(rdev) && !rdev->pm.dpm_enabled) {
5019 r = ni_mc_load_microcode(rdev);
5026 if (rdev->flags & RADEON_IS_AGP) {
5027 evergreen_agp_enable(rdev);
5029 r = evergreen_pcie_gart_enable(rdev);
5033 evergreen_gpu_init(rdev);
5036 if (rdev->flags & RADEON_IS_IGP) {
5037 rdev->rlc.reg_list = sumo_rlc_save_restore_register_list;
5038 rdev->rlc.reg_list_size =
5040 rdev->rlc.cs_data = evergreen_cs_data;
5041 r = sumo_rlc_init(rdev);
5049 r = radeon_wb_init(rdev);
5053 r = radeon_fence_driver_start_ring(rdev, RADEON_RING_TYPE_GFX_INDEX);
5055 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r);
5059 r = radeon_fence_driver_start_ring(rdev, R600_RING_TYPE_DMA_INDEX);
5061 dev_err(rdev->dev, "failed initializing DMA fences (%d).\n", r);
5065 evergreen_uvd_start(rdev);
5068 if (!rdev->irq.installed) {
5069 r = radeon_irq_kms_init(rdev);
5074 r = r600_irq_init(rdev);
5077 radeon_irq_kms_fini(rdev);
5080 evergreen_irq_set(rdev);
5082 ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
5083 r = radeon_ring_init(rdev, ring, ring->ring_size, RADEON_WB_CP_RPTR_OFFSET,
5088 ring = &rdev->ring[R600_RING_TYPE_DMA_INDEX];
5089 r = radeon_ring_init(rdev, ring, ring->ring_size, R600_WB_DMA_RPTR_OFFSET,
5094 r = evergreen_cp_load_microcode(rdev);
5097 r = evergreen_cp_resume(rdev);
5100 r = r600_dma_resume(rdev);
5104 evergreen_uvd_resume(rdev);
5106 r = radeon_ib_pool_init(rdev);
5108 dev_err(rdev->dev, "IB initialization failed (%d).\n", r);
5112 r = radeon_audio_init(rdev);
5121 int evergreen_resume(struct radeon_device *rdev)
5128 if (radeon_asic_reset(rdev))
5129 dev_warn(rdev->dev, "GPU reset failed !\n");
5135 atom_asic_init(rdev->mode_info.atom_context);
5138 evergreen_init_golden_registers(rdev);
5140 if (rdev->pm.pm_method == PM_METHOD_DPM)
5141 radeon_pm_resume(rdev);
5143 rdev->accel_working = true;
5144 r = evergreen_startup(rdev);
5147 rdev->accel_working = false;
5155 int evergreen_suspend(struct radeon_device *rdev)
5157 radeon_pm_suspend(rdev);
5158 radeon_audio_fini(rdev);
5159 if (rdev->has_uvd) {
5160 uvd_v1_0_fini(rdev);
5161 radeon_uvd_suspend(rdev);
5163 r700_cp_stop(rdev);
5164 r600_dma_stop(rdev);
5165 evergreen_irq_suspend(rdev);
5166 radeon_wb_disable(rdev);
5167 evergreen_pcie_gart_disable(rdev);
5178 int evergreen_init(struct radeon_device *rdev)
5183 if (!radeon_get_bios(rdev)) {
5184 if (ASIC_IS_AVIVO(rdev))
5188 if (!rdev->is_atom_bios) {
5189 dev_err(rdev->dev, "Expecting atombios for evergreen GPU\n");
5192 r = radeon_atombios_init(rdev);
5198 if (radeon_asic_reset(rdev))
5199 dev_warn(rdev->dev, "GPU reset failed !\n");
5201 if (!radeon_card_posted(rdev)) {
5202 if (!rdev->bios) {
5203 dev_err(rdev->dev, "Card not posted and no BIOS - ignoring\n");
5207 atom_asic_init(rdev->mode_info.atom_context);
5210 evergreen_init_golden_registers(rdev);
5212 r600_scratch_init(rdev);
5214 radeon_surface_init(rdev);
5216 radeon_get_clock_info(rdev->ddev);
5218 r = radeon_fence_driver_init(rdev);
5222 if (rdev->flags & RADEON_IS_AGP) {
5223 r = radeon_agp_init(rdev);
5225 radeon_agp_disable(rdev);
5228 r = evergreen_mc_init(rdev);
5232 r = radeon_bo_init(rdev);
5236 if (ASIC_IS_DCE5(rdev)) {
5237 if (!rdev->me_fw || !rdev->pfp_fw || !rdev->rlc_fw || !rdev->mc_fw) {
5238 r = ni_init_microcode(rdev);
5245 if (!rdev->me_fw || !rdev->pfp_fw || !rdev->rlc_fw) {
5246 r = r600_init_microcode(rdev);
5255 radeon_pm_init(rdev);
5257 rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ring_obj = NULL;
5258 r600_ring_init(rdev, &rdev->ring[RADEON_RING_TYPE_GFX_INDEX], 1024 * 1024);
5260 rdev->ring[R600_RING_TYPE_DMA_INDEX].ring_obj = NULL;
5261 r600_ring_init(rdev, &rdev->ring[R600_RING_TYPE_DMA_INDEX], 64 * 1024);
5263 evergreen_uvd_init(rdev);
5265 rdev->ih.ring_obj = NULL;
5266 r600_ih_ring_init(rdev, 64 * 1024);
5268 r = r600_pcie_gart_init(rdev);
5272 rdev->accel_working = true;
5273 r = evergreen_startup(rdev);
5275 dev_err(rdev->dev, "disabling GPU acceleration\n");
5276 r700_cp_fini(rdev);
5277 r600_dma_fini(rdev);
5278 r600_irq_fini(rdev);
5279 if (rdev->flags & RADEON_IS_IGP)
5280 sumo_rlc_fini(rdev);
5281 radeon_wb_fini(rdev);
5282 radeon_ib_pool_fini(rdev);
5283 radeon_irq_kms_fini(rdev);
5284 evergreen_pcie_gart_fini(rdev);
5285 rdev->accel_working = false;
5292 if (ASIC_IS_DCE5(rdev)) {
5293 if (!rdev->mc_fw && !(rdev->flags & RADEON_IS_IGP)) {
5302 void evergreen_fini(struct radeon_device *rdev)
5304 radeon_pm_fini(rdev);
5305 radeon_audio_fini(rdev);
5306 r700_cp_fini(rdev);
5307 r600_dma_fini(rdev);
5308 r600_irq_fini(rdev);
5309 if (rdev->flags & RADEON_IS_IGP)
5310 sumo_rlc_fini(rdev);
5311 radeon_wb_fini(rdev);
5312 radeon_ib_pool_fini(rdev);
5313 radeon_irq_kms_fini(rdev);
5314 uvd_v1_0_fini(rdev);
5315 radeon_uvd_fini(rdev);
5316 evergreen_pcie_gart_fini(rdev);
5317 r600_vram_scratch_fini(rdev);
5318 radeon_gem_fini(rdev);
5319 radeon_fence_driver_fini(rdev);
5320 radeon_agp_fini(rdev);
5321 radeon_bo_fini(rdev);
5322 radeon_atombios_fini(rdev);
5323 kfree(rdev->bios);
5324 rdev->bios = NULL;
5327 void evergreen_pcie_gen2_enable(struct radeon_device *rdev)
5334 if (rdev->flags & RADEON_IS_IGP)
5337 if (!(rdev->flags & RADEON_IS_PCIE))
5341 if (ASIC_IS_X2(rdev))
5344 if ((rdev->pdev->bus->max_bus_speed != PCIE_SPEED_5_0GT) &&
5345 (rdev->pdev->bus->max_bus_speed != PCIE_SPEED_8_0GT))
5390 void evergreen_program_aspm(struct radeon_device *rdev)
5405 if (!(rdev->flags & RADEON_IS_PCIE))
5408 switch (rdev->family) {
5425 if (rdev->flags & RADEON_IS_IGP)
5447 if (rdev->family >= CHIP_BARTS)
5454 if (rdev->family >= CHIP_BARTS)
5484 if (rdev->family >= CHIP_BARTS) {
5516 if (rdev->family >= CHIP_BARTS) {
5533 if (rdev->family < CHIP_BARTS)