Lines Matching refs:levels
780 &smc_state->levels[0],
787 &smc_state->levels[1],
794 &smc_state->levels[2],
799 smc_state->levels[0].arbValue = MC_CG_ARB_FREQ_F1;
800 smc_state->levels[1].arbValue = MC_CG_ARB_FREQ_F2;
801 smc_state->levels[2].arbValue = MC_CG_ARB_FREQ_F3;
804 smc_state->levels[0].ACIndex = 2;
805 smc_state->levels[1].ACIndex = 3;
806 smc_state->levels[2].ACIndex = 4;
808 smc_state->levels[0].ACIndex = 0;
809 smc_state->levels[1].ACIndex = 0;
810 smc_state->levels[2].ACIndex = 0;
1248 table->initialState.levels[0].mclk.mclk770.vMPLL_AD_FUNC_CNTL =
1250 table->initialState.levels[0].mclk.mclk770.vMPLL_AD_FUNC_CNTL_2 =
1252 table->initialState.levels[0].mclk.mclk770.vMPLL_DQ_FUNC_CNTL =
1254 table->initialState.levels[0].mclk.mclk770.vMPLL_DQ_FUNC_CNTL_2 =
1256 table->initialState.levels[0].mclk.mclk770.vMCLK_PWRMGT_CNTL =
1258 table->initialState.levels[0].mclk.mclk770.vDLL_CNTL =
1261 table->initialState.levels[0].mclk.mclk770.vMPLL_SS =
1263 table->initialState.levels[0].mclk.mclk770.vMPLL_SS2 =
1266 table->initialState.levels[0].mclk.mclk770.mclk_value =
1269 table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL =
1271 table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_2 =
1273 table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_3 =
1275 table->initialState.levels[0].sclk.vCG_SPLL_SPREAD_SPECTRUM =
1277 table->initialState.levels[0].sclk.vCG_SPLL_SPREAD_SPECTRUM_2 =
1280 table->initialState.levels[0].sclk.sclk_value =
1283 table->initialState.levels[0].arbValue = MC_CG_ARB_FREQ_F0;
1285 table->initialState.levels[0].ACIndex = 0;
1290 &table->initialState.levels[0].vddc);
1296 &table->initialState.levels[0].vddci);
1299 &table->initialState.levels[0].mvdd);
1302 table->initialState.levels[0].aT = cpu_to_be32(a_t);
1304 table->initialState.levels[0].bSP = cpu_to_be32(pi->dsp);
1308 table->initialState.levels[0].gen2PCIE = 1;
1310 table->initialState.levels[0].gen2PCIE = 0;
1312 table->initialState.levels[0].gen2XSP = 1;
1314 table->initialState.levels[0].gen2XSP = 0;
1317 table->initialState.levels[0].strobeMode =
1322 table->initialState.levels[0].mcFlags = SMC_MC_EDC_RD_FLAG | SMC_MC_EDC_WR_FLAG;
1324 table->initialState.levels[0].mcFlags = 0;
1327 table->initialState.levels[1] = table->initialState.levels[0];
1328 table->initialState.levels[2] = table->initialState.levels[0];
1367 &table->ACPIState.levels[0].vddc);
1370 table->ACPIState.levels[0].gen2PCIE = 1;
1372 table->ACPIState.levels[0].gen2PCIE = 0;
1374 table->ACPIState.levels[0].gen2PCIE = 0;
1376 table->ACPIState.levels[0].gen2XSP = 1;
1378 table->ACPIState.levels[0].gen2XSP = 0;
1383 &table->ACPIState.levels[0].vddc);
1384 table->ACPIState.levels[0].gen2PCIE = 0;
1392 &table->ACPIState.levels[0].vddci);
1438 table->ACPIState.levels[0].mclk.mclk770.vMPLL_AD_FUNC_CNTL =
1440 table->ACPIState.levels[0].mclk.mclk770.vMPLL_AD_FUNC_CNTL_2 =
1442 table->ACPIState.levels[0].mclk.mclk770.vMPLL_DQ_FUNC_CNTL =
1444 table->ACPIState.levels[0].mclk.mclk770.vMPLL_DQ_FUNC_CNTL_2 =
1446 table->ACPIState.levels[0].mclk.mclk770.vMCLK_PWRMGT_CNTL =
1448 table->ACPIState.levels[0].mclk.mclk770.vDLL_CNTL = cpu_to_be32(dll_cntl);
1450 table->ACPIState.levels[0].mclk.mclk770.mclk_value = 0;
1452 table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL =
1454 table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_2 =
1456 table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_3 =
1459 table->ACPIState.levels[0].sclk.sclk_value = 0;
1461 cypress_populate_mvdd_value(rdev, 0, &table->ACPIState.levels[0].mvdd);
1464 table->ACPIState.levels[0].ACIndex = 1;
1466 table->ACPIState.levels[1] = table->ACPIState.levels[0];
1467 table->ACPIState.levels[2] = table->ACPIState.levels[0];