Lines Matching defs:tmp
54 u32 tmp, bif;
56 tmp = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL);
58 if ((tmp & LC_OTHER_SIDE_EVER_SENT_GEN2) &&
59 (tmp & LC_OTHER_SIDE_SUPPORTS_GEN2)) {
65 tmp &= ~LC_HW_VOLTAGE_IF_CONTROL_MASK;
66 tmp |= LC_HW_VOLTAGE_IF_CONTROL(1);
67 tmp |= LC_GEN2_EN_STRAP;
69 tmp |= LC_CLR_FAILED_SPD_CHANGE_CNT;
70 WREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL, tmp);
72 tmp &= ~LC_CLR_FAILED_SPD_CHANGE_CNT;
73 WREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL, tmp);
78 tmp &= ~LC_HW_VOLTAGE_IF_CONTROL_MASK;
79 tmp &= ~LC_GEN2_EN_STRAP;
81 if ((tmp & LC_OTHER_SIDE_EVER_SENT_GEN2) ||
82 (tmp & LC_OTHER_SIDE_SUPPORTS_GEN2))
83 WREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL, tmp);
307 u32 tmp;
310 tmp = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL);
311 if ((perf_req == PCIE_PERF_REQ_PECI_GEN1) && (tmp & LC_CURRENT_DATA_RATE))
332 u32 tmp;
338 tmp = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL);
340 if ((tmp & LC_OTHER_SIDE_EVER_SENT_GEN2) &&
341 (tmp & LC_OTHER_SIDE_SUPPORTS_GEN2))
1581 u32 tmp = RREG32(GENERAL_PWRMGT);
1583 if (!(tmp & BACKBIAS_PAD_EN)) {
1590 if (tmp & BACKBIAS_VALUE)
1700 u32 tmp;
1706 &tmp, pi->sram_end);
1710 pi->state_table_start = (u16)tmp;
1715 &tmp, pi->sram_end);
1719 pi->soft_regs_start = (u16)tmp;
1724 &tmp, pi->sram_end);
1728 eg_pi->mc_reg_table_start = (u16)tmp;
1735 u32 tmp = RREG32(CG_DISPLAY_GAP_CNTL);
1737 tmp &= ~(DISP1_GAP_MASK | DISP2_GAP_MASK);
1738 tmp |= (DISP1_GAP(R600_PM_DISPLAY_GAP_IGNORE) |
1741 tmp &= ~(DISP1_GAP_MCHG_MASK | DISP2_GAP_MCHG_MASK);
1742 tmp |= (DISP1_GAP_MCHG(R600_PM_DISPLAY_GAP_VBLANK) |
1744 WREG32(CG_DISPLAY_GAP_CNTL, tmp);
1749 u32 tmp, pipe;
1752 tmp = RREG32(CG_DISPLAY_GAP_CNTL) & ~(DISP1_GAP_MASK | DISP2_GAP_MASK);
1754 tmp |= DISP1_GAP(R600_PM_DISPLAY_GAP_VBLANK_OR_WM);
1756 tmp |= DISP1_GAP(R600_PM_DISPLAY_GAP_IGNORE);
1759 tmp |= DISP2_GAP(R600_PM_DISPLAY_GAP_VBLANK_OR_WM);
1761 tmp |= DISP2_GAP(R600_PM_DISPLAY_GAP_IGNORE);
1763 WREG32(CG_DISPLAY_GAP_CNTL, tmp);
1765 tmp = RREG32(DCCG_DISP_SLOW_SELECT_REG);
1766 pipe = (tmp & DCCG_DISP1_SLOW_SELECT_MASK) >> DCCG_DISP1_SLOW_SELECT_SHIFT;
1780 tmp &= ~DCCG_DISP1_SLOW_SELECT_MASK;
1781 tmp |= DCCG_DISP1_SLOW_SELECT(pipe);
1782 WREG32(DCCG_DISP_SLOW_SELECT_REG, tmp);