Lines Matching refs:ring
43 * and each one supports 1 ring buffer used for gfx
47 * (ring buffer, IBs, etc.), but sDMA has it's own
59 * @ring: radeon ring pointer
64 struct radeon_ring *ring)
69 rptr = rdev->wb.wb[ring->rptr_offs/4];
71 if (ring->idx == R600_RING_TYPE_DMA_INDEX)
86 * @ring: radeon ring pointer
91 struct radeon_ring *ring)
95 if (ring->idx == R600_RING_TYPE_DMA_INDEX)
107 * @ring: radeon ring pointer
112 struct radeon_ring *ring)
116 if (ring->idx == R600_RING_TYPE_DMA_INDEX)
121 WREG32(reg, (ring->wptr << 2) & 0x3fffc);
131 * Schedule an IB in the DMA ring (CIK).
136 struct radeon_ring *ring = &rdev->ring[ib->ring];
137 u32 extra_bits = (ib->vm ? ib->vm->ids[ib->ring].id : 0) & 0xf;
140 u32 next_rptr = ring->wptr + 5;
144 radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_WRITE, SDMA_WRITE_SUB_OPCODE_LINEAR, 0));
145 radeon_ring_write(ring, ring->next_rptr_gpu_addr & 0xfffffffc);
146 radeon_ring_write(ring, upper_32_bits(ring->next_rptr_gpu_addr));
147 radeon_ring_write(ring, 1); /* number of DWs to follow */
148 radeon_ring_write(ring, next_rptr);
152 while ((ring->wptr & 7) != 4)
153 radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_NOP, 0, 0));
154 radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_INDIRECT_BUFFER, 0, extra_bits));
155 radeon_ring_write(ring, ib->gpu_addr & 0xffffffe0); /* base must be 32 byte aligned */
156 radeon_ring_write(ring, upper_32_bits(ib->gpu_addr));
157 radeon_ring_write(ring, ib->length_dw);
162 * cik_sdma_hdp_flush_ring_emit - emit an hdp flush on the DMA ring
165 * @ridx: radeon ring index
167 * Emit an hdp flush packet on the requested DMA ring.
172 struct radeon_ring *ring = &rdev->ring[ridx];
182 radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_POLL_REG_MEM, 0, extra_bits));
183 radeon_ring_write(ring, GPU_HDP_FLUSH_DONE);
184 radeon_ring_write(ring, GPU_HDP_FLUSH_REQ);
185 radeon_ring_write(ring, ref_and_mask); /* reference */
186 radeon_ring_write(ring, ref_and_mask); /* mask */
187 radeon_ring_write(ring, (0xfff << 16) | 10); /* retry count, poll interval */
191 * cik_sdma_fence_ring_emit - emit a fence on the DMA ring
196 * Add a DMA fence packet to the ring to write
203 struct radeon_ring *ring = &rdev->ring[fence->ring];
204 u64 addr = rdev->fence_drv[fence->ring].gpu_addr;
207 radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_FENCE, 0, 0));
208 radeon_ring_write(ring, lower_32_bits(addr));
209 radeon_ring_write(ring, upper_32_bits(addr));
210 radeon_ring_write(ring, fence->seq);
212 radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_TRAP, 0, 0));
214 cik_sdma_hdp_flush_ring_emit(rdev, fence->ring);
218 * cik_sdma_semaphore_ring_emit - emit a semaphore on the dma ring
221 * @ring: radeon_ring structure holding ring information
225 * Add a DMA semaphore packet to the ring wait on or signal
229 struct radeon_ring *ring,
236 radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_SEMAPHORE, 0, extra_bits));
237 radeon_ring_write(ring, addr & 0xfffffff8);
238 radeon_ring_write(ring, upper_32_bits(addr));
248 * Stop the gfx async dma ring buffers (CIK).
269 rdev->ring[R600_RING_TYPE_DMA_INDEX].ready = false;
270 rdev->ring[CAYMAN_RING_TYPE_DMA1_INDEX].ready = false;
362 * Set up the gfx DMA ring buffers and enable them (CIK).
367 struct radeon_ring *ring;
375 ring = &rdev->ring[R600_RING_TYPE_DMA_INDEX];
379 ring = &rdev->ring[CAYMAN_RING_TYPE_DMA1_INDEX];
387 /* Set ring buffer size in dwords */
388 rb_bufsz = order_base_2(ring->ring_size / 4);
395 /* Initialize the ring buffer's read and write pointers */
408 WREG32(SDMA0_GFX_RB_BASE + reg_offset, ring->gpu_addr >> 8);
409 WREG32(SDMA0_GFX_RB_BASE_HI + reg_offset, ring->gpu_addr >> 40);
411 ring->wptr = 0;
412 WREG32(SDMA0_GFX_RB_WPTR + reg_offset, ring->wptr << 2);
424 ring->ready = true;
426 r = radeon_ring_test(rdev, ring->idx, ring);
428 ring->ready = false;
561 radeon_ring_fini(rdev, &rdev->ring[R600_RING_TYPE_DMA_INDEX]);
562 radeon_ring_fini(rdev, &rdev->ring[CAYMAN_RING_TYPE_DMA1_INDEX]);
587 struct radeon_ring *ring = &rdev->ring[ring_index];
596 r = radeon_ring_lock(rdev, ring, num_loops * 7 + 14);
604 radeon_sync_rings(rdev, &sync, ring->idx);
611 radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_COPY, SDMA_COPY_SUB_OPCODE_LINEAR, 0));
612 radeon_ring_write(ring, cur_size_in_bytes);
613 radeon_ring_write(ring, 0); /* src/dst endian swap */
614 radeon_ring_write(ring, lower_32_bits(src_offset));
615 radeon_ring_write(ring, upper_32_bits(src_offset));
616 radeon_ring_write(ring, lower_32_bits(dst_offset));
617 radeon_ring_write(ring, upper_32_bits(dst_offset));
622 r = radeon_fence_emit(rdev, &fence, ring->idx);
624 radeon_ring_unlock_undo(rdev, ring);
629 radeon_ring_unlock_commit(rdev, ring, false);
639 * @ring: radeon_ring structure holding ring information
646 struct radeon_ring *ring)
654 if (ring->idx == R600_RING_TYPE_DMA_INDEX)
664 r = radeon_ring_lock(rdev, ring, 5);
666 DRM_ERROR("radeon: dma failed to lock ring %d (%d).\n", ring->idx, r);
669 radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_WRITE, SDMA_WRITE_SUB_OPCODE_LINEAR, 0));
670 radeon_ring_write(ring, lower_32_bits(gpu_addr));
671 radeon_ring_write(ring, upper_32_bits(gpu_addr));
672 radeon_ring_write(ring, 1); /* number of DWs to follow */
673 radeon_ring_write(ring, 0xDEADBEEF);
674 radeon_ring_unlock_commit(rdev, ring, false);
684 DRM_INFO("ring test on %d succeeded in %d usecs\n", ring->idx, i);
686 DRM_ERROR("radeon: ring %d test failed (0x%08X)\n",
687 ring->idx, tmp);
697 * @ring: radeon_ring structure holding ring information
699 * Test a simple IB in the DMA ring (CIK).
702 int cik_sdma_ib_test(struct radeon_device *rdev, struct radeon_ring *ring)
711 if (ring->idx == R600_RING_TYPE_DMA_INDEX)
721 r = radeon_ib_get(rdev, ring->idx, &ib, NULL, 256);
757 DRM_INFO("ib test on ring %d succeeded in %u usecs\n", ib.fence->ring, i);
770 * @ring: radeon_ring structure holding ring information
775 bool cik_sdma_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring)
780 if (ring->idx == R600_RING_TYPE_DMA_INDEX)
786 radeon_ring_lockup_update(rdev, ring);
789 return radeon_ring_test_lockup(rdev, ring);
947 void cik_dma_vm_flush(struct radeon_device *rdev, struct radeon_ring *ring,
953 radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_SRBM_WRITE, 0, 0xf000));
955 radeon_ring_write(ring, (VM_CONTEXT0_PAGE_TABLE_BASE_ADDR + (vm_id << 2)) >> 2);
957 radeon_ring_write(ring, (VM_CONTEXT8_PAGE_TABLE_BASE_ADDR + ((vm_id - 8) << 2)) >> 2);
959 radeon_ring_write(ring, pd_addr >> 12);
962 radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_SRBM_WRITE, 0, 0xf000));
963 radeon_ring_write(ring, SRBM_GFX_CNTL >> 2);
964 radeon_ring_write(ring, VMID(vm_id));
966 radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_SRBM_WRITE, 0, 0xf000));
967 radeon_ring_write(ring, SH_MEM_BASES >> 2);
968 radeon_ring_write(ring, 0);
970 radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_SRBM_WRITE, 0, 0xf000));
971 radeon_ring_write(ring, SH_MEM_CONFIG >> 2);
972 radeon_ring_write(ring, 0);
974 radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_SRBM_WRITE, 0, 0xf000));
975 radeon_ring_write(ring, SH_MEM_APE1_BASE >> 2);
976 radeon_ring_write(ring, 1);
978 radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_SRBM_WRITE, 0, 0xf000));
979 radeon_ring_write(ring, SH_MEM_APE1_LIMIT >> 2);
980 radeon_ring_write(ring, 0);
982 radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_SRBM_WRITE, 0, 0xf000));
983 radeon_ring_write(ring, SRBM_GFX_CNTL >> 2);
984 radeon_ring_write(ring, VMID(0));
987 cik_sdma_hdp_flush_ring_emit(rdev, ring->idx);
990 radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_SRBM_WRITE, 0, 0xf000));
991 radeon_ring_write(ring, VM_INVALIDATE_REQUEST >> 2);
992 radeon_ring_write(ring, 1 << vm_id);
994 radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_POLL_REG_MEM, 0, extra_bits));
995 radeon_ring_write(ring, VM_INVALIDATE_REQUEST >> 2);
996 radeon_ring_write(ring, 0);
997 radeon_ring_write(ring, 0); /* reference */
998 radeon_ring_write(ring, 0); /* mask */
999 radeon_ring_write(ring, (0xfff << 16) | 10); /* retry count, poll interval */