Lines Matching refs:ib
129 * @ib: IB object to schedule
134 struct radeon_ib *ib)
136 struct radeon_ring *ring = &rdev->ring[ib->ring];
137 u32 extra_bits = (ib->vm ? ib->vm->ids[ib->ring].id : 0) & 0xf;
155 radeon_ring_write(ring, ib->gpu_addr & 0xffffffe0); /* base must be 32 byte aligned */
156 radeon_ring_write(ring, upper_32_bits(ib->gpu_addr));
157 radeon_ring_write(ring, ib->length_dw);
704 struct radeon_ib ib;
721 r = radeon_ib_get(rdev, ring->idx, &ib, NULL, 256);
723 DRM_ERROR("radeon: failed to get ib (%d).\n", r);
727 ib.ptr[0] = SDMA_PACKET(SDMA_OPCODE_WRITE, SDMA_WRITE_SUB_OPCODE_LINEAR, 0);
728 ib.ptr[1] = lower_32_bits(gpu_addr);
729 ib.ptr[2] = upper_32_bits(gpu_addr);
730 ib.ptr[3] = 1;
731 ib.ptr[4] = 0xDEADBEEF;
732 ib.length_dw = 5;
734 r = radeon_ib_schedule(rdev, &ib, NULL, false);
736 radeon_ib_free(rdev, &ib);
737 DRM_ERROR("radeon: failed to schedule ib (%d).\n", r);
740 r = radeon_fence_wait_timeout(ib.fence, false, usecs_to_jiffies(
757 DRM_INFO("ib test on ring %d succeeded in %u usecs\n", ib.fence->ring, i);
759 DRM_ERROR("radeon: ib test failed (0x%08X)\n", tmp);
762 radeon_ib_free(rdev, &ib);
796 * @ib: indirect buffer to fill with commands
804 struct radeon_ib *ib,
813 ib->ptr[ib->length_dw++] = SDMA_PACKET(SDMA_OPCODE_COPY,
815 ib->ptr[ib->length_dw++] = bytes;
816 ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */
817 ib->ptr[ib->length_dw++] = lower_32_bits(src);
818 ib->ptr[ib->length_dw++] = upper_32_bits(src);
819 ib->ptr[ib->length_dw++] = lower_32_bits(pe);
820 ib->ptr[ib->length_dw++] = upper_32_bits(pe);
832 * @ib: indirect buffer to fill with commands
842 struct radeon_ib *ib,
856 ib->ptr[ib->length_dw++] = SDMA_PACKET(SDMA_OPCODE_WRITE,
858 ib->ptr[ib->length_dw++] = pe;
859 ib->ptr[ib->length_dw++] = upper_32_bits(pe);
860 ib->ptr[ib->length_dw++] = ndw;
871 ib->ptr[ib->length_dw++] = value;
872 ib->ptr[ib->length_dw++] = upper_32_bits(value);
881 * @ib: indirect buffer to fill with commands
891 struct radeon_ib *ib,
910 ib->ptr[ib->length_dw++] = SDMA_PACKET(SDMA_OPCODE_GENERATE_PTE_PDE, 0, 0);
911 ib->ptr[ib->length_dw++] = pe; /* dst addr */
912 ib->ptr[ib->length_dw++] = upper_32_bits(pe);
913 ib->ptr[ib->length_dw++] = flags; /* mask */
914 ib->ptr[ib->length_dw++] = 0;
915 ib->ptr[ib->length_dw++] = value; /* value */
916 ib->ptr[ib->length_dw++] = upper_32_bits(value);
917 ib->ptr[ib->length_dw++] = incr; /* increment size */
918 ib->ptr[ib->length_dw++] = 0;
919 ib->ptr[ib->length_dw++] = ndw; /* number of entries */
930 * @ib: indirect buffer to fill with padding
933 void cik_sdma_vm_pad_ib(struct radeon_ib *ib)
935 while (ib->length_dw & 0x7)
936 ib->ptr[ib->length_dw++] = SDMA_PACKET(SDMA_OPCODE_NOP, 0, 0);