Lines Matching defs:tmp
1873 u32 running, tmp;
1929 tmp = RREG32(MC_SEQ_MISC0);
1930 if ((rdev->pdev->device == 0x6649) && ((tmp & 0xff00) == 0x5600)) {
3183 u32 tmp;
3279 tmp = (mc_arb_ramcfg & NOOFCOLS_MASK) >> NOOFCOLS_SHIFT;
3280 rdev->config.cik.mem_row_size_in_kb = (4 * (1 << (8 + tmp))) / 1024;
3364 tmp = RREG32(SPI_CONFIG_CNTL);
3365 tmp |= 0x03000000;
3366 WREG32(SPI_CONFIG_CNTL, tmp);
3372 tmp = RREG32(DB_DEBUG2) & ~0xf00fffff;
3373 tmp |= 0x00000400;
3374 WREG32(DB_DEBUG2, tmp);
3376 tmp = RREG32(DB_DEBUG3) & ~0x0002021c;
3377 tmp |= 0x00020200;
3378 WREG32(DB_DEBUG3, tmp);
3380 tmp = RREG32(CB_HW_CONTROL) & ~0x00010000;
3381 tmp |= 0x00018208;
3382 WREG32(CB_HW_CONTROL, tmp);
3406 tmp = RREG32(HDP_MISC_CNTL);
3407 tmp |= HDP_FLUSH_INVALIDATE_CACHE;
3408 WREG32(HDP_MISC_CNTL, tmp);
3458 uint32_t tmp = 0;
3480 tmp = RREG32(scratch);
3481 if (tmp == 0xDEADBEEF)
3489 ring->idx, scratch, tmp);
3783 uint32_t tmp = 0;
3825 tmp = RREG32(scratch);
3826 if (tmp == 0xDEADBEEF)
3834 scratch, tmp);
4059 u32 tmp;
4080 tmp = (order_base_2(RADEON_GPU_PAGE_SIZE/8) << 8) | rb_bufsz;
4082 tmp |= BUF_SWAP_32BIT;
4084 WREG32(CP_RB0_CNTL, tmp);
4087 WREG32(CP_RB0_CNTL, tmp | RB_RPTR_WR_ENA);
4099 tmp |= RB_NO_UPDATE;
4102 WREG32(CP_RB0_CNTL, tmp);
4197 u32 j, tmp;
4201 tmp = RREG32(CP_PQ_WPTR_POLL_CNTL);
4202 tmp &= ~WPTR_POLL_EN;
4203 WREG32(CP_PQ_WPTR_POLL_CNTL, tmp);
4521 u32 tmp;
4535 tmp = RREG32(CP_CPF_DEBUG);
4536 tmp |= (1 << 23);
4537 WREG32(CP_CPF_DEBUG, tmp);
4557 tmp = RREG32(CP_HPD_EOP_CONTROL);
4558 tmp &= ~EOP_SIZE_MASK;
4559 tmp |= order_base_2(MEC_HPD_SIZE / 8);
4560 WREG32(CP_HPD_EOP_CONTROL, tmp);
4620 tmp = RREG32(CP_PQ_WPTR_POLL_CNTL);
4621 tmp &= ~WPTR_POLL_EN;
4622 WREG32(CP_PQ_WPTR_POLL_CNTL, tmp);
4855 u32 tmp;
4858 tmp = RREG32(GRBM_STATUS);
4859 if (tmp & (PA_BUSY | SC_BUSY |
4867 if (tmp & (CP_BUSY | CP_COHERENCY_BUSY))
4871 tmp = RREG32(GRBM_STATUS2);
4872 if (tmp & RLC_BUSY)
4876 tmp = RREG32(SDMA0_STATUS_REG + SDMA0_REGISTER_OFFSET);
4877 if (!(tmp & SDMA_IDLE))
4881 tmp = RREG32(SDMA0_STATUS_REG + SDMA1_REGISTER_OFFSET);
4882 if (!(tmp & SDMA_IDLE))
4886 tmp = RREG32(SRBM_STATUS2);
4887 if (tmp & SDMA_BUSY)
4890 if (tmp & SDMA1_BUSY)
4894 tmp = RREG32(SRBM_STATUS);
4896 if (tmp & IH_BUSY)
4899 if (tmp & SEM_BUSY)
4902 if (tmp & GRBM_RQ_PENDING)
4905 if (tmp & VMC_BUSY)
4908 if (tmp & (MCB_BUSY | MCB_NON_DISPLAY_BUSY |
4936 u32 tmp;
4964 tmp = RREG32(SDMA0_ME_CNTL + SDMA0_REGISTER_OFFSET);
4965 tmp |= SDMA_HALT;
4966 WREG32(SDMA0_ME_CNTL + SDMA0_REGISTER_OFFSET, tmp);
4970 tmp = RREG32(SDMA0_ME_CNTL + SDMA1_REGISTER_OFFSET);
4971 tmp |= SDMA_HALT;
4972 WREG32(SDMA0_ME_CNTL + SDMA1_REGISTER_OFFSET, tmp);
5019 tmp = RREG32(GRBM_SOFT_RESET);
5020 tmp |= grbm_soft_reset;
5021 dev_info(rdev->dev, "GRBM_SOFT_RESET=0x%08X\n", tmp);
5022 WREG32(GRBM_SOFT_RESET, tmp);
5023 tmp = RREG32(GRBM_SOFT_RESET);
5027 tmp &= ~grbm_soft_reset;
5028 WREG32(GRBM_SOFT_RESET, tmp);
5029 tmp = RREG32(GRBM_SOFT_RESET);
5033 tmp = RREG32(SRBM_SOFT_RESET);
5034 tmp |= srbm_soft_reset;
5035 dev_info(rdev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
5036 WREG32(SRBM_SOFT_RESET, tmp);
5037 tmp = RREG32(SRBM_SOFT_RESET);
5041 tmp &= ~srbm_soft_reset;
5042 WREG32(SRBM_SOFT_RESET, tmp);
5043 tmp = RREG32(SRBM_SOFT_RESET);
5150 u32 tmp, i;
5167 tmp = RREG32(SDMA0_ME_CNTL + SDMA0_REGISTER_OFFSET);
5168 tmp |= SDMA_HALT;
5169 WREG32(SDMA0_ME_CNTL + SDMA0_REGISTER_OFFSET, tmp);
5171 tmp = RREG32(SDMA0_ME_CNTL + SDMA1_REGISTER_OFFSET);
5172 tmp |= SDMA_HALT;
5173 WREG32(SDMA0_ME_CNTL + SDMA1_REGISTER_OFFSET, tmp);
5284 u32 tmp;
5310 tmp = ((rdev->mc.vram_end >> 24) & 0xFFFF) << 16;
5311 tmp |= ((rdev->mc.vram_start >> 24) & 0xFFFF);
5312 WREG32(MC_VM_FB_LOCATION, tmp);
5340 u32 tmp;
5345 tmp = RREG32(MC_ARB_RAMCFG);
5346 if (tmp & CHANSIZE_MASK) {
5351 tmp = RREG32(MC_SHARED_CHMAP);
5352 switch ((tmp & NOOFCHAN_MASK) >> NOOFCHAN_SHIFT) {
5506 u32 tmp = RREG32(CHUB_CONTROL);
5507 tmp &= ~BYPASS_VM;
5508 WREG32(CHUB_CONTROL, tmp);
5631 u64 tmp = RREG32(MC_VM_FB_OFFSET);
5632 tmp <<= 22;
5633 rdev->vm_manager.vram_base_offset = tmp;
5771 u32 tmp = RREG32(CP_INT_CNTL_RING0);
5774 tmp |= (CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE);
5776 tmp &= ~(CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE);
5777 WREG32(CP_INT_CNTL_RING0, tmp);
5782 u32 tmp;
5784 tmp = RREG32(RLC_LB_CNTL);
5786 tmp |= LOAD_BALANCE_ENABLE;
5788 tmp &= ~LOAD_BALANCE_ENABLE;
5789 WREG32(RLC_LB_CNTL, tmp);
5819 u32 tmp;
5821 tmp = RREG32(RLC_CNTL);
5822 if (tmp != rlc)
5852 u32 tmp, i, mask;
5854 tmp = REQ | MESSAGE(MSG_ENTER_RLC_SAFE_MODE);
5855 WREG32(RLC_GPR_REG2, tmp);
5873 u32 tmp;
5875 tmp = REQ | MESSAGE(MSG_EXIT_RLC_SAFE_MODE);
5876 WREG32(RLC_GPR_REG2, tmp);
5922 u32 i, size, tmp;
5930 tmp = RREG32(RLC_CGCG_CGLS_CTRL) & 0xfffffffc;
5931 WREG32(RLC_CGCG_CGLS_CTRL, tmp);
6003 u32 data, orig, tmp, tmp2;
6010 tmp = cik_halt_rlc(rdev);
6018 cik_update_rlc(rdev, tmp);
6039 u32 data, orig, tmp = 0;
6057 tmp = cik_halt_rlc(rdev);
6065 cik_update_rlc(rdev, tmp);
6105 tmp = cik_halt_rlc(rdev);
6113 cik_update_rlc(rdev, tmp);
6537 u32 mask = 0, tmp, tmp1;
6541 tmp = RREG32(CC_GC_SHADER_ARRAY_CONFIG);
6545 tmp &= 0xffff0000;
6547 tmp |= tmp1;
6548 tmp >>= 16;
6555 return (~tmp) & mask;
6562 u32 tmp = 0;
6579 tmp |= (cu_bitmap << (i * 16 + j * 8));
6583 WREG32(RLC_PG_AO_CU_MASK, tmp);
6585 tmp = RREG32(RLC_MAX_PG_CU);
6586 tmp &= ~MAX_PU_CU_MASK;
6587 tmp |= MAX_PU_CU(active_cu_number);
6588 WREG32(RLC_MAX_PG_CU, tmp);
6867 u32 tmp;
6870 tmp = RREG32(CP_INT_CNTL_RING0) &
6872 WREG32(CP_INT_CNTL_RING0, tmp);
6874 tmp = RREG32(SDMA0_CNTL + SDMA0_REGISTER_OFFSET) & ~TRAP_ENABLE;
6875 WREG32(SDMA0_CNTL + SDMA0_REGISTER_OFFSET, tmp);
6876 tmp = RREG32(SDMA0_CNTL + SDMA1_REGISTER_OFFSET) & ~TRAP_ENABLE;
6877 WREG32(SDMA0_CNTL + SDMA1_REGISTER_OFFSET, tmp);
6920 tmp = RREG32(DC_HPD1_INT_CONTROL) & DC_HPDx_INT_POLARITY;
6921 WREG32(DC_HPD1_INT_CONTROL, tmp);
6922 tmp = RREG32(DC_HPD2_INT_CONTROL) & DC_HPDx_INT_POLARITY;
6923 WREG32(DC_HPD2_INT_CONTROL, tmp);
6924 tmp = RREG32(DC_HPD3_INT_CONTROL) & DC_HPDx_INT_POLARITY;
6925 WREG32(DC_HPD3_INT_CONTROL, tmp);
6926 tmp = RREG32(DC_HPD4_INT_CONTROL) & DC_HPDx_INT_POLARITY;
6927 WREG32(DC_HPD4_INT_CONTROL, tmp);
6928 tmp = RREG32(DC_HPD5_INT_CONTROL) & DC_HPDx_INT_POLARITY;
6929 WREG32(DC_HPD5_INT_CONTROL, tmp);
6930 tmp = RREG32(DC_HPD6_INT_CONTROL) & DC_HPDx_INT_POLARITY;
6931 WREG32(DC_HPD6_INT_CONTROL, tmp);
7298 u32 tmp;
7375 tmp = RREG32(DC_HPD1_INT_CONTROL);
7376 tmp |= DC_HPDx_INT_ACK;
7377 WREG32(DC_HPD1_INT_CONTROL, tmp);
7380 tmp = RREG32(DC_HPD2_INT_CONTROL);
7381 tmp |= DC_HPDx_INT_ACK;
7382 WREG32(DC_HPD2_INT_CONTROL, tmp);
7385 tmp = RREG32(DC_HPD3_INT_CONTROL);
7386 tmp |= DC_HPDx_INT_ACK;
7387 WREG32(DC_HPD3_INT_CONTROL, tmp);
7390 tmp = RREG32(DC_HPD4_INT_CONTROL);
7391 tmp |= DC_HPDx_INT_ACK;
7392 WREG32(DC_HPD4_INT_CONTROL, tmp);
7395 tmp = RREG32(DC_HPD5_INT_CONTROL);
7396 tmp |= DC_HPDx_INT_ACK;
7397 WREG32(DC_HPD5_INT_CONTROL, tmp);
7400 tmp = RREG32(DC_HPD6_INT_CONTROL);
7401 tmp |= DC_HPDx_INT_ACK;
7402 WREG32(DC_HPD6_INT_CONTROL, tmp);
7405 tmp = RREG32(DC_HPD1_INT_CONTROL);
7406 tmp |= DC_HPDx_RX_INT_ACK;
7407 WREG32(DC_HPD1_INT_CONTROL, tmp);
7410 tmp = RREG32(DC_HPD2_INT_CONTROL);
7411 tmp |= DC_HPDx_RX_INT_ACK;
7412 WREG32(DC_HPD2_INT_CONTROL, tmp);
7415 tmp = RREG32(DC_HPD3_INT_CONTROL);
7416 tmp |= DC_HPDx_RX_INT_ACK;
7417 WREG32(DC_HPD3_INT_CONTROL, tmp);
7420 tmp = RREG32(DC_HPD4_INT_CONTROL);
7421 tmp |= DC_HPDx_RX_INT_ACK;
7422 WREG32(DC_HPD4_INT_CONTROL, tmp);
7425 tmp = RREG32(DC_HPD5_INT_CONTROL);
7426 tmp |= DC_HPDx_RX_INT_ACK;
7427 WREG32(DC_HPD5_INT_CONTROL, tmp);
7430 tmp = RREG32(DC_HPD6_INT_CONTROL);
7431 tmp |= DC_HPDx_RX_INT_ACK;
7432 WREG32(DC_HPD6_INT_CONTROL, tmp);
7494 u32 wptr, tmp;
7510 tmp = RREG32(IH_RB_CNTL);
7511 tmp |= IH_WPTR_OVERFLOW_CLEAR;
7512 WREG32(IH_RB_CNTL, tmp);
8749 u32 tmp = 0;
8774 tmp |= (FMT_FRAME_RANDOM_ENABLE | FMT_HIGHPASS_RANDOM_ENABLE |
8777 tmp |= (FMT_TRUNCATE_EN | FMT_TRUNCATE_DEPTH(0));
8782 tmp |= (FMT_FRAME_RANDOM_ENABLE | FMT_HIGHPASS_RANDOM_ENABLE |
8786 tmp |= (FMT_TRUNCATE_EN | FMT_TRUNCATE_DEPTH(1));
8791 tmp |= (FMT_FRAME_RANDOM_ENABLE | FMT_HIGHPASS_RANDOM_ENABLE |
8795 tmp |= (FMT_TRUNCATE_EN | FMT_TRUNCATE_DEPTH(2));
8802 WREG32(FMT_BIT_DEPTH_CONTROL + radeon_crtc->crtc_offset, tmp);
8822 u32 tmp, buffer_alloc, i;
8834 tmp = 1;
8837 tmp = 2;
8840 tmp = 0;
8844 tmp = 0;
8848 tmp = 1;
8853 LB_MEMORY_CONFIG(tmp) | LB_MEMORY_SIZE(0x6B0));
8865 switch (tmp) {
8891 u32 tmp = RREG32(MC_SHARED_CHMAP);
8893 switch ((tmp & NOOFCHAN_MASK) >> NOOFCHAN_SHIFT) {
9123 u32 tmp, dmif_size = 12288;
9142 tmp = div_u64((u64) dmif_size * (u64) wm->disp_clk, mc_latency + 512);
9143 tmp = min(dfixed_trunc(a), tmp);
9145 lb_fill_bw = min(tmp, wm->disp_clk * wm->bytes_per_pixel / 1000);
9256 u32 tmp, wm_mask;
9351 tmp = wm_mask;
9352 tmp &= ~LATENCY_WATERMARK_MASK(3);
9353 tmp |= LATENCY_WATERMARK_MASK(1);
9354 WREG32(DPG_WATERMARK_MASK_CONTROL + radeon_crtc->crtc_offset, tmp);
9359 tmp = RREG32(DPG_WATERMARK_MASK_CONTROL + radeon_crtc->crtc_offset);
9360 tmp &= ~LATENCY_WATERMARK_MASK(3);
9361 tmp |= LATENCY_WATERMARK_MASK(2);
9362 WREG32(DPG_WATERMARK_MASK_CONTROL + radeon_crtc->crtc_offset, tmp);
9430 uint32_t tmp;
9437 tmp = RREG32_SMC(cntl_reg);
9438 tmp &= ~(DCLK_DIR_CNTL_EN|DCLK_DIVIDER_MASK);
9439 tmp |= dividers.post_divider;
9440 WREG32_SMC(cntl_reg, tmp);
9469 u32 tmp;
9484 tmp = RREG32_SMC(CG_ECLK_CNTL);
9485 tmp &= ~(ECLK_DIR_CNTL_EN|ECLK_DIVIDER_MASK);
9486 tmp |= dividers.post_divider;
9487 WREG32_SMC(CG_ECLK_CNTL, tmp);
9553 u32 max_lw, current_lw, tmp;
9558 tmp = RREG32_PCIE_PORT(PCIE_LC_STATUS1);
9559 max_lw = (tmp & LC_DETECTED_LINK_WIDTH_MASK) >> LC_DETECTED_LINK_WIDTH_SHIFT;
9560 current_lw = (tmp & LC_OPERATING_LINK_WIDTH_MASK) >> LC_OPERATING_LINK_WIDTH_SHIFT;
9563 tmp = RREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL);
9564 if (tmp & LC_RENEGOTIATION_SUPPORT) {
9565 tmp &= ~(LC_LINK_WIDTH_MASK | LC_UPCONFIGURE_DIS);
9566 tmp |= (max_lw << LC_LINK_WIDTH_SHIFT);
9567 tmp |= LC_UPCONFIGURE_SUPPORT | LC_RENEGOTIATE_EN | LC_RECONFIG_NOW;
9568 WREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL, tmp);
9592 tmp = RREG32_PCIE_PORT(PCIE_LC_CNTL4);
9593 tmp |= LC_SET_QUIESCE;
9594 WREG32_PCIE_PORT(PCIE_LC_CNTL4, tmp);
9596 tmp = RREG32_PCIE_PORT(PCIE_LC_CNTL4);
9597 tmp |= LC_REDO_EQ;
9598 WREG32_PCIE_PORT(PCIE_LC_CNTL4, tmp);
9636 tmp = RREG32_PCIE_PORT(PCIE_LC_CNTL4);
9637 tmp &= ~LC_SET_QUIESCE;
9638 WREG32_PCIE_PORT(PCIE_LC_CNTL4, tmp);