Lines Matching defs:queue_state
4504 struct hqd_registers queue_state;
4625 mqd->queue_state.cp_hqd_pq_doorbell_control =
4628 mqd->queue_state.cp_hqd_pq_doorbell_control |= DOORBELL_EN;
4630 mqd->queue_state.cp_hqd_pq_doorbell_control &= ~DOORBELL_EN;
4632 mqd->queue_state.cp_hqd_pq_doorbell_control);
4635 mqd->queue_state.cp_hqd_dequeue_request = 0;
4636 mqd->queue_state.cp_hqd_pq_rptr = 0;
4637 mqd->queue_state.cp_hqd_pq_wptr= 0;
4645 WREG32(CP_HQD_DEQUEUE_REQUEST, mqd->queue_state.cp_hqd_dequeue_request);
4646 WREG32(CP_HQD_PQ_RPTR, mqd->queue_state.cp_hqd_pq_rptr);
4647 WREG32(CP_HQD_PQ_WPTR, mqd->queue_state.cp_hqd_pq_wptr);
4651 mqd->queue_state.cp_mqd_base_addr = mqd_gpu_addr & 0xfffffffc;
4652 mqd->queue_state.cp_mqd_base_addr_hi = upper_32_bits(mqd_gpu_addr);
4653 WREG32(CP_MQD_BASE_ADDR, mqd->queue_state.cp_mqd_base_addr);
4654 WREG32(CP_MQD_BASE_ADDR_HI, mqd->queue_state.cp_mqd_base_addr_hi);
4656 mqd->queue_state.cp_mqd_control = RREG32(CP_MQD_CONTROL);
4657 mqd->queue_state.cp_mqd_control &= ~MQD_VMID_MASK;
4658 WREG32(CP_MQD_CONTROL, mqd->queue_state.cp_mqd_control);
4662 mqd->queue_state.cp_hqd_pq_base = hqd_gpu_addr;
4663 mqd->queue_state.cp_hqd_pq_base_hi = upper_32_bits(hqd_gpu_addr);
4664 WREG32(CP_HQD_PQ_BASE, mqd->queue_state.cp_hqd_pq_base);
4665 WREG32(CP_HQD_PQ_BASE_HI, mqd->queue_state.cp_hqd_pq_base_hi);
4668 mqd->queue_state.cp_hqd_pq_control = RREG32(CP_HQD_PQ_CONTROL);
4669 mqd->queue_state.cp_hqd_pq_control &=
4672 mqd->queue_state.cp_hqd_pq_control |=
4674 mqd->queue_state.cp_hqd_pq_control |=
4677 mqd->queue_state.cp_hqd_pq_control |= BUF_SWAP_32BIT;
4679 mqd->queue_state.cp_hqd_pq_control &=
4681 mqd->queue_state.cp_hqd_pq_control |=
4683 WREG32(CP_HQD_PQ_CONTROL, mqd->queue_state.cp_hqd_pq_control);
4690 mqd->queue_state.cp_hqd_pq_wptr_poll_addr = wb_gpu_addr & 0xfffffffc;
4691 mqd->queue_state.cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff;
4692 WREG32(CP_HQD_PQ_WPTR_POLL_ADDR, mqd->queue_state.cp_hqd_pq_wptr_poll_addr);
4694 mqd->queue_state.cp_hqd_pq_wptr_poll_addr_hi);
4701 mqd->queue_state.cp_hqd_pq_rptr_report_addr = wb_gpu_addr & 0xfffffffc;
4702 mqd->queue_state.cp_hqd_pq_rptr_report_addr_hi =
4705 mqd->queue_state.cp_hqd_pq_rptr_report_addr);
4707 mqd->queue_state.cp_hqd_pq_rptr_report_addr_hi);
4711 mqd->queue_state.cp_hqd_pq_doorbell_control =
4713 mqd->queue_state.cp_hqd_pq_doorbell_control &= ~DOORBELL_OFFSET_MASK;
4714 mqd->queue_state.cp_hqd_pq_doorbell_control |=
4716 mqd->queue_state.cp_hqd_pq_doorbell_control |= DOORBELL_EN;
4717 mqd->queue_state.cp_hqd_pq_doorbell_control &=
4721 mqd->queue_state.cp_hqd_pq_doorbell_control = 0;
4724 mqd->queue_state.cp_hqd_pq_doorbell_control);
4728 mqd->queue_state.cp_hqd_pq_wptr = rdev->ring[idx].wptr;
4729 WREG32(CP_HQD_PQ_WPTR, mqd->queue_state.cp_hqd_pq_wptr);
4730 mqd->queue_state.cp_hqd_pq_rptr = RREG32(CP_HQD_PQ_RPTR);
4733 mqd->queue_state.cp_hqd_vmid = 0;
4734 WREG32(CP_HQD_VMID, mqd->queue_state.cp_hqd_vmid);
4737 mqd->queue_state.cp_hqd_active = 1;
4738 WREG32(CP_HQD_ACTIVE, mqd->queue_state.cp_hqd_active);