Lines Matching defs:pipe
1842 * @pipe: pipe
1848 * me/pipe/queue combination.
1851 u32 me, u32 pipe, u32 queue, u32 vmid)
1853 u32 srbm_gfx_cntl = (PIPEID(pipe & 0x3) |
3020 DRM_ERROR("unknown num pipe config: 0x%x\n", num_pipe_configs);
3516 ref_and_mask = CP2 << ring->pipe;
3519 ref_and_mask = CP6 << ring->pipe;
3557 * event down the pipe with seq one below.
3570 /* Then send the real EOP event down the pipe. */
3861 * Each MEC supports 4 compute pipes and each pipe supports 8 queues.
4158 cik_srbm_select(rdev, ring->me, ring->pipe, ring->queue, 0);
4177 cik_srbm_select(rdev, ring->me, ring->pipe, ring->queue, 0);
4199 cik_srbm_select(rdev, ring->me, ring->pipe, ring->queue, 0);
4544 int pipe = (i < 4) ? i : (i - 4);
4546 cik_srbm_select(rdev, me, pipe, 0, 0);
4616 rdev->ring[idx].pipe,
7080 switch (ring->pipe) {
7094 DRM_DEBUG("si_irq_set: sw int cp1 invalid pipe %d\n", ring->pipe);
7098 switch (ring->pipe) {
7112 DRM_DEBUG("si_irq_set: sw int cp1 invalid pipe %d\n", ring->pipe);
7123 switch (ring->pipe) {
7137 DRM_DEBUG("si_irq_set: sw int cp2 invalid pipe %d\n", ring->pipe);
7141 switch (ring->pipe) {
7155 DRM_DEBUG("si_irq_set: sw int cp2 invalid pipe %d\n", ring->pipe);
7951 if ((cp1_ring->me == me_id) & (cp1_ring->pipe == pipe_id))
7953 if ((cp2_ring->me == me_id) & (cp2_ring->pipe == pipe_id))
8427 ring->pipe = 0; /* first pipe */
8439 ring->pipe = 0; /* first pipe */
8928 u32 lb_size; /* line buffer allocated to pipe */
9118 u32 dc_latency = 40000000 / wm->disp_clk; /* dc pipe latency */