Lines Matching defs:enable
139 extern void cik_sdma_enable(struct radeon_device *rdev, bool enable);
141 extern void vce_v2_0_enable_mgcg(struct radeon_device *rdev, bool enable);
150 bool enable);
3866 * cik_cp_gfx_enable - enable/disable the gfx CP MEs
3869 * @enable: enable or disable the MEs
3873 static void cik_cp_gfx_enable(struct radeon_device *rdev, bool enable)
3875 if (enable)
4220 * cik_cp_compute_enable - enable/disable the compute CP MEs
4223 * @enable: enable or disable the MEs
4227 static void cik_cp_compute_enable(struct radeon_device *rdev, bool enable)
4229 if (enable)
4624 /* enable doorbell? */
4709 /* enable the doorbell if requested */
4755 static void cik_cp_enable(struct radeon_device *rdev, bool enable)
4757 cik_cp_gfx_enable(rdev, enable);
4758 cik_cp_compute_enable(rdev, enable);
5419 * cik_pcie_gart_enable - gart enable
5486 /* enable context1-15 */
5769 bool enable)
5773 if (enable)
5780 static void cik_enable_lbpw(struct radeon_device *rdev, bool enable)
5785 if (enable)
6001 static void cik_enable_cgcg(struct radeon_device *rdev, bool enable)
6007 if (enable && (rdev->cg_flags & RADEON_CG_SUPPORT_GFX_CGCG)) {
6037 static void cik_enable_mgcg(struct radeon_device *rdev, bool enable)
6041 if (enable && (rdev->cg_flags & RADEON_CG_SUPPORT_GFX_MGCG)) {
6131 bool enable)
6138 if (enable && (rdev->cg_flags & RADEON_CG_SUPPORT_MC_LS))
6148 bool enable)
6155 if (enable && (rdev->cg_flags & RADEON_CG_SUPPORT_MC_MGCG))
6165 bool enable)
6169 if (enable && (rdev->cg_flags & RADEON_CG_SUPPORT_SDMA_MGCG)) {
6186 bool enable)
6190 if (enable && (rdev->cg_flags & RADEON_CG_SUPPORT_SDMA_LS)) {
6214 bool enable)
6218 if (enable && (rdev->cg_flags & RADEON_CG_SUPPORT_UVD_MGCG)) {
6240 bool enable)
6246 if (enable && (rdev->cg_flags & RADEON_CG_SUPPORT_BIF_LS))
6258 bool enable)
6264 if (enable && (rdev->cg_flags & RADEON_CG_SUPPORT_HDP_MGCG))
6274 bool enable)
6280 if (enable && (rdev->cg_flags & RADEON_CG_SUPPORT_HDP_LS))
6290 u32 block, bool enable)
6296 if (enable) {
6308 cik_enable_mc_mgcg(rdev, enable);
6309 cik_enable_mc_ls(rdev, enable);
6314 cik_enable_sdma_mgcg(rdev, enable);
6315 cik_enable_sdma_mgls(rdev, enable);
6319 cik_enable_bif_mgls(rdev, enable);
6324 cik_enable_uvd_mgcg(rdev, enable);
6328 cik_enable_hdp_mgcg(rdev, enable);
6329 cik_enable_hdp_ls(rdev, enable);
6333 vce_v2_0_enable_mgcg(rdev, enable);
6364 bool enable)
6369 if (enable && (rdev->pg_flags & RADEON_PG_SUPPORT_RLC_SMU_HS))
6378 bool enable)
6383 if (enable && (rdev->pg_flags & RADEON_PG_SUPPORT_RLC_SMU_HS))
6391 static void cik_enable_cp_pg(struct radeon_device *rdev, bool enable)
6396 if (enable && (rdev->pg_flags & RADEON_PG_SUPPORT_CP))
6404 static void cik_enable_gds_pg(struct radeon_device *rdev, bool enable)
6409 if (enable && (rdev->pg_flags & RADEON_PG_SUPPORT_GDS))
6506 bool enable)
6510 if (enable && (rdev->pg_flags & RADEON_PG_SUPPORT_GFX_PG)) {
6592 bool enable)
6597 if (enable && (rdev->pg_flags & RADEON_PG_SUPPORT_GFX_SMG))
6606 bool enable)
6611 if (enable && (rdev->pg_flags & RADEON_PG_SUPPORT_GFX_DMG))
6671 static void cik_update_gfx_pg(struct radeon_device *rdev, bool enable)
6673 cik_enable_gfx_cgpg(rdev, enable);
6674 cik_enable_gfx_static_mgpg(rdev, enable);
6675 cik_enable_gfx_dynamic_mgpg(rdev, enable);
6863 * Clear all interrupt enable bits used by the driver (CIK).
6936 * cik_irq_init - init and enable the interrupt ring
6941 * enable the RLC, disable interrupts, enable the IH
6942 * ring buffer and enable it (CIK).
7011 /* enable irqs */
7018 * cik_irq_set - enable/disable interrupt sources
7037 WARN(1, "Can't enable IRQ/MSI because no handler is installed\n");
7040 /* don't enable anything if the ih is disabled */
7071 /* enable CP interrupts on all rings */
8298 /* enable pcie gen2/3 link */
8300 /* enable aspm */
8828 * to enable based on the display width. For display widths larger