Lines Matching defs:data
1883 (const struct mc_firmware_header_v1_0 *)rdev->mc_fw->data;
1889 (rdev->mc_fw->data + le32_to_cpu(hdr->io_debug_array_offset_bytes));
1892 (rdev->mc_fw->data + le32_to_cpu(hdr->header.ucode_array_offset_bytes));
1908 fw_data = (const __be32 *)rdev->mc_fw->data;
3038 u32 data = INSTANCE_BROADCAST_WRITES;
3041 data |= SH_BROADCAST_WRITES | SE_BROADCAST_WRITES;
3043 data |= SE_BROADCAST_WRITES | SH_INDEX(sh_num);
3045 data |= SH_BROADCAST_WRITES | SE_INDEX(se_num);
3047 data |= SH_INDEX(sh_num) | SE_INDEX(se_num);
3048 WREG32(GRBM_GFX_INDEX, data);
3085 u32 data, mask;
3087 data = RREG32(CC_RB_BACKEND_DISABLE);
3088 if (data & 1)
3089 data &= BACKEND_DISABLE_MASK;
3091 data = 0;
3092 data |= RREG32(GC_USER_RB_BACKEND_DISABLE);
3094 data >>= BACKEND_DISABLE_SHIFT;
3098 return data & mask;
3116 u32 data, mask;
3123 data = cik_get_rb_disabled(rdev, max_rb_num_per_se, sh_per_se);
3125 disabled_rbs |= data << ((i * sh_per_se + j) * HAWAII_RB_BITMAP_WIDTH_PER_SH);
3127 disabled_rbs |= data << ((i * sh_per_se + j) * CIK_RB_BITMAP_WIDTH_PER_SH);
3143 data = 0;
3148 data |= PKR_MAP(RASTER_CONFIG_RB_MAP_3);
3150 data |= PKR_MAP(RASTER_CONFIG_RB_MAP_0);
3153 data |= (RASTER_CONFIG_RB_MAP_0 << (i * sh_per_se + j) * 2);
3156 data |= (RASTER_CONFIG_RB_MAP_3 << (i * sh_per_se + j) * 2);
3160 data |= (RASTER_CONFIG_RB_MAP_2 << (i * sh_per_se + j) * 2);
3165 WREG32(PA_SC_RASTER_CONFIG, data);
3905 (const struct gfx_firmware_header_v1_0 *)rdev->pfp_fw->data;
3907 (const struct gfx_firmware_header_v1_0 *)rdev->ce_fw->data;
3909 (const struct gfx_firmware_header_v1_0 *)rdev->me_fw->data;
3919 (rdev->pfp_fw->data + le32_to_cpu(pfp_hdr->header.ucode_array_offset_bytes));
3928 (rdev->ce_fw->data + le32_to_cpu(ce_hdr->header.ucode_array_offset_bytes));
3937 (rdev->me_fw->data + le32_to_cpu(me_hdr->header.ucode_array_offset_bytes));
3948 fw_data = (const __be32 *)rdev->pfp_fw->data;
3955 fw_data = (const __be32 *)rdev->ce_fw->data;
3962 fw_data = (const __be32 *)rdev->me_fw->data;
4267 (const struct gfx_firmware_header_v1_0 *)rdev->mec_fw->data;
4275 (rdev->mec_fw->data + le32_to_cpu(mec_hdr->header.ucode_array_offset_bytes));
4285 (const struct gfx_firmware_header_v1_0 *)rdev->mec2_fw->data;
4288 (rdev->mec2_fw->data +
4300 fw_data = (const __be32 *)rdev->mec_fw->data;
4308 fw_data = (const __be32 *)rdev->mec_fw->data;
5828 u32 data, orig;
5830 orig = data = RREG32(RLC_CNTL);
5832 if (data & RLC_ENABLE) {
5835 data &= ~RLC_ENABLE;
5836 WREG32(RLC_CNTL, data);
5952 (const struct rlc_firmware_header_v1_0 *)rdev->rlc_fw->data;
5954 (rdev->rlc_fw->data + le32_to_cpu(hdr->header.ucode_array_offset_bytes));
5983 fw_data = (const __be32 *)rdev->rlc_fw->data;
6003 u32 data, orig, tmp, tmp2;
6005 orig = data = RREG32(RLC_CGCG_CGLS_CTRL);
6020 data |= CGCG_EN | CGLS_EN;
6029 data &= ~(CGCG_EN | CGLS_EN);
6032 if (orig != data)
6033 WREG32(RLC_CGCG_CGLS_CTRL, data);
6039 u32 data, orig, tmp = 0;
6044 orig = data = RREG32(CP_MEM_SLP_CNTL);
6045 data |= CP_MEM_LS_EN;
6046 if (orig != data)
6047 WREG32(CP_MEM_SLP_CNTL, data);
6051 orig = data = RREG32(RLC_CGTT_MGCG_OVERRIDE);
6052 data |= 0x00000001;
6053 data &= 0xfffffffd;
6054 if (orig != data)
6055 WREG32(RLC_CGTT_MGCG_OVERRIDE, data);
6062 data = BPM_ADDR_MASK | MGCG_OVERRIDE_0;
6063 WREG32(RLC_SERDES_WR_CTRL, data);
6068 orig = data = RREG32(CGTS_SM_CTRL_REG);
6069 data &= ~SM_MODE_MASK;
6070 data |= SM_MODE(0x2);
6071 data |= SM_MODE_ENABLE;
6072 data &= ~CGTS_OVERRIDE;
6075 data &= ~CGTS_LS_OVERRIDE;
6076 data &= ~ON_MONITOR_ADD_MASK;
6077 data |= ON_MONITOR_ADD_EN;
6078 data |= ON_MONITOR_ADD(0x96);
6079 if (orig != data)
6080 WREG32(CGTS_SM_CTRL_REG, data);
6083 orig = data = RREG32(RLC_CGTT_MGCG_OVERRIDE);
6084 data |= 0x00000003;
6085 if (orig != data)
6086 WREG32(RLC_CGTT_MGCG_OVERRIDE, data);
6088 data = RREG32(RLC_MEM_SLP_CNTL);
6089 if (data & RLC_MEM_LS_EN) {
6090 data &= ~RLC_MEM_LS_EN;
6091 WREG32(RLC_MEM_SLP_CNTL, data);
6094 data = RREG32(CP_MEM_SLP_CNTL);
6095 if (data & CP_MEM_LS_EN) {
6096 data &= ~CP_MEM_LS_EN;
6097 WREG32(CP_MEM_SLP_CNTL, data);
6100 orig = data = RREG32(CGTS_SM_CTRL_REG);
6101 data |= CGTS_OVERRIDE | CGTS_LS_OVERRIDE;
6102 if (orig != data)
6103 WREG32(CGTS_SM_CTRL_REG, data);
6110 data = BPM_ADDR_MASK | MGCG_OVERRIDE_1;
6111 WREG32(RLC_SERDES_WR_CTRL, data);
6134 u32 orig, data;
6137 orig = data = RREG32(mc_cg_registers[i]);
6139 data |= MC_LS_ENABLE;
6141 data &= ~MC_LS_ENABLE;
6142 if (data != orig)
6143 WREG32(mc_cg_registers[i], data);
6151 u32 orig, data;
6154 orig = data = RREG32(mc_cg_registers[i]);
6156 data |= MC_CG_ENABLE;
6158 data &= ~MC_CG_ENABLE;
6159 if (data != orig)
6160 WREG32(mc_cg_registers[i], data);
6167 u32 orig, data;
6173 orig = data = RREG32(SDMA0_CLK_CTRL + SDMA0_REGISTER_OFFSET);
6174 data |= 0xff000000;
6175 if (data != orig)
6176 WREG32(SDMA0_CLK_CTRL + SDMA0_REGISTER_OFFSET, data);
6178 orig = data = RREG32(SDMA0_CLK_CTRL + SDMA1_REGISTER_OFFSET);
6179 data |= 0xff000000;
6180 if (data != orig)
6181 WREG32(SDMA0_CLK_CTRL + SDMA1_REGISTER_OFFSET, data);
6188 u32 orig, data;
6191 orig = data = RREG32(SDMA0_POWER_CNTL + SDMA0_REGISTER_OFFSET);
6192 data |= 0x100;
6193 if (orig != data)
6194 WREG32(SDMA0_POWER_CNTL + SDMA0_REGISTER_OFFSET, data);
6196 orig = data = RREG32(SDMA0_POWER_CNTL + SDMA1_REGISTER_OFFSET);
6197 data |= 0x100;
6198 if (orig != data)
6199 WREG32(SDMA0_POWER_CNTL + SDMA1_REGISTER_OFFSET, data);
6201 orig = data = RREG32(SDMA0_POWER_CNTL + SDMA0_REGISTER_OFFSET);
6202 data &= ~0x100;
6203 if (orig != data)
6204 WREG32(SDMA0_POWER_CNTL + SDMA0_REGISTER_OFFSET, data);
6206 orig = data = RREG32(SDMA0_POWER_CNTL + SDMA1_REGISTER_OFFSET);
6207 data &= ~0x100;
6208 if (orig != data)
6209 WREG32(SDMA0_POWER_CNTL + SDMA1_REGISTER_OFFSET, data);
6216 u32 orig, data;
6219 data = RREG32_UVD_CTX(UVD_CGC_MEM_CTRL);
6220 data = 0xfff;
6221 WREG32_UVD_CTX(UVD_CGC_MEM_CTRL, data);
6223 orig = data = RREG32(UVD_CGC_CTRL);
6224 data |= DCM;
6225 if (orig != data)
6226 WREG32(UVD_CGC_CTRL, data);
6228 data = RREG32_UVD_CTX(UVD_CGC_MEM_CTRL);
6229 data &= ~0xfff;
6230 WREG32_UVD_CTX(UVD_CGC_MEM_CTRL, data);
6232 orig = data = RREG32(UVD_CGC_CTRL);
6233 data &= ~DCM;
6234 if (orig != data)
6235 WREG32(UVD_CGC_CTRL, data);
6242 u32 orig, data;
6244 orig = data = RREG32_PCIE_PORT(PCIE_CNTL2);
6247 data |= SLV_MEM_LS_EN | MST_MEM_LS_EN |
6250 data &= ~(SLV_MEM_LS_EN | MST_MEM_LS_EN |
6253 if (orig != data)
6254 WREG32_PCIE_PORT(PCIE_CNTL2, data);
6260 u32 orig, data;
6262 orig = data = RREG32(HDP_HOST_PATH_CNTL);
6265 data &= ~CLOCK_GATING_DIS;
6267 data |= CLOCK_GATING_DIS;
6269 if (orig != data)
6270 WREG32(HDP_HOST_PATH_CNTL, data);
6276 u32 orig, data;
6278 orig = data = RREG32(HDP_MEM_POWER_LS);
6281 data |= HDP_LS_ENABLE;
6283 data &= ~HDP_LS_ENABLE;
6285 if (orig != data)
6286 WREG32(HDP_MEM_POWER_LS, data);
6366 u32 data, orig;
6368 orig = data = RREG32(RLC_PG_CNTL);
6370 data |= SMU_CLK_SLOWDOWN_ON_PU_ENABLE;
6372 data &= ~SMU_CLK_SLOWDOWN_ON_PU_ENABLE;
6373 if (orig != data)
6374 WREG32(RLC_PG_CNTL, data);
6380 u32 data, orig;
6382 orig = data = RREG32(RLC_PG_CNTL);
6384 data |= SMU_CLK_SLOWDOWN_ON_PD_ENABLE;
6386 data &= ~SMU_CLK_SLOWDOWN_ON_PD_ENABLE;
6387 if (orig != data)
6388 WREG32(RLC_PG_CNTL, data);
6393 u32 data, orig;
6395 orig = data = RREG32(RLC_PG_CNTL);
6397 data &= ~DISABLE_CP_PG;
6399 data |= DISABLE_CP_PG;
6400 if (orig != data)
6401 WREG32(RLC_PG_CNTL, data);
6406 u32 data, orig;
6408 orig = data = RREG32(RLC_PG_CNTL);
6410 data &= ~DISABLE_GDS_PG;
6412 data |= DISABLE_GDS_PG;
6413 if (orig != data)
6414 WREG32(RLC_PG_CNTL, data);
6442 hdr = (const struct gfx_firmware_header_v1_0 *)rdev->ce_fw->data;
6444 (rdev->ce_fw->data + le32_to_cpu(hdr->header.ucode_array_offset_bytes));
6448 hdr = (const struct gfx_firmware_header_v1_0 *)rdev->pfp_fw->data;
6450 (rdev->pfp_fw->data + le32_to_cpu(hdr->header.ucode_array_offset_bytes));
6454 hdr = (const struct gfx_firmware_header_v1_0 *)rdev->me_fw->data;
6456 (rdev->me_fw->data + le32_to_cpu(hdr->header.ucode_array_offset_bytes));
6460 hdr = (const struct gfx_firmware_header_v1_0 *)rdev->mec_fw->data;
6462 (rdev->mec_fw->data + le32_to_cpu(hdr->header.ucode_array_offset_bytes));
6466 hdr = (const struct gfx_firmware_header_v1_0 *)rdev->mec2_fw->data;
6468 (rdev->mec2_fw->data + le32_to_cpu(hdr->header.ucode_array_offset_bytes));
6483 fw_data = (const __be32 *)rdev->ce_fw->data;
6486 fw_data = (const __be32 *)rdev->pfp_fw->data;
6489 fw_data = (const __be32 *)rdev->me_fw->data;
6492 fw_data = (const __be32 *)rdev->mec_fw->data;
6508 u32 data, orig;
6511 orig = data = RREG32(RLC_PG_CNTL);
6512 data |= GFX_PG_ENABLE;
6513 if (orig != data)
6514 WREG32(RLC_PG_CNTL, data);
6516 orig = data = RREG32(RLC_AUTO_PG_CTRL);
6517 data |= AUTO_PG_EN;
6518 if (orig != data)
6519 WREG32(RLC_AUTO_PG_CTRL, data);
6521 orig = data = RREG32(RLC_PG_CNTL);
6522 data &= ~GFX_PG_ENABLE;
6523 if (orig != data)
6524 WREG32(RLC_PG_CNTL, data);
6526 orig = data = RREG32(RLC_AUTO_PG_CTRL);
6527 data &= ~AUTO_PG_EN;
6528 if (orig != data)
6529 WREG32(RLC_AUTO_PG_CTRL, data);
6531 data = RREG32(DB_RENDER_CONTROL);
6594 u32 data, orig;
6596 orig = data = RREG32(RLC_PG_CNTL);
6598 data |= STATIC_PER_CU_PG_ENABLE;
6600 data &= ~STATIC_PER_CU_PG_ENABLE;
6601 if (orig != data)
6602 WREG32(RLC_PG_CNTL, data);
6608 u32 data, orig;
6610 orig = data = RREG32(RLC_PG_CNTL);
6612 data |= DYN_PER_CU_PG_ENABLE;
6614 data &= ~DYN_PER_CU_PG_ENABLE;
6615 if (orig != data)
6616 WREG32(RLC_PG_CNTL, data);
6624 u32 data, orig;
6643 orig = data = RREG32(RLC_PG_CNTL);
6644 data |= GFX_PG_SRC;
6645 if (orig != data)
6646 WREG32(RLC_PG_CNTL, data);
6651 data = RREG32(CP_RB_WPTR_POLL_CNTL);
6652 data &= ~IDLE_POLL_COUNT_MASK;
6653 data |= IDLE_POLL_COUNT(0x60);
6654 WREG32(CP_RB_WPTR_POLL_CNTL, data);
6656 data = 0x10101010;
6657 WREG32(RLC_PG_DELAY, data);
6659 data = RREG32(RLC_PG_DELAY_2);
6660 data &= ~0xff;
6661 data |= 0x3;
6662 WREG32(RLC_PG_DELAY_2, data);
6664 data = RREG32(RLC_AUTO_PG_CTRL);
6665 data &= ~GRBM_REG_SGIT_MASK;
6666 data |= GRBM_REG_SGIT(0x700);
6667 WREG32(RLC_AUTO_PG_CTRL, data);
7521 * [59:32] - interrupt source data
7577 /* Order reading of wptr vs. reading of IH ring data */
8918 u32 yclk; /* bandwidth per dram data pin in kHz */
8935 * @wm: watermark calculation data
8964 * @wm: watermark calculation data
8991 * dce8_data_return_bandwidth - get the data return bandwidth
8993 * @wm: watermark calculation data
8995 * Calculate the data return bandwidth used for display (CIK).
8997 * Returns the data return bandwidth in MBytes/s
9022 * @wm: watermark calculation data
9053 * @wm: watermark calculation data
9072 * @wm: watermark calculation data
9105 * @wm: watermark calculation data
9165 * @wm: watermark calculation data
9185 * @wm: watermark calculation data
9204 * @wm: watermark calculation data
9672 u32 data, orig;
9686 orig = data = RREG32_PCIE_PORT(PCIE_LC_N_FTS_CNTL);
9687 data &= ~LC_XMIT_N_FTS_MASK;
9688 data |= LC_XMIT_N_FTS(0x24) | LC_XMIT_N_FTS_OVERRIDE_EN;
9689 if (orig != data)
9690 WREG32_PCIE_PORT(PCIE_LC_N_FTS_CNTL, data);
9692 orig = data = RREG32_PCIE_PORT(PCIE_LC_CNTL3);
9693 data |= LC_GO_TO_RECOVERY;
9694 if (orig != data)
9695 WREG32_PCIE_PORT(PCIE_LC_CNTL3, data);
9697 orig = data = RREG32_PCIE_PORT(PCIE_P_CNTL);
9698 data |= P_IGNORE_EDB_ERR;
9699 if (orig != data)
9700 WREG32_PCIE_PORT(PCIE_P_CNTL, data);
9702 orig = data = RREG32_PCIE_PORT(PCIE_LC_CNTL);
9703 data &= ~(LC_L0S_INACTIVITY_MASK | LC_L1_INACTIVITY_MASK);
9704 data |= LC_PMI_TO_L1_DIS;
9706 data |= LC_L0S_INACTIVITY(7);
9709 data |= LC_L1_INACTIVITY(7);
9710 data &= ~LC_PMI_TO_L1_DIS;
9711 if (orig != data)
9712 WREG32_PCIE_PORT(PCIE_LC_CNTL, data);
9717 orig = data = RREG32_PCIE_PORT(PB0_PIF_PWRDOWN_0);
9718 data &= ~(PLL_POWER_STATE_IN_OFF_0_MASK | PLL_POWER_STATE_IN_TXS2_0_MASK);
9719 data |= PLL_POWER_STATE_IN_OFF_0(7) | PLL_POWER_STATE_IN_TXS2_0(7);
9720 if (orig != data)
9721 WREG32_PCIE_PORT(PB0_PIF_PWRDOWN_0, data);
9723 orig = data = RREG32_PCIE_PORT(PB0_PIF_PWRDOWN_1);
9724 data &= ~(PLL_POWER_STATE_IN_OFF_1_MASK | PLL_POWER_STATE_IN_TXS2_1_MASK);
9725 data |= PLL_POWER_STATE_IN_OFF_1(7) | PLL_POWER_STATE_IN_TXS2_1(7);
9726 if (orig != data)
9727 WREG32_PCIE_PORT(PB0_PIF_PWRDOWN_1, data);
9729 orig = data = RREG32_PCIE_PORT(PB1_PIF_PWRDOWN_0);
9730 data &= ~(PLL_POWER_STATE_IN_OFF_0_MASK | PLL_POWER_STATE_IN_TXS2_0_MASK);
9731 data |= PLL_POWER_STATE_IN_OFF_0(7) | PLL_POWER_STATE_IN_TXS2_0(7);
9732 if (orig != data)
9733 WREG32_PCIE_PORT(PB1_PIF_PWRDOWN_0, data);
9735 orig = data = RREG32_PCIE_PORT(PB1_PIF_PWRDOWN_1);
9736 data &= ~(PLL_POWER_STATE_IN_OFF_1_MASK | PLL_POWER_STATE_IN_TXS2_1_MASK);
9737 data |= PLL_POWER_STATE_IN_OFF_1(7) | PLL_POWER_STATE_IN_TXS2_1(7);
9738 if (orig != data)
9739 WREG32_PCIE_PORT(PB1_PIF_PWRDOWN_1, data);
9741 orig = data = RREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL);
9742 data &= ~LC_DYN_LANES_PWR_STATE_MASK;
9743 data |= LC_DYN_LANES_PWR_STATE(3);
9744 if (orig != data)
9745 WREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL, data);
9761 orig = data = RREG32_PCIE_PORT(PCIE_LC_CNTL2);
9762 data |= LC_ALLOW_PDWN_IN_L1 | LC_ALLOW_PDWN_IN_L23;
9763 if (orig != data)
9764 WREG32_PCIE_PORT(PCIE_LC_CNTL2, data);
9766 orig = data = RREG32_SMC(THM_CLK_CNTL);
9767 data &= ~(CMON_CLK_SEL_MASK | TMON_CLK_SEL_MASK);
9768 data |= CMON_CLK_SEL(1) | TMON_CLK_SEL(1);
9769 if (orig != data)
9770 WREG32_SMC(THM_CLK_CNTL, data);
9772 orig = data = RREG32_SMC(MISC_CLK_CTRL);
9773 data &= ~(DEEP_SLEEP_CLK_SEL_MASK | ZCLK_SEL_MASK);
9774 data |= DEEP_SLEEP_CLK_SEL(1) | ZCLK_SEL(1);
9775 if (orig != data)
9776 WREG32_SMC(MISC_CLK_CTRL, data);
9778 orig = data = RREG32_SMC(CG_CLKPIN_CNTL);
9779 data &= ~BCLK_AS_XCLK;
9780 if (orig != data)
9781 WREG32_SMC(CG_CLKPIN_CNTL, data);
9783 orig = data = RREG32_SMC(CG_CLKPIN_CNTL_2);
9784 data &= ~FORCE_BIF_REFCLK_EN;
9785 if (orig != data)
9786 WREG32_SMC(CG_CLKPIN_CNTL_2, data);
9788 orig = data = RREG32_SMC(MPLL_BYPASSCLK_SEL);
9789 data &= ~MPLL_CLKOUT_SEL_MASK;
9790 data |= MPLL_CLKOUT_SEL(4);
9791 if (orig != data)
9792 WREG32_SMC(MPLL_BYPASSCLK_SEL, data);
9796 if (orig != data)
9797 WREG32_PCIE_PORT(PCIE_LC_CNTL, data);
9800 orig = data = RREG32_PCIE_PORT(PCIE_CNTL2);
9801 data |= SLV_MEM_LS_EN | MST_MEM_LS_EN | REPLAY_MEM_LS_EN;
9802 if (orig != data)
9803 WREG32_PCIE_PORT(PCIE_CNTL2, data);
9806 data = RREG32_PCIE_PORT(PCIE_LC_N_FTS_CNTL);
9807 if((data & LC_N_FTS_MASK) == LC_N_FTS_MASK) {
9808 data = RREG32_PCIE_PORT(PCIE_LC_STATUS1);
9809 if ((data & LC_REVERSE_XMIT) && (data & LC_REVERSE_RCVR)) {
9810 orig = data = RREG32_PCIE_PORT(PCIE_LC_CNTL);
9811 data &= ~LC_L0S_INACTIVITY_MASK;
9812 if (orig != data)
9813 WREG32_PCIE_PORT(PCIE_LC_CNTL, data);