Lines Matching refs:UvdLevel
2644 table->UvdLevel[count].VclkFrequency =
2646 table->UvdLevel[count].DclkFrequency =
2648 table->UvdLevel[count].MinVddc =
2650 table->UvdLevel[count].MinVddcPhases = 1;
2654 table->UvdLevel[count].VclkFrequency, false, ÷rs);
2658 table->UvdLevel[count].VclkDivider = (u8)dividers.post_divider;
2662 table->UvdLevel[count].DclkFrequency, false, ÷rs);
2666 table->UvdLevel[count].DclkDivider = (u8)dividers.post_divider;
2668 table->UvdLevel[count].VclkFrequency = cpu_to_be32(table->UvdLevel[count].VclkFrequency);
2669 table->UvdLevel[count].DclkFrequency = cpu_to_be32(table->UvdLevel[count].DclkFrequency);
2670 table->UvdLevel[count].MinVddc = cpu_to_be16(table->UvdLevel[count].MinVddc);