Lines Matching defs:tmp
860 u32 tmp;
871 tmp = RREG32_SMC(CG_THERMAL_INT);
872 tmp &= ~(CI_DIG_THERM_INTH_MASK | CI_DIG_THERM_INTL_MASK);
873 tmp |= CI_DIG_THERM_INTH(high_temp / 1000) |
875 WREG32_SMC(CG_THERMAL_INT, tmp);
879 tmp = RREG32_SMC(CG_THERMAL_CTRL);
880 tmp &= DIG_THERM_DPM_MASK;
881 tmp |= DIG_THERM_DPM(high_temp / 1000);
882 WREG32_SMC(CG_THERMAL_CTRL, tmp);
923 u32 tmp;
926 tmp = (RREG32_SMC(CG_FDO_CTRL2) & FDO_PWM_MODE_MASK) >> FDO_PWM_MODE_SHIFT;
927 pi->fan_ctrl_default_mode = tmp;
928 tmp = (RREG32_SMC(CG_FDO_CTRL2) & TMIN_MASK) >> TMIN_SHIFT;
929 pi->t_min = tmp;
933 tmp = RREG32_SMC(CG_FDO_CTRL2) & ~TMIN_MASK;
934 tmp |= TMIN(0);
935 WREG32_SMC(CG_FDO_CTRL2, tmp);
937 tmp = RREG32_SMC(CG_FDO_CTRL2) & ~FDO_PWM_MODE_MASK;
938 tmp |= FDO_PWM_MODE(mode);
939 WREG32_SMC(CG_FDO_CTRL2, tmp);
949 u32 reference_clock, tmp;
1002 tmp = (RREG32_SMC(CG_MULT_THERMAL_CTRL) & TEMP_SEL_MASK) >> TEMP_SEL_SHIFT;
1003 fan_table.TempSrc = (uint8_t)tmp;
1088 u32 tmp;
1111 tmp = RREG32_SMC(CG_FDO_CTRL0) & ~FDO_STATIC_DUTY_MASK;
1112 tmp |= FDO_STATIC_DUTY(duty);
1113 WREG32_SMC(CG_FDO_CTRL0, tmp);
1137 u32 tmp;
1142 tmp = RREG32_SMC(CG_FDO_CTRL2) & FDO_PWM_MODE_MASK;
1143 return (tmp >> FDO_PWM_MODE_SHIFT);
1171 u32 tach_period, tmp;
1188 tmp = RREG32_SMC(CG_TACH_CTRL) & ~TARGET_PERIOD_MASK;
1189 tmp |= TARGET_PERIOD(tach_period);
1190 WREG32_SMC(CG_TACH_CTRL, tmp);
1201 u32 tmp;
1204 tmp = RREG32_SMC(CG_FDO_CTRL2) & ~FDO_PWM_MODE_MASK;
1205 tmp |= FDO_PWM_MODE(pi->fan_ctrl_default_mode);
1206 WREG32_SMC(CG_FDO_CTRL2, tmp);
1208 tmp = RREG32_SMC(CG_FDO_CTRL2) & ~TMIN_MASK;
1209 tmp |= TMIN(pi->t_min);
1210 WREG32_SMC(CG_FDO_CTRL2, tmp);
1225 u32 tmp;
1228 tmp = RREG32_SMC(CG_TACH_CTRL) & ~EDGE_PER_REV_MASK;
1229 tmp |= EDGE_PER_REV(rdev->pm.fan_pulses_per_revolution -1);
1230 WREG32_SMC(CG_TACH_CTRL, tmp);
1233 tmp = RREG32_SMC(CG_FDO_CTRL2) & ~TACH_PWM_RESP_RATE_MASK;
1234 tmp |= TACH_PWM_RESP_RATE(0x28);
1235 WREG32_SMC(CG_FDO_CTRL2, tmp);
1293 u16 tmp;
1295 tmp = 45;
1296 table->FpsHighT = cpu_to_be16(tmp);
1298 tmp = 30;
1299 table->FpsLowT = cpu_to_be16(tmp);
1370 u32 tmp;
1395 tmp = RREG32_SMC(CG_THERMAL_CTRL);
1396 tmp &= DPM_EVENT_SRC_MASK;
1397 tmp |= DPM_EVENT_SRC(dpm_event_src);
1398 WREG32_SMC(CG_THERMAL_CTRL, tmp);
1401 tmp = RREG32_SMC(GENERAL_PWRMGT);
1403 tmp &= ~THERMAL_PROTECTION_DIS;
1405 tmp |= THERMAL_PROTECTION_DIS;
1406 WREG32_SMC(GENERAL_PWRMGT, tmp);
1408 tmp = RREG32_SMC(GENERAL_PWRMGT);
1409 tmp |= THERMAL_PROTECTION_DIS;
1410 WREG32_SMC(GENERAL_PWRMGT, tmp);
1516 u32 tmp;
1518 tmp = RREG32_SMC(GENERAL_PWRMGT);
1519 tmp |= GLOBAL_PWRMGT_EN;
1520 WREG32_SMC(GENERAL_PWRMGT, tmp);
1522 tmp = RREG32_SMC(SCLK_PWRMGT_CNTL);
1523 tmp |= DYNAMIC_PM_EN;
1524 WREG32_SMC(SCLK_PWRMGT_CNTL, tmp);
1577 u32 tmp;
1579 tmp = RREG32_SMC(GENERAL_PWRMGT);
1580 tmp &= ~GLOBAL_PWRMGT_EN;
1581 WREG32_SMC(GENERAL_PWRMGT, tmp);
1583 tmp = RREG32_SMC(SCLK_PWRMGT_CNTL);
1584 tmp &= ~DYNAMIC_PM_EN;
1585 WREG32_SMC(SCLK_PWRMGT_CNTL, tmp);
1606 u32 tmp = RREG32_SMC(SCLK_PWRMGT_CNTL);
1609 tmp &= ~SCLK_PWRMGT_OFF;
1611 tmp |= SCLK_PWRMGT_OFF;
1612 WREG32_SMC(SCLK_PWRMGT_CNTL, tmp);
1644 u32 tmp;
1653 tmp = RREG32(SMC_RESP_0);
1654 if (tmp != 0)
1658 tmp = RREG32(SMC_RESP_0);
1660 return (PPSMC_Result)tmp;
1804 u32 tmp;
1810 &tmp, pi->sram_end);
1814 pi->dpm_table_start = tmp;
1819 &tmp, pi->sram_end);
1823 pi->soft_regs_start = tmp;
1828 &tmp, pi->sram_end);
1832 pi->mc_reg_table_start = tmp;
1837 &tmp, pi->sram_end);
1841 pi->fan_table_start = tmp;
1846 &tmp, pi->sram_end);
1850 pi->arb_table_start = tmp;
1892 u32 tmp = RREG32_SMC(GENERAL_PWRMGT);
1895 tmp &= ~THERMAL_PROTECTION_DIS;
1897 tmp |= THERMAL_PROTECTION_DIS;
1898 WREG32_SMC(GENERAL_PWRMGT, tmp);
1903 u32 tmp = RREG32_SMC(GENERAL_PWRMGT);
1905 tmp |= STATIC_PM_EN;
1907 WREG32_SMC(GENERAL_PWRMGT, tmp);
1972 u32 tmp = RREG32_SMC(CG_DISPLAY_GAP_CNTL);
1979 tmp &= ~DISP_GAP_MASK;
1981 tmp |= DISP_GAP(R600_PM_DISPLAY_GAP_VBLANK_OR_WM);
1983 tmp |= DISP_GAP(R600_PM_DISPLAY_GAP_IGNORE);
1984 WREG32_SMC(CG_DISPLAY_GAP_CNTL, tmp);
1993 tmp = pre_vbi_time_in_us * (ref_clock / 100);
1995 WREG32_SMC(CG_DISPLAY_GAP_CNTL2, tmp);
2007 u32 tmp;
2011 tmp = RREG32_SMC(GENERAL_PWRMGT);
2012 tmp |= DYN_SPREAD_SPECTRUM_EN;
2013 WREG32_SMC(GENERAL_PWRMGT, tmp);
2016 tmp = RREG32_SMC(CG_SPLL_SPREAD_SPECTRUM);
2017 tmp &= ~SSEN;
2018 WREG32_SMC(CG_SPLL_SPREAD_SPECTRUM, tmp);
2020 tmp = RREG32_SMC(GENERAL_PWRMGT);
2021 tmp &= ~DYN_SPREAD_SPECTRUM_EN;
2022 WREG32_SMC(GENERAL_PWRMGT, tmp);
2033 u32 tmp = RREG32_SMC(CG_DISPLAY_GAP_CNTL);
2035 tmp &= ~(DISP_GAP_MASK | DISP_GAP_MCHG_MASK);
2036 tmp |= (DISP_GAP(R600_PM_DISPLAY_GAP_IGNORE) |
2039 WREG32_SMC(CG_DISPLAY_GAP_CNTL, tmp);
2044 u32 tmp;
2046 tmp = RREG32_SMC(SCLK_PWRMGT_CNTL);
2047 tmp &= ~(RESET_SCLK_CNT | RESET_BUSY_CNT);
2048 WREG32_SMC(SCLK_PWRMGT_CNTL, tmp);
2062 u32 tmp;
2064 tmp = RREG32_SMC(SCLK_PWRMGT_CNTL);
2065 tmp |= (RESET_SCLK_CNT | RESET_BUSY_CNT);
2066 WREG32_SMC(SCLK_PWRMGT_CNTL, tmp);
2401 u32 tmp;
2405 &tmp, pi->sram_end);
2409 tmp &= 0x00FFFFFF;
2410 tmp |= MC_CG_ARB_FREQ_F1 << 24;
2413 tmp, pi->sram_end);
2441 u32 tmp;
2449 tmp = sclk / (1 << i);
2450 if (tmp >= min || i == 0)
2470 u32 tmp;
2472 tmp = (RREG32_SMC(SMC_SCRATCH9) & 0x0000ff00) >> 8;
2474 if (tmp == MC_CG_ARB_FREQ_F0)
2477 return ni_copy_and_switch_arb_sets(rdev, tmp, MC_CG_ARB_FREQ_F0);
2486 u32 tmp, tmp2;
2488 tmp = RREG32(MC_SEQ_MISC0);
2489 patch = ((tmp & 0x0000f00) == 0x300) ? true : false;
2815 u32 tmp;
2823 tmp = (freq_nom / reference_clock);
2824 tmp = tmp * tmp;
2828 u32 clkv = (u32)((((131 * ss.percentage * ss.rate) / 100) * tmp) / freq_nom);
4065 u32 tmp;
4075 tmp = RREG32_SMC(DPM_TABLE_475);
4076 tmp &= ~UvdBootLevel_MASK;
4077 tmp |= UvdBootLevel(pi->smc_state_table.UvdBootLevel);
4078 WREG32_SMC(DPM_TABLE_475, tmp);
4105 u32 tmp;
4113 tmp = RREG32_SMC(DPM_TABLE_475);
4114 tmp &= ~VceBootLevel_MASK;
4115 tmp |= VceBootLevel(pi->smc_state_table.VceBootLevel);
4116 WREG32_SMC(DPM_TABLE_475, tmp);
4138 u32 tmp;
4143 tmp = RREG32_SMC(DPM_TABLE_475);
4144 tmp &= ~AcpBootLevel_MASK;
4145 tmp |= AcpBootLevel(pi->smc_state_table.AcpBootLevel);
4146 WREG32_SMC(DPM_TABLE_475, tmp);
4195 u32 tmp, levels, i;
4202 tmp = pi->dpm_level_enable_mask.pcie_dpm_enable_mask;
4203 while (tmp >>= 1)
4210 tmp = (RREG32_SMC(TARGET_AND_CURRENT_PROFILE_INDEX_1) &
4212 if (tmp == levels)
4221 tmp = pi->dpm_level_enable_mask.sclk_dpm_enable_mask;
4222 while (tmp >>= 1)
4229 tmp = (RREG32_SMC(TARGET_AND_CURRENT_PROFILE_INDEX) &
4231 if (tmp == levels)
4240 tmp = pi->dpm_level_enable_mask.mclk_dpm_enable_mask;
4241 while (tmp >>= 1)
4248 tmp = (RREG32_SMC(TARGET_AND_CURRENT_PROFILE_INDEX) &
4250 if (tmp == levels)
4265 tmp = (RREG32_SMC(TARGET_AND_CURRENT_PROFILE_INDEX) &
4267 if (tmp == levels)
4280 tmp = (RREG32_SMC(TARGET_AND_CURRENT_PROFILE_INDEX) &
4282 if (tmp == levels)
4295 tmp = (RREG32_SMC(TARGET_AND_CURRENT_PROFILE_INDEX_1) &
4297 if (tmp == levels)
4523 u32 tmp;
4526 tmp = RREG32(MC_SEQ_MISC0);
4527 patch = ((tmp & 0x0000f00) == 0x300) ? true : false;
4600 tmp = RREG32(MC_SEQ_IO_DEBUG_DATA);
4601 tmp = (tmp & 0xFFF8FFFF) | (1 << 16);
4603 WREG32(MC_SEQ_IO_DEBUG_DATA, tmp);
4776 u32 tmp = RREG32_SMC(GENERAL_PWRMGT);
4778 tmp |= VOLT_PWRMGT_EN;
4779 WREG32_SMC(GENERAL_PWRMGT, tmp);
5081 u32 tmp;
5083 tmp = RREG32(MC_SEQ_MISC0);
5085 if (((tmp & MC_SEQ_MISC0_GDDR5_MASK) >> MC_SEQ_MISC0_GDDR5_SHIFT) ==
5845 u32 tmp = RREG32_SMC(CNB_PWRMGT_CNTL);
5849 tmp &= ~GNB_SLOW_MODE_MASK;
5850 tmp |= GNB_SLOW_MODE(1);
5853 tmp &= ~GNB_SLOW_MODE_MASK;
5854 tmp |= GNB_SLOW_MODE(2);
5857 tmp |= GNB_SLOW;
5860 tmp |= FORCE_NB_PS1;
5863 tmp |= DPM_ENABLED;
5869 WREG32_SMC(CNB_PWRMGT_CNTL, tmp);