Lines Matching defs:rdev
152 extern u8 rv770_get_memory_module_index(struct radeon_device *rdev);
153 extern int ni_copy_and_switch_arb_sets(struct radeon_device *rdev,
157 extern void si_trim_voltage_table_to_fit_state_table(struct radeon_device *rdev,
160 extern void cik_enter_rlc_safe_mode(struct radeon_device *rdev);
161 extern void cik_exit_rlc_safe_mode(struct radeon_device *rdev);
162 extern int ci_mc_load_microcode(struct radeon_device *rdev);
163 extern void cik_update_cg(struct radeon_device *rdev,
166 static int ci_get_std_voltage_value_sidd(struct radeon_device *rdev,
169 static int ci_set_power_limit(struct radeon_device *rdev, u32 n);
170 static int ci_set_overdrive_target_tdp(struct radeon_device *rdev,
172 static int ci_update_uvd_dpm(struct radeon_device *rdev, bool gate);
174 static PPSMC_Result ci_send_msg_to_smc(struct radeon_device *rdev, PPSMC_Msg msg);
175 static PPSMC_Result ci_send_msg_to_smc_with_parameter(struct radeon_device *rdev,
178 static void ci_thermal_start_smc_fan_control(struct radeon_device *rdev);
179 static void ci_fan_ctrl_set_default_mode(struct radeon_device *rdev);
181 static struct ci_power_info *ci_get_pi(struct radeon_device *rdev)
183 struct ci_power_info *pi = rdev->pm.dpm.priv;
195 static void ci_initialize_powertune_defaults(struct radeon_device *rdev)
197 struct ci_power_info *pi = ci_get_pi(rdev);
199 switch (rdev->pdev->device) {
246 if (rdev->family == CHIP_HAWAII)
260 static int ci_populate_bapm_vddc_vid_sidd(struct radeon_device *rdev)
262 struct ci_power_info *pi = ci_get_pi(rdev);
268 if (rdev->pm.dpm.dyn_state.cac_leakage_table.entries == NULL)
270 if (rdev->pm.dpm.dyn_state.cac_leakage_table.count > 8)
272 if (rdev->pm.dpm.dyn_state.cac_leakage_table.count !=
273 rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count)
276 for (i = 0; i < rdev->pm.dpm.dyn_state.cac_leakage_table.count; i++) {
277 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_EVV) {
278 lo_vid[i] = ci_convert_to_vid(rdev->pm.dpm.dyn_state.cac_leakage_table.entries[i].vddc1);
279 hi_vid[i] = ci_convert_to_vid(rdev->pm.dpm.dyn_state.cac_leakage_table.entries[i].vddc2);
280 hi2_vid[i] = ci_convert_to_vid(rdev->pm.dpm.dyn_state.cac_leakage_table.entries[i].vddc3);
282 lo_vid[i] = ci_convert_to_vid(rdev->pm.dpm.dyn_state.cac_leakage_table.entries[i].vddc);
283 hi_vid[i] = ci_convert_to_vid((u16)rdev->pm.dpm.dyn_state.cac_leakage_table.entries[i].leakage);
289 static int ci_populate_vddc_vid(struct radeon_device *rdev)
291 struct ci_power_info *pi = ci_get_pi(rdev);
304 static int ci_populate_svi_load_line(struct radeon_device *rdev)
306 struct ci_power_info *pi = ci_get_pi(rdev);
317 static int ci_populate_tdc_limit(struct radeon_device *rdev)
319 struct ci_power_info *pi = ci_get_pi(rdev);
323 tdc_limit = rdev->pm.dpm.dyn_state.cac_tdp_table->tdc * 256;
332 static int ci_populate_dw8(struct radeon_device *rdev)
334 struct ci_power_info *pi = ci_get_pi(rdev);
338 ret = ci_read_smc_sram_dword(rdev,
352 static int ci_populate_fuzzy_fan(struct radeon_device *rdev)
354 struct ci_power_info *pi = ci_get_pi(rdev);
356 if ((rdev->pm.dpm.fan.fan_output_sensitivity & (1 << 15)) ||
357 (rdev->pm.dpm.fan.fan_output_sensitivity == 0))
358 rdev->pm.dpm.fan.fan_output_sensitivity =
359 rdev->pm.dpm.fan.default_fan_output_sensitivity;
362 cpu_to_be16(rdev->pm.dpm.fan.fan_output_sensitivity);
367 static int ci_min_max_v_gnbl_pm_lid_from_bapm_vddc(struct radeon_device *rdev)
369 struct ci_power_info *pi = ci_get_pi(rdev);
399 static int ci_populate_bapm_vddc_base_leakage_sidd(struct radeon_device *rdev)
401 struct ci_power_info *pi = ci_get_pi(rdev);
405 rdev->pm.dpm.dyn_state.cac_tdp_table;
416 static int ci_populate_bapm_parameters_in_dpm_table(struct radeon_device *rdev)
418 struct ci_power_info *pi = ci_get_pi(rdev);
422 rdev->pm.dpm.dyn_state.cac_tdp_table;
423 struct radeon_ppm_table *ppm = rdev->pm.dpm.dyn_state.ppm_table;
464 static int ci_populate_pm_base(struct radeon_device *rdev)
466 struct ci_power_info *pi = ci_get_pi(rdev);
471 ret = ci_read_smc_sram_dword(rdev,
477 ret = ci_populate_bapm_vddc_vid_sidd(rdev);
480 ret = ci_populate_vddc_vid(rdev);
483 ret = ci_populate_svi_load_line(rdev);
486 ret = ci_populate_tdc_limit(rdev);
489 ret = ci_populate_dw8(rdev);
492 ret = ci_populate_fuzzy_fan(rdev);
495 ret = ci_min_max_v_gnbl_pm_lid_from_bapm_vddc(rdev);
498 ret = ci_populate_bapm_vddc_base_leakage_sidd(rdev);
501 ret = ci_copy_bytes_to_smc(rdev, pm_fuse_table_offset,
511 static void ci_do_enable_didt(struct radeon_device *rdev, const bool enable)
513 struct ci_power_info *pi = ci_get_pi(rdev);
553 static int ci_program_pt_config_registers(struct radeon_device *rdev,
601 static int ci_enable_didt(struct radeon_device *rdev, bool enable)
603 struct ci_power_info *pi = ci_get_pi(rdev);
608 cik_enter_rlc_safe_mode(rdev);
611 ret = ci_program_pt_config_registers(rdev, didt_config_ci);
613 cik_exit_rlc_safe_mode(rdev);
618 ci_do_enable_didt(rdev, enable);
620 cik_exit_rlc_safe_mode(rdev);
626 static int ci_enable_power_containment(struct radeon_device *rdev, bool enable)
628 struct ci_power_info *pi = ci_get_pi(rdev);
636 smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_EnableDTE);
644 smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_TDCLimitEnable);
652 smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_PkgPwrLimitEnable);
657 rdev->pm.dpm.dyn_state.cac_tdp_table;
663 ci_set_power_limit(rdev, default_pwr_limit);
670 ci_send_msg_to_smc(rdev, PPSMC_MSG_TDCLimitDisable);
673 ci_send_msg_to_smc(rdev, PPSMC_MSG_DisableDTE);
676 ci_send_msg_to_smc(rdev, PPSMC_MSG_PkgPwrLimitDisable);
684 static int ci_enable_smc_cac(struct radeon_device *rdev, bool enable)
686 struct ci_power_info *pi = ci_get_pi(rdev);
692 smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_EnableCac);
700 ci_send_msg_to_smc(rdev, PPSMC_MSG_DisableCac);
708 static int ci_enable_thermal_based_sclk_dpm(struct radeon_device *rdev,
711 struct ci_power_info *pi = ci_get_pi(rdev);
716 smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_ENABLE_THERMAL_DPM);
718 smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_DISABLE_THERMAL_DPM);
727 static int ci_power_control_set_level(struct radeon_device *rdev)
729 struct ci_power_info *pi = ci_get_pi(rdev);
731 rdev->pm.dpm.dyn_state.cac_tdp_table;
739 rdev->pm.dpm.tdp_adjustment : (-1 * rdev->pm.dpm.tdp_adjustment);
743 ret = ci_set_overdrive_target_tdp(rdev, (u32)target_tdp);
749 void ci_dpm_powergate_uvd(struct radeon_device *rdev, bool gate)
751 struct ci_power_info *pi = ci_get_pi(rdev);
758 ci_update_uvd_dpm(rdev, gate);
761 bool ci_dpm_vblank_too_short(struct radeon_device *rdev)
763 struct ci_power_info *pi = ci_get_pi(rdev);
764 u32 vblank_time = r600_dpm_get_vblank_time(rdev);
770 if (r600_dpm_get_vrefresh(rdev) > 120)
780 static void ci_apply_state_adjust_rules(struct radeon_device *rdev,
784 struct ci_power_info *pi = ci_get_pi(rdev);
791 rps->evclk = rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].evclk;
792 rps->ecclk = rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].ecclk;
798 if ((rdev->pm.dpm.new_active_crtc_count > 1) ||
799 ci_dpm_vblank_too_short(rdev))
809 if (rdev->pm.dpm.ac_power)
810 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac;
812 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc;
814 if (rdev->pm.dpm.ac_power == false) {
834 if (sclk < rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].sclk)
835 sclk = rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].sclk;
836 if (mclk < rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].mclk)
837 mclk = rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].mclk;
855 static int ci_thermal_set_temperature_range(struct radeon_device *rdev,
885 rdev->pm.dpm.thermal.min_temp = low_temp;
886 rdev->pm.dpm.thermal.max_temp = high_temp;
891 static int ci_thermal_enable_alert(struct radeon_device *rdev,
900 rdev->irq.dpm_thermal = false;
901 result = ci_send_msg_to_smc(rdev, PPSMC_MSG_Thermal_Cntl_Enable);
909 rdev->irq.dpm_thermal = true;
910 result = ci_send_msg_to_smc(rdev, PPSMC_MSG_Thermal_Cntl_Disable);
920 static void ci_fan_ctrl_set_static_mode(struct radeon_device *rdev, u32 mode)
922 struct ci_power_info *pi = ci_get_pi(rdev);
942 static int ci_thermal_setup_fan_table(struct radeon_device *rdev)
944 struct ci_power_info *pi = ci_get_pi(rdev);
954 rdev->pm.dpm.fan.ucode_fan_control = false;
961 rdev->pm.dpm.fan.ucode_fan_control = false;
965 tmp64 = (u64)rdev->pm.dpm.fan.pwm_min * duty100;
969 t_diff1 = rdev->pm.dpm.fan.t_med - rdev->pm.dpm.fan.t_min;
970 t_diff2 = rdev->pm.dpm.fan.t_high - rdev->pm.dpm.fan.t_med;
972 pwm_diff1 = rdev->pm.dpm.fan.pwm_med - rdev->pm.dpm.fan.pwm_min;
973 pwm_diff2 = rdev->pm.dpm.fan.pwm_high - rdev->pm.dpm.fan.pwm_med;
978 fan_table.TempMin = cpu_to_be16((50 + rdev->pm.dpm.fan.t_min) / 100);
979 fan_table.TempMed = cpu_to_be16((50 + rdev->pm.dpm.fan.t_med) / 100);
980 fan_table.TempMax = cpu_to_be16((50 + rdev->pm.dpm.fan.t_max) / 100);
987 fan_table.HystDown = cpu_to_be16(rdev->pm.dpm.fan.t_hyst);
995 reference_clock = radeon_get_xclk(rdev);
997 fan_table.RefreshPeriod = cpu_to_be32((rdev->pm.dpm.fan.cycle_delay *
1005 ret = ci_copy_bytes_to_smc(rdev,
1013 rdev->pm.dpm.fan.ucode_fan_control = false;
1019 static int ci_fan_ctrl_start_smc_fan_control(struct radeon_device *rdev)
1021 struct ci_power_info *pi = ci_get_pi(rdev);
1025 ret = ci_send_msg_to_smc_with_parameter(rdev,
1030 ret = ci_send_msg_to_smc_with_parameter(rdev,
1032 rdev->pm.dpm.fan.default_max_fan_pwm);
1036 ret = ci_send_msg_to_smc_with_parameter(rdev,
1047 static int ci_fan_ctrl_stop_smc_fan_control(struct radeon_device *rdev)
1050 struct ci_power_info *pi = ci_get_pi(rdev);
1052 ret = ci_send_msg_to_smc(rdev, PPSMC_StopFanControl);
1060 int ci_fan_ctrl_get_fan_speed_percent(struct radeon_device *rdev,
1066 if (rdev->pm.no_fan)
1085 int ci_fan_ctrl_set_fan_speed_percent(struct radeon_device *rdev,
1091 struct ci_power_info *pi = ci_get_pi(rdev);
1093 if (rdev->pm.no_fan)
1118 void ci_fan_ctrl_set_mode(struct radeon_device *rdev, u32 mode)
1122 if (rdev->pm.dpm.fan.ucode_fan_control)
1123 ci_fan_ctrl_stop_smc_fan_control(rdev);
1124 ci_fan_ctrl_set_static_mode(rdev, mode);
1127 if (rdev->pm.dpm.fan.ucode_fan_control)
1128 ci_thermal_start_smc_fan_control(rdev);
1130 ci_fan_ctrl_set_default_mode(rdev);
1134 u32 ci_fan_ctrl_get_mode(struct radeon_device *rdev)
1136 struct ci_power_info *pi = ci_get_pi(rdev);
1147 static int ci_fan_ctrl_get_fan_speed_rpm(struct radeon_device *rdev,
1151 u32 xclk = radeon_get_xclk(rdev);
1153 if (rdev->pm.no_fan)
1156 if (rdev->pm.fan_pulses_per_revolution == 0)
1168 static int ci_fan_ctrl_set_fan_speed_rpm(struct radeon_device *rdev,
1172 u32 xclk = radeon_get_xclk(rdev);
1174 if (rdev->pm.no_fan)
1177 if (rdev->pm.fan_pulses_per_revolution == 0)
1180 if ((speed < rdev->pm.fan_min_rpm) ||
1181 (speed > rdev->pm.fan_max_rpm))
1184 if (rdev->pm.dpm.fan.ucode_fan_control)
1185 ci_fan_ctrl_stop_smc_fan_control(rdev);
1192 ci_fan_ctrl_set_static_mode(rdev, FDO_PWM_MODE_STATIC_RPM);
1198 static void ci_fan_ctrl_set_default_mode(struct radeon_device *rdev)
1200 struct ci_power_info *pi = ci_get_pi(rdev);
1215 static void ci_thermal_start_smc_fan_control(struct radeon_device *rdev)
1217 if (rdev->pm.dpm.fan.ucode_fan_control) {
1218 ci_fan_ctrl_start_smc_fan_control(rdev);
1219 ci_fan_ctrl_set_static_mode(rdev, FDO_PWM_MODE_STATIC);
1223 static void ci_thermal_initialize(struct radeon_device *rdev)
1227 if (rdev->pm.fan_pulses_per_revolution) {
1229 tmp |= EDGE_PER_REV(rdev->pm.fan_pulses_per_revolution -1);
1238 static int ci_thermal_start_thermal_controller(struct radeon_device *rdev)
1242 ci_thermal_initialize(rdev);
1243 ret = ci_thermal_set_temperature_range(rdev, R600_TEMP_RANGE_MIN, R600_TEMP_RANGE_MAX);
1246 ret = ci_thermal_enable_alert(rdev, true);
1249 if (rdev->pm.dpm.fan.ucode_fan_control) {
1250 ret = ci_thermal_setup_fan_table(rdev);
1253 ci_thermal_start_smc_fan_control(rdev);
1259 static void ci_thermal_stop_thermal_controller(struct radeon_device *rdev)
1261 if (!rdev->pm.no_fan)
1262 ci_fan_ctrl_set_default_mode(rdev);
1266 static int ci_read_smc_soft_register(struct radeon_device *rdev,
1269 struct ci_power_info *pi = ci_get_pi(rdev);
1271 return ci_read_smc_sram_dword(rdev,
1277 static int ci_write_smc_soft_register(struct radeon_device *rdev,
1280 struct ci_power_info *pi = ci_get_pi(rdev);
1282 return ci_write_smc_sram_dword(rdev,
1287 static void ci_init_fps_limits(struct radeon_device *rdev)
1289 struct ci_power_info *pi = ci_get_pi(rdev);
1303 static int ci_update_sclk_t(struct radeon_device *rdev)
1305 struct ci_power_info *pi = ci_get_pi(rdev);
1312 ret = ci_copy_bytes_to_smc(rdev,
1323 static void ci_get_leakage_voltages(struct radeon_device *rdev)
1325 struct ci_power_info *pi = ci_get_pi(rdev);
1333 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_EVV) {
1336 if (radeon_atom_get_voltage_evv(rdev, virtual_voltage_id, &vddc) != 0)
1344 } else if (radeon_atom_get_leakage_id_from_vbios(rdev, &leakage_id) == 0) {
1347 if (radeon_atom_get_leakage_vddc_based_on_leakage_params(rdev, &vddc, &vddci,
1365 static void ci_set_dpm_event_sources(struct radeon_device *rdev, u32 sources)
1367 struct ci_power_info *pi = ci_get_pi(rdev);
1414 static void ci_enable_auto_throttle_source(struct radeon_device *rdev,
1418 struct ci_power_info *pi = ci_get_pi(rdev);
1423 ci_set_dpm_event_sources(rdev, pi->active_auto_throttle_sources);
1428 ci_set_dpm_event_sources(rdev, pi->active_auto_throttle_sources);
1433 static void ci_enable_vr_hot_gpio_interrupt(struct radeon_device *rdev)
1435 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_REGULATOR_HOT)
1436 ci_send_msg_to_smc(rdev, PPSMC_MSG_EnableVRHotGPIOInterrupt);
1439 static int ci_unfreeze_sclk_mclk_dpm(struct radeon_device *rdev)
1441 struct ci_power_info *pi = ci_get_pi(rdev);
1449 smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_SCLKDPM_UnfreezeLevel);
1456 smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_MCLKDPM_UnfreezeLevel);
1465 static int ci_enable_sclk_mclk_dpm(struct radeon_device *rdev, bool enable)
1467 struct ci_power_info *pi = ci_get_pi(rdev);
1472 smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_DPM_Enable);
1478 smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_MCLKDPM_Enable);
1496 smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_DPM_Disable);
1502 smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_MCLKDPM_Disable);
1511 static int ci_start_dpm(struct radeon_device *rdev)
1513 struct ci_power_info *pi = ci_get_pi(rdev);
1526 ci_write_smc_soft_register(rdev, offsetof(SMU7_SoftRegisters, VoltageChangeTimeout), 0x1000);
1530 smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_Voltage_Cntl_Enable);
1534 ret = ci_enable_sclk_mclk_dpm(rdev, true);
1539 smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_PCIeDPM_Enable);
1547 static int ci_freeze_sclk_mclk_dpm(struct radeon_device *rdev)
1549 struct ci_power_info *pi = ci_get_pi(rdev);
1557 smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_SCLKDPM_FreezeLevel);
1564 smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_MCLKDPM_FreezeLevel);
1572 static int ci_stop_dpm(struct radeon_device *rdev)
1574 struct ci_power_info *pi = ci_get_pi(rdev);
1588 smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_PCIeDPM_Disable);
1593 ret = ci_enable_sclk_mclk_dpm(rdev, false);
1597 smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_Voltage_Cntl_Disable);
1604 static void ci_enable_sclk_control(struct radeon_device *rdev, bool enable)
1616 static int ci_notify_hw_of_power_source(struct radeon_device *rdev,
1619 struct ci_power_info *pi = ci_get_pi(rdev);
1621 rdev->pm.dpm.dyn_state.cac_tdp_table;
1629 ci_set_power_limit(rdev, power_limit);
1633 ci_send_msg_to_smc(rdev, PPSMC_MSG_RunningOnAC);
1635 ci_send_msg_to_smc(rdev, PPSMC_MSG_Remove_DC_Clamp);
1642 static PPSMC_Result ci_send_msg_to_smc(struct radeon_device *rdev, PPSMC_Msg msg)
1647 if (!ci_is_smc_running(rdev))
1652 for (i = 0; i < rdev->usec_timeout; i++) {
1663 static PPSMC_Result ci_send_msg_to_smc_with_parameter(struct radeon_device *rdev,
1667 return ci_send_msg_to_smc(rdev, msg);
1670 static PPSMC_Result ci_send_msg_to_smc_return_parameter(struct radeon_device *rdev,
1675 smc_result = ci_send_msg_to_smc(rdev, msg);
1683 static int ci_dpm_force_state_sclk(struct radeon_device *rdev, u32 n)
1685 struct ci_power_info *pi = ci_get_pi(rdev);
1689 ci_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SCLKDPM_SetEnabledMask, 1 << n);
1697 static int ci_dpm_force_state_mclk(struct radeon_device *rdev, u32 n)
1699 struct ci_power_info *pi = ci_get_pi(rdev);
1703 ci_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_MCLKDPM_SetEnabledMask, 1 << n);
1711 static int ci_dpm_force_state_pcie(struct radeon_device *rdev, u32 n)
1713 struct ci_power_info *pi = ci_get_pi(rdev);
1717 ci_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_PCIeDPM_ForceLevel, n);
1725 static int ci_set_power_limit(struct radeon_device *rdev, u32 n)
1727 struct ci_power_info *pi = ci_get_pi(rdev);
1731 ci_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_PkgPwrSetLimit, n);
1739 static int ci_set_overdrive_target_tdp(struct radeon_device *rdev,
1743 ci_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_OverDriveSetTargetTdp, target_tdp);
1750 static int ci_set_boot_state(struct radeon_device *rdev)
1752 return ci_enable_sclk_mclk_dpm(rdev, false);
1756 static u32 ci_get_average_sclk_freq(struct radeon_device *rdev)
1760 ci_send_msg_to_smc_return_parameter(rdev,
1769 static u32 ci_get_average_mclk_freq(struct radeon_device *rdev)
1773 ci_send_msg_to_smc_return_parameter(rdev,
1782 static void ci_dpm_start_smc(struct radeon_device *rdev)
1786 ci_program_jump_on_start(rdev);
1787 ci_start_smc_clock(rdev);
1788 ci_start_smc(rdev);
1789 for (i = 0; i < rdev->usec_timeout; i++) {
1795 static void ci_dpm_stop_smc(struct radeon_device *rdev)
1797 ci_reset_smc(rdev);
1798 ci_stop_smc_clock(rdev);
1801 static int ci_process_firmware_header(struct radeon_device *rdev)
1803 struct ci_power_info *pi = ci_get_pi(rdev);
1807 ret = ci_read_smc_sram_dword(rdev,
1816 ret = ci_read_smc_sram_dword(rdev,
1825 ret = ci_read_smc_sram_dword(rdev,
1834 ret = ci_read_smc_sram_dword(rdev,
1843 ret = ci_read_smc_sram_dword(rdev,
1855 static void ci_read_clock_registers(struct radeon_device *rdev)
1857 struct ci_power_info *pi = ci_get_pi(rdev);
1882 static void ci_init_sclk_t(struct radeon_device *rdev)
1884 struct ci_power_info *pi = ci_get_pi(rdev);
1889 static void ci_enable_thermal_protection(struct radeon_device *rdev,
1901 static void ci_enable_acpi_power_management(struct radeon_device *rdev)
1911 static int ci_enter_ulp_state(struct radeon_device *rdev)
1921 static int ci_exit_ulp_state(struct radeon_device *rdev)
1929 for (i = 0; i < rdev->usec_timeout; i++) {
1939 static int ci_notify_smc_display_change(struct radeon_device *rdev,
1944 return (ci_send_msg_to_smc(rdev, msg) == PPSMC_Result_OK) ? 0 : -EINVAL;
1947 static int ci_enable_ds_master_switch(struct radeon_device *rdev,
1950 struct ci_power_info *pi = ci_get_pi(rdev);
1954 if (ci_send_msg_to_smc(rdev, PPSMC_MSG_MASTER_DeepSleep_ON) != PPSMC_Result_OK)
1957 if (ci_send_msg_to_smc(rdev, PPSMC_MSG_MASTER_DeepSleep_OFF) != PPSMC_Result_OK)
1962 if (ci_send_msg_to_smc(rdev, PPSMC_MSG_MASTER_DeepSleep_OFF) != PPSMC_Result_OK)
1970 static void ci_program_display_gap(struct radeon_device *rdev)
1975 u32 ref_clock = rdev->clock.spll.reference_freq;
1976 u32 refresh_rate = r600_dpm_get_vrefresh(rdev);
1977 u32 vblank_time = r600_dpm_get_vblank_time(rdev);
1980 if (rdev->pm.dpm.new_active_crtc_count > 0)
1996 ci_write_smc_soft_register(rdev, offsetof(SMU7_SoftRegisters, PreVBlankGap), 0x64);
1997 ci_write_smc_soft_register(rdev, offsetof(SMU7_SoftRegisters, VBlankTimeout), (frame_time_in_us - pre_vbi_time_in_us));
2000 ci_notify_smc_display_change(rdev, (rdev->pm.dpm.new_active_crtc_count == 1));
2004 static void ci_enable_spread_spectrum(struct radeon_device *rdev, bool enable)
2006 struct ci_power_info *pi = ci_get_pi(rdev);
2026 static void ci_program_sstp(struct radeon_device *rdev)
2031 static void ci_enable_display_gap(struct radeon_device *rdev)
2042 static void ci_program_vc(struct radeon_device *rdev)
2060 static void ci_clear_vc(struct radeon_device *rdev)
2078 static int ci_upload_firmware(struct radeon_device *rdev)
2080 struct ci_power_info *pi = ci_get_pi(rdev);
2083 for (i = 0; i < rdev->usec_timeout; i++) {
2089 ci_stop_smc_clock(rdev);
2090 ci_reset_smc(rdev);
2092 ret = ci_load_smc_ucode(rdev, pi->sram_end);
2098 static int ci_get_svi2_voltage_table(struct radeon_device *rdev,
2119 static int ci_construct_voltage_tables(struct radeon_device *rdev)
2121 struct ci_power_info *pi = ci_get_pi(rdev);
2125 ret = radeon_atom_get_voltage_table(rdev, VOLTAGE_TYPE_VDDC,
2131 ret = ci_get_svi2_voltage_table(rdev,
2132 &rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk,
2139 si_trim_voltage_table_to_fit_state_table(rdev, SMU7_MAX_LEVELS_VDDC,
2143 ret = radeon_atom_get_voltage_table(rdev, VOLTAGE_TYPE_VDDCI,
2149 ret = ci_get_svi2_voltage_table(rdev,
2150 &rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk,
2157 si_trim_voltage_table_to_fit_state_table(rdev, SMU7_MAX_LEVELS_VDDCI,
2161 ret = radeon_atom_get_voltage_table(rdev, VOLTAGE_TYPE_MVDDC,
2167 ret = ci_get_svi2_voltage_table(rdev,
2168 &rdev->pm.dpm.dyn_state.mvdd_dependency_on_mclk,
2175 si_trim_voltage_table_to_fit_state_table(rdev, SMU7_MAX_LEVELS_MVDD,
2181 static void ci_populate_smc_voltage_table(struct radeon_device *rdev,
2187 ret = ci_get_std_voltage_value_sidd(rdev, voltage_table,
2203 static int ci_populate_smc_vddc_table(struct radeon_device *rdev,
2206 struct ci_power_info *pi = ci_get_pi(rdev);
2211 ci_populate_smc_voltage_table(rdev,
2226 static int ci_populate_smc_vddci_table(struct radeon_device *rdev,
2230 struct ci_power_info *pi = ci_get_pi(rdev);
2234 ci_populate_smc_voltage_table(rdev,
2249 static int ci_populate_smc_mvdd_table(struct radeon_device *rdev,
2252 struct ci_power_info *pi = ci_get_pi(rdev);
2257 ci_populate_smc_voltage_table(rdev,
2272 static int ci_populate_smc_voltage_tables(struct radeon_device *rdev,
2277 ret = ci_populate_smc_vddc_table(rdev, table);
2281 ret = ci_populate_smc_vddci_table(rdev, table);
2285 ret = ci_populate_smc_mvdd_table(rdev, table);
2292 static int ci_populate_mvdd_value(struct radeon_device *rdev, u32 mclk,
2295 struct ci_power_info *pi = ci_get_pi(rdev);
2299 for (i = 0; i < rdev->pm.dpm.dyn_state.mvdd_dependency_on_mclk.count; i++) {
2300 if (mclk <= rdev->pm.dpm.dyn_state.mvdd_dependency_on_mclk.entries[i].clk) {
2306 if (i >= rdev->pm.dpm.dyn_state.mvdd_dependency_on_mclk.count)
2313 static int ci_get_std_voltage_value_sidd(struct radeon_device *rdev,
2322 if (rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries == NULL)
2325 if (rdev->pm.dpm.dyn_state.cac_leakage_table.entries) {
2326 for (v_index = 0; (u32)v_index < rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count; v_index++) {
2328 rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[v_index].v) {
2330 if ((u32)v_index < rdev->pm.dpm.dyn_state.cac_leakage_table.count)
2333 idx = rdev->pm.dpm.dyn_state.cac_leakage_table.count - 1;
2335 rdev->pm.dpm.dyn_state.cac_leakage_table.entries[idx].vddc * VOLTAGE_SCALE;
2337 rdev->pm.dpm.dyn_state.cac_leakage_table.entries[idx].leakage * VOLTAGE_SCALE;
2343 for (v_index = 0; (u32)v_index < rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count; v_index++) {
2345 rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[v_index].v) {
2347 if ((u32)v_index < rdev->pm.dpm.dyn_state.cac_leakage_table.count)
2350 idx = rdev->pm.dpm.dyn_state.cac_leakage_table.count - 1;
2352 rdev->pm.dpm.dyn_state.cac_leakage_table.entries[idx].vddc * VOLTAGE_SCALE;
2354 rdev->pm.dpm.dyn_state.cac_leakage_table.entries[idx].leakage * VOLTAGE_SCALE;
2364 static void ci_populate_phase_value_based_on_sclk(struct radeon_device *rdev,
2381 static void ci_populate_phase_value_based_on_mclk(struct radeon_device *rdev,
2398 static int ci_init_arb_table_index(struct radeon_device *rdev)
2400 struct ci_power_info *pi = ci_get_pi(rdev);
2404 ret = ci_read_smc_sram_dword(rdev, pi->arb_table_start,
2412 return ci_write_smc_sram_dword(rdev, pi->arb_table_start,
2416 static int ci_get_dependency_volt_by_clk(struct radeon_device *rdev,
2437 static u8 ci_get_sleep_divider_id_from_clock(struct radeon_device *rdev,
2457 static int ci_initial_switch_from_arb_f0_to_f1(struct radeon_device *rdev)
2459 return ni_copy_and_switch_arb_sets(rdev, MC_CG_ARB_FREQ_F0, MC_CG_ARB_FREQ_F1);
2462 static int ci_reset_to_default(struct radeon_device *rdev)
2464 return (ci_send_msg_to_smc(rdev, PPSMC_MSG_ResetToDefaults) == PPSMC_Result_OK) ?
2468 static int ci_force_switch_to_arb_f0(struct radeon_device *rdev)
2477 return ni_copy_and_switch_arb_sets(rdev, tmp, MC_CG_ARB_FREQ_F0);
2480 static void ci_register_patching_mc_arb(struct radeon_device *rdev,
2492 ((rdev->pdev->device == 0x67B0) ||
2493 (rdev->pdev->device == 0x67B1))) {
2507 static int ci_populate_memory_timing_parameters(struct radeon_device *rdev,
2516 radeon_atom_set_engine_dram_timings(rdev, sclk, mclk);
2522 ci_register_patching_mc_arb(rdev, sclk, mclk, &dram_timing2);
2531 static int ci_do_program_memory_timing_parameters(struct radeon_device *rdev)
2533 struct ci_power_info *pi = ci_get_pi(rdev);
2542 ret = ci_populate_memory_timing_parameters(rdev,
2552 ret = ci_copy_bytes_to_smc(rdev,
2561 static int ci_program_memory_timing_parameters(struct radeon_device *rdev)
2563 struct ci_power_info *pi = ci_get_pi(rdev);
2568 return ci_do_program_memory_timing_parameters(rdev);
2571 static void ci_populate_smc_initial_state(struct radeon_device *rdev,
2575 struct ci_power_info *pi = ci_get_pi(rdev);
2578 for (level = 0; level < rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count; level++) {
2579 if (rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[level].clk >=
2586 for (level = 0; level < rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk.count; level++) {
2587 if (rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk.entries[level].clk >=
2611 static void ci_populate_smc_link_level(struct radeon_device *rdev,
2614 struct ci_power_info *pi = ci_get_pi(rdev);
2633 static int ci_populate_smc_uvd_level(struct radeon_device *rdev,
2641 rdev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.count;
2645 rdev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.entries[count].vclk;
2647 rdev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.entries[count].dclk;
2649 rdev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.entries[count].v * VOLTAGE_SCALE;
2652 ret = radeon_atom_get_clock_dividers(rdev,
2660 ret = radeon_atom_get_clock_dividers(rdev,
2676 static int ci_populate_smc_vce_level(struct radeon_device *rdev,
2684 rdev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table.count;
2688 rdev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table.entries[count].evclk;
2690 (u16)rdev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table.entries[count].v * VOLTAGE_SCALE;
2693 ret = radeon_atom_get_clock_dividers(rdev,
2709 static int ci_populate_smc_acp_level(struct radeon_device *rdev,
2717 (rdev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table.count);
2721 rdev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table.entries[count].clk;
2723 rdev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table.entries[count].v;
2726 ret = radeon_atom_get_clock_dividers(rdev,
2741 static int ci_populate_smc_samu_level(struct radeon_device *rdev,
2749 rdev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table.count;
2753 rdev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table.entries[count].clk;
2755 rdev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table.entries[count].v * VOLTAGE_SCALE;
2758 ret = radeon_atom_get_clock_dividers(rdev,
2773 static int ci_calculate_mclk_params(struct radeon_device *rdev,
2779 struct ci_power_info *pi = ci_get_pi(rdev);
2792 ret = radeon_atom_get_memory_pll_dividers(rdev, memory_clock, strobe_mode, &mpll_param);
2816 u32 reference_clock = rdev->clock.mpll.reference_freq;
2825 if (radeon_atombios_get_asic_ss_info(rdev, &ss,
2860 static int ci_populate_single_memory_level(struct radeon_device *rdev,
2864 struct ci_power_info *pi = ci_get_pi(rdev);
2868 if (rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk.entries) {
2869 ret = ci_get_dependency_volt_by_clk(rdev,
2870 &rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk,
2876 if (rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk.entries) {
2877 ret = ci_get_dependency_volt_by_clk(rdev,
2878 &rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk,
2884 if (rdev->pm.dpm.dyn_state.mvdd_dependency_on_mclk.entries) {
2885 ret = ci_get_dependency_volt_by_clk(rdev,
2886 &rdev->pm.dpm.dyn_state.mvdd_dependency_on_mclk,
2895 ci_populate_phase_value_based_on_mclk(rdev,
2896 &rdev->pm.dpm.dyn_state.phase_shedding_limits_table,
2918 (rdev->pm.dpm.new_active_crtc_count <= 2))
2950 ret = ci_calculate_mclk_params(rdev, memory_clock, memory_level, memory_level->StrobeEnable, dll_state_on);
2974 static int ci_populate_smc_acpi_level(struct radeon_device *rdev,
2977 struct ci_power_info *pi = ci_get_pi(rdev);
2995 table->ACPILevel.SclkFrequency = rdev->clock.spll.reference_freq;
2997 ret = radeon_atom_get_clock_dividers(rdev,
3046 if (ci_populate_mvdd_value(rdev, 0, &voltage_level))
3090 static int ci_enable_ulv(struct radeon_device *rdev, bool enable)
3092 struct ci_power_info *pi = ci_get_pi(rdev);
3097 return (ci_send_msg_to_smc(rdev, PPSMC_MSG_EnableULV) == PPSMC_Result_OK) ?
3100 return (ci_send_msg_to_smc(rdev, PPSMC_MSG_DisableULV) == PPSMC_Result_OK) ?
3107 static int ci_populate_ulv_level(struct radeon_device *rdev,
3110 struct ci_power_info *pi = ci_get_pi(rdev);
3111 u16 ulv_voltage = rdev->pm.dpm.backbias_response_time;
3122 if (ulv_voltage > rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[0].v)
3126 rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[0].v - ulv_voltage;
3128 if (ulv_voltage > rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[0].v)
3132 ((rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[0].v - ulv_voltage) *
3144 static int ci_calculate_sclk_params(struct radeon_device *rdev,
3148 struct ci_power_info *pi = ci_get_pi(rdev);
3154 u32 reference_clock = rdev->clock.spll.reference_freq;
3159 ret = radeon_atom_get_clock_dividers(rdev,
3176 if (radeon_atombios_get_asic_ss_info(rdev, &ss,
3200 static int ci_populate_single_graphic_level(struct radeon_device *rdev,
3205 struct ci_power_info *pi = ci_get_pi(rdev);
3208 ret = ci_calculate_sclk_params(rdev, engine_clock, graphic_level);
3212 ret = ci_get_dependency_volt_by_clk(rdev,
3213 &rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk,
3224 ci_populate_phase_value_based_on_sclk(rdev,
3225 &rdev->pm.dpm.dyn_state.phase_shedding_limits_table,
3240 graphic_level->DeepSleepDivId = ci_get_sleep_divider_id_from_clock(rdev,
3261 static int ci_populate_all_graphic_levels(struct radeon_device *rdev)
3263 struct ci_power_info *pi = ci_get_pi(rdev);
3275 ret = ci_populate_single_graphic_level(rdev,
3293 ret = ci_copy_bytes_to_smc(rdev, level_array_address,
3302 static int ci_populate_ulv_state(struct radeon_device *rdev,
3305 return ci_populate_ulv_level(rdev, ulv_level);
3308 static int ci_populate_all_memory_levels(struct radeon_device *rdev)
3310 struct ci_power_info *pi = ci_get_pi(rdev);
3324 ret = ci_populate_single_memory_level(rdev,
3334 ((rdev->pdev->device == 0x67B0) || (rdev->pdev->device == 0x67B1))) {
3350 ret = ci_copy_bytes_to_smc(rdev, level_array_address,
3359 static void ci_reset_single_dpm_table(struct radeon_device *rdev,
3378 static int ci_setup_default_pcie_tables(struct radeon_device *rdev)
3380 struct ci_power_info *pi = ci_get_pi(rdev);
3393 ci_reset_single_dpm_table(rdev,
3397 if (rdev->family == CHIP_BONAIRE)
3426 static int ci_setup_default_dpm_tables(struct radeon_device *rdev)
3428 struct ci_power_info *pi = ci_get_pi(rdev);
3430 &rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk;
3432 &rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk;
3434 &rdev->pm.dpm.dyn_state.cac_leakage_table;
3448 ci_reset_single_dpm_table(rdev,
3451 ci_reset_single_dpm_table(rdev,
3454 ci_reset_single_dpm_table(rdev,
3457 ci_reset_single_dpm_table(rdev,
3460 ci_reset_single_dpm_table(rdev,
3499 allowed_mclk_table = &rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk;
3509 allowed_mclk_table = &rdev->pm.dpm.dyn_state.mvdd_dependency_on_mclk;
3519 ci_setup_default_pcie_tables(rdev);
3540 static int ci_init_smc_table(struct radeon_device *rdev)
3542 struct ci_power_info *pi = ci_get_pi(rdev);
3544 struct radeon_ps *radeon_boot_state = rdev->pm.dpm.boot_ps;
3548 ret = ci_setup_default_dpm_tables(rdev);
3553 ci_populate_smc_voltage_tables(rdev, table);
3555 ci_init_fps_limits(rdev);
3557 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_HARDWAREDC)
3560 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_STEPVDDC)
3567 ret = ci_populate_ulv_state(rdev, &pi->smc_state_table.Ulv);
3573 ret = ci_populate_all_graphic_levels(rdev);
3577 ret = ci_populate_all_memory_levels(rdev);
3581 ci_populate_smc_link_level(rdev, table);
3583 ret = ci_populate_smc_acpi_level(rdev, table);
3587 ret = ci_populate_smc_vce_level(rdev, table);
3591 ret = ci_populate_smc_acp_level(rdev, table);
3595 ret = ci_populate_smc_samu_level(rdev, table);
3599 ret = ci_do_program_memory_timing_parameters(rdev);
3603 ret = ci_populate_smc_uvd_level(rdev, table);
3626 ci_populate_smc_initial_state(rdev, radeon_boot_state);
3628 ret = ci_populate_bapm_parameters_in_dpm_table(rdev);
3676 ret = ci_copy_bytes_to_smc(rdev,
3688 static void ci_trim_single_dpm_states(struct radeon_device *rdev,
3703 static void ci_trim_pcie_dpm_states(struct radeon_device *rdev,
3707 struct ci_power_info *pi = ci_get_pi(rdev);
3734 static int ci_trim_dpm_states(struct radeon_device *rdev,
3738 struct ci_power_info *pi = ci_get_pi(rdev);
3749 ci_trim_single_dpm_states(rdev,
3754 ci_trim_single_dpm_states(rdev,
3759 ci_trim_pcie_dpm_states(rdev,
3768 static int ci_apply_disp_minimum_voltage_request(struct radeon_device *rdev)
3771 &rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk;
3773 &rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk;
3783 if (rdev->clock.current_dispclk == disp_voltage_table->entries[i].clk)
3790 return (ci_send_msg_to_smc_with_parameter(rdev,
3800 static int ci_upload_dpm_level_enable_mask(struct radeon_device *rdev)
3802 struct ci_power_info *pi = ci_get_pi(rdev);
3805 ci_apply_disp_minimum_voltage_request(rdev);
3809 result = ci_send_msg_to_smc_with_parameter(rdev,
3819 result = ci_send_msg_to_smc_with_parameter(rdev,
3829 result = ci_send_msg_to_smc_with_parameter(rdev,
3840 static void ci_find_dpm_states_clocks_in_dpm_table(struct radeon_device *rdev,
3843 struct ci_power_info *pi = ci_get_pi(rdev);
3877 if (rdev->pm.dpm.current_active_crtc_count !=
3878 rdev->pm.dpm.new_active_crtc_count)
3882 static int ci_populate_and_upload_sclk_mclk_dpm_levels(struct radeon_device *rdev,
3885 struct ci_power_info *pi = ci_get_pi(rdev);
3902 ret = ci_populate_all_graphic_levels(rdev);
3908 ret = ci_populate_all_memory_levels(rdev);
3916 static int ci_enable_uvd_dpm(struct radeon_device *rdev, bool enable)
3918 struct ci_power_info *pi = ci_get_pi(rdev);
3922 if (rdev->pm.dpm.ac_power)
3923 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac;
3925 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc;
3930 for (i = rdev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.count - 1; i >= 0; i--) {
3931 if (rdev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.entries[i].v <= max_limits->vddc) {
3939 ci_send_msg_to_smc_with_parameter(rdev,
3946 ci_send_msg_to_smc_with_parameter(rdev,
3954 ci_send_msg_to_smc_with_parameter(rdev,
3960 return (ci_send_msg_to_smc(rdev, enable ?
3965 static int ci_enable_vce_dpm(struct radeon_device *rdev, bool enable)
3967 struct ci_power_info *pi = ci_get_pi(rdev);
3971 if (rdev->pm.dpm.ac_power)
3972 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac;
3974 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc;
3978 for (i = rdev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table.count - 1; i >= 0; i--) {
3979 if (rdev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table.entries[i].v <= max_limits->vddc) {
3987 ci_send_msg_to_smc_with_parameter(rdev,
3992 return (ci_send_msg_to_smc(rdev, enable ?
3998 static int ci_enable_samu_dpm(struct radeon_device *rdev, bool enable)
4000 struct ci_power_info *pi = ci_get_pi(rdev);
4004 if (rdev->pm.dpm.ac_power)
4005 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac;
4007 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc;
4011 for (i = rdev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table.count - 1; i >= 0; i--) {
4012 if (rdev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table.entries[i].v <= max_limits->vddc) {
4020 ci_send_msg_to_smc_with_parameter(rdev,
4024 return (ci_send_msg_to_smc(rdev, enable ?
4029 static int ci_enable_acp_dpm(struct radeon_device *rdev, bool enable)
4031 struct ci_power_info *pi = ci_get_pi(rdev);
4035 if (rdev->pm.dpm.ac_power)
4036 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac;
4038 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc;
4042 for (i = rdev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table.count - 1; i >= 0; i--) {
4043 if (rdev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table.entries[i].v <= max_limits->vddc) {
4051 ci_send_msg_to_smc_with_parameter(rdev,
4056 return (ci_send_msg_to_smc(rdev, enable ?
4062 static int ci_update_uvd_dpm(struct radeon_device *rdev, bool gate)
4064 struct ci_power_info *pi = ci_get_pi(rdev);
4069 (rdev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.count <= 0))
4073 rdev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.count - 1;
4081 return ci_enable_uvd_dpm(rdev, !gate);
4084 static u8 ci_get_vce_boot_level(struct radeon_device *rdev)
4089 &rdev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table;
4099 static int ci_update_vce_dpm(struct radeon_device *rdev,
4103 struct ci_power_info *pi = ci_get_pi(rdev);
4110 cik_update_cg(rdev, RADEON_CG_BLOCK_VCE, false);
4112 pi->smc_state_table.VceBootLevel = ci_get_vce_boot_level(rdev);
4118 ret = ci_enable_vce_dpm(rdev, true);
4121 cik_update_cg(rdev, RADEON_CG_BLOCK_VCE, true);
4123 ret = ci_enable_vce_dpm(rdev, false);
4130 static int ci_update_samu_dpm(struct radeon_device *rdev, bool gate)
4132 return ci_enable_samu_dpm(rdev, gate);
4135 static int ci_update_acp_dpm(struct radeon_device *rdev, bool gate)
4137 struct ci_power_info *pi = ci_get_pi(rdev);
4149 return ci_enable_acp_dpm(rdev, !gate);
4153 static int ci_generate_dpm_level_enable_mask(struct radeon_device *rdev,
4156 struct ci_power_info *pi = ci_get_pi(rdev);
4159 ret = ci_trim_dpm_states(rdev, radeon_state);
4179 static u32 ci_get_lowest_enabled_level(struct radeon_device *rdev,
4191 int ci_dpm_force_performance_level(struct radeon_device *rdev,
4194 struct ci_power_info *pi = ci_get_pi(rdev);
4206 ret = ci_dpm_force_state_pcie(rdev, level);
4209 for (i = 0; i < rdev->usec_timeout; i++) {
4225 ret = ci_dpm_force_state_sclk(rdev, levels);
4228 for (i = 0; i < rdev->usec_timeout; i++) {
4244 ret = ci_dpm_force_state_mclk(rdev, levels);
4247 for (i = 0; i < rdev->usec_timeout; i++) {
4259 levels = ci_get_lowest_enabled_level(rdev,
4261 ret = ci_dpm_force_state_sclk(rdev, levels);
4264 for (i = 0; i < rdev->usec_timeout; i++) {
4274 levels = ci_get_lowest_enabled_level(rdev,
4276 ret = ci_dpm_force_state_mclk(rdev, levels);
4279 for (i = 0; i < rdev->usec_timeout; i++) {
4289 levels = ci_get_lowest_enabled_level(rdev,
4291 ret = ci_dpm_force_state_pcie(rdev, levels);
4294 for (i = 0; i < rdev->usec_timeout; i++) {
4306 smc_result = ci_send_msg_to_smc(rdev,
4311 ret = ci_upload_dpm_level_enable_mask(rdev);
4316 rdev->pm.dpm.forced_level = level;
4321 static int ci_set_mc_special_registers(struct radeon_device *rdev,
4324 struct ci_power_info *pi = ci_get_pi(rdev);
4519 static int ci_register_patching_mc_seq(struct radeon_device *rdev,
4530 ((rdev->pdev->device == 0x67B0) ||
4531 (rdev->pdev->device == 0x67B1))) {
4609 static int ci_initialize_mc_reg_table(struct radeon_device *rdev)
4611 struct ci_power_info *pi = ci_get_pi(rdev);
4614 u8 module_index = rv770_get_memory_module_index(rdev);
4642 ret = radeon_atom_init_mc_reg_table(rdev, module_index, table);
4652 ret = ci_register_patching_mc_seq(rdev, ci_table);
4656 ret = ci_set_mc_special_registers(rdev, ci_table);
4668 static int ci_populate_mc_reg_addresses(struct radeon_device *rdev,
4671 struct ci_power_info *pi = ci_get_pi(rdev);
4703 static void ci_convert_mc_reg_table_entry_to_smc(struct radeon_device *rdev,
4707 struct ci_power_info *pi = ci_get_pi(rdev);
4723 static void ci_convert_mc_reg_table_to_smc(struct radeon_device *rdev,
4726 struct ci_power_info *pi = ci_get_pi(rdev);
4730 ci_convert_mc_reg_table_entry_to_smc(rdev,
4735 static int ci_populate_initial_mc_reg_table(struct radeon_device *rdev)
4737 struct ci_power_info *pi = ci_get_pi(rdev);
4742 ret = ci_populate_mc_reg_addresses(rdev, &pi->smc_mc_reg_table);
4745 ci_convert_mc_reg_table_to_smc(rdev, &pi->smc_mc_reg_table);
4747 return ci_copy_bytes_to_smc(rdev,
4754 static int ci_update_and_upload_mc_reg_table(struct radeon_device *rdev)
4756 struct ci_power_info *pi = ci_get_pi(rdev);
4763 ci_convert_mc_reg_table_to_smc(rdev, &pi->smc_mc_reg_table);
4765 return ci_copy_bytes_to_smc(rdev,
4774 static void ci_enable_voltage_control(struct radeon_device *rdev)
4782 static enum radeon_pcie_gen ci_get_maximum_link_speed(struct radeon_device *rdev,
4798 static u16 ci_get_current_pcie_speed(struct radeon_device *rdev)
4808 static int ci_get_current_pcie_lane_number(struct radeon_device *rdev)
4834 static void ci_request_link_speed_change_before_state_change(struct radeon_device *rdev,
4838 struct ci_power_info *pi = ci_get_pi(rdev);
4840 ci_get_maximum_link_speed(rdev, radeon_new_state);
4844 current_link_speed = ci_get_maximum_link_speed(rdev, radeon_current_state);
4854 if (radeon_acpi_pcie_performance_request(rdev, PCIE_PERF_REQ_PECI_GEN3, false) == 0)
4861 if (radeon_acpi_pcie_performance_request(rdev, PCIE_PERF_REQ_PECI_GEN2, false) == 0)
4866 pi->force_pcie_gen = ci_get_current_pcie_speed(rdev);
4875 static void ci_notify_link_speed_change_after_state_change(struct radeon_device *rdev,
4879 struct ci_power_info *pi = ci_get_pi(rdev);
4881 ci_get_maximum_link_speed(rdev, radeon_new_state);
4893 (ci_get_current_pcie_speed(rdev) > 0))
4897 radeon_acpi_pcie_performance_request(rdev, request, false);
4902 static int ci_set_private_data_variables_based_on_pptable(struct radeon_device *rdev)
4904 struct ci_power_info *pi = ci_get_pi(rdev);
4906 &rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk;
4908 &rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk;
4910 &rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk;
4933 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.sclk =
4935 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.mclk =
4937 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.vddc =
4939 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.vddci =
4945 static void ci_patch_with_vddc_leakage(struct radeon_device *rdev, u16 *vddc)
4947 struct ci_power_info *pi = ci_get_pi(rdev);
4959 static void ci_patch_with_vddci_leakage(struct radeon_device *rdev, u16 *vddci)
4961 struct ci_power_info *pi = ci_get_pi(rdev);
4973 static void ci_patch_clock_voltage_dependency_table_with_vddc_leakage(struct radeon_device *rdev,
4980 ci_patch_with_vddc_leakage(rdev, &table->entries[i].v);
4984 static void ci_patch_clock_voltage_dependency_table_with_vddci_leakage(struct radeon_device *rdev,
4991 ci_patch_with_vddci_leakage(rdev, &table->entries[i].v);
4995 static void ci_patch_vce_clock_voltage_dependency_table_with_vddc_leakage(struct radeon_device *rdev,
5002 ci_patch_with_vddc_leakage(rdev, &table->entries[i].v);
5006 static void ci_patch_uvd_clock_voltage_dependency_table_with_vddc_leakage(struct radeon_device *rdev,
5013 ci_patch_with_vddc_leakage(rdev, &table->entries[i].v);
5017 static void ci_patch_vddc_phase_shed_limit_table_with_vddc_leakage(struct radeon_device *rdev,
5024 ci_patch_with_vddc_leakage(rdev, &table->entries[i].voltage);
5028 static void ci_patch_clock_voltage_limits_with_vddc_leakage(struct radeon_device *rdev,
5032 ci_patch_with_vddc_leakage(rdev, (u16 *)&table->vddc);
5033 ci_patch_with_vddci_leakage(rdev, (u16 *)&table->vddci);
5037 static void ci_patch_cac_leakage_table_with_vddc_leakage(struct radeon_device *rdev,
5044 ci_patch_with_vddc_leakage(rdev, &table->entries[i].vddc);
5048 static void ci_patch_dependency_tables_with_leakage(struct radeon_device *rdev)
5051 ci_patch_clock_voltage_dependency_table_with_vddc_leakage(rdev,
5052 &rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk);
5053 ci_patch_clock_voltage_dependency_table_with_vddc_leakage(rdev,
5054 &rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk);
5055 ci_patch_clock_voltage_dependency_table_with_vddc_leakage(rdev,
5056 &rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk);
5057 ci_patch_clock_voltage_dependency_table_with_vddci_leakage(rdev,
5058 &rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk);
5059 ci_patch_vce_clock_voltage_dependency_table_with_vddc_leakage(rdev,
5060 &rdev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table);
5061 ci_patch_uvd_clock_voltage_dependency_table_with_vddc_leakage(rdev,
5062 &rdev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table);
5063 ci_patch_clock_voltage_dependency_table_with_vddc_leakage(rdev,
5064 &rdev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table);
5065 ci_patch_clock_voltage_dependency_table_with_vddc_leakage(rdev,
5066 &rdev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table);
5067 ci_patch_vddc_phase_shed_limit_table_with_vddc_leakage(rdev,
5068 &rdev->pm.dpm.dyn_state.phase_shedding_limits_table);
5069 ci_patch_clock_voltage_limits_with_vddc_leakage(rdev,
5070 &rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac);
5071 ci_patch_clock_voltage_limits_with_vddc_leakage(rdev,
5072 &rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc);
5073 ci_patch_cac_leakage_table_with_vddc_leakage(rdev,
5074 &rdev->pm.dpm.dyn_state.cac_leakage_table);
5078 static void ci_get_memory_type(struct radeon_device *rdev)
5080 struct ci_power_info *pi = ci_get_pi(rdev);
5093 static void ci_update_current_ps(struct radeon_device *rdev,
5097 struct ci_power_info *pi = ci_get_pi(rdev);
5104 static void ci_update_requested_ps(struct radeon_device *rdev,
5108 struct ci_power_info *pi = ci_get_pi(rdev);
5115 int ci_dpm_pre_set_power_state(struct radeon_device *rdev)
5117 struct ci_power_info *pi = ci_get_pi(rdev);
5118 struct radeon_ps requested_ps = *rdev->pm.dpm.requested_ps;
5121 ci_update_requested_ps(rdev, new_ps);
5123 ci_apply_state_adjust_rules(rdev, &pi->requested_rps);
5128 void ci_dpm_post_set_power_state(struct radeon_device *rdev)
5130 struct ci_power_info *pi = ci_get_pi(rdev);
5133 ci_update_current_ps(rdev, new_ps);
5137 void ci_dpm_setup_asic(struct radeon_device *rdev)
5141 r = ci_mc_load_microcode(rdev);
5144 ci_read_clock_registers(rdev);
5145 ci_get_memory_type(rdev);
5146 ci_enable_acpi_power_management(rdev);
5147 ci_init_sclk_t(rdev);
5150 int ci_dpm_enable(struct radeon_device *rdev)
5152 struct ci_power_info *pi = ci_get_pi(rdev);
5153 struct radeon_ps *boot_ps = rdev->pm.dpm.boot_ps;
5156 if (ci_is_smc_running(rdev))
5159 ci_enable_voltage_control(rdev);
5160 ret = ci_construct_voltage_tables(rdev);
5167 ret = ci_initialize_mc_reg_table(rdev);
5172 ci_enable_spread_spectrum(rdev, true);
5174 ci_enable_thermal_protection(rdev, true);
5175 ci_program_sstp(rdev);
5176 ci_enable_display_gap(rdev);
5177 ci_program_vc(rdev);
5178 ret = ci_upload_firmware(rdev);
5183 ret = ci_process_firmware_header(rdev);
5188 ret = ci_initial_switch_from_arb_f0_to_f1(rdev);
5193 ret = ci_init_smc_table(rdev);
5198 ret = ci_init_arb_table_index(rdev);
5204 ret = ci_populate_initial_mc_reg_table(rdev);
5210 ret = ci_populate_pm_base(rdev);
5215 ci_dpm_start_smc(rdev);
5216 ci_enable_vr_hot_gpio_interrupt(rdev);
5217 ret = ci_notify_smc_display_change(rdev, false);
5222 ci_enable_sclk_control(rdev, true);
5223 ret = ci_enable_ulv(rdev, true);
5228 ret = ci_enable_ds_master_switch(rdev, true);
5233 ret = ci_start_dpm(rdev);
5238 ret = ci_enable_didt(rdev, true);
5243 ret = ci_enable_smc_cac(rdev, true);
5248 ret = ci_enable_power_containment(rdev, true);
5254 ret = ci_power_control_set_level(rdev);
5260 ci_enable_auto_throttle_source(rdev, RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL, true);
5262 ret = ci_enable_thermal_based_sclk_dpm(rdev, true);
5268 ci_thermal_start_thermal_controller(rdev);
5270 ci_update_current_ps(rdev, boot_ps);
5275 static int ci_set_temperature_range(struct radeon_device *rdev)
5279 ret = ci_thermal_enable_alert(rdev, false);
5282 ret = ci_thermal_set_temperature_range(rdev, R600_TEMP_RANGE_MIN, R600_TEMP_RANGE_MAX);
5285 ret = ci_thermal_enable_alert(rdev, true);
5292 int ci_dpm_late_enable(struct radeon_device *rdev)
5296 ret = ci_set_temperature_range(rdev);
5300 ci_dpm_powergate_uvd(rdev, true);
5305 void ci_dpm_disable(struct radeon_device *rdev)
5307 struct ci_power_info *pi = ci_get_pi(rdev);
5308 struct radeon_ps *boot_ps = rdev->pm.dpm.boot_ps;
5310 ci_dpm_powergate_uvd(rdev, false);
5312 if (!ci_is_smc_running(rdev))
5315 ci_thermal_stop_thermal_controller(rdev);
5318 ci_enable_thermal_protection(rdev, false);
5319 ci_enable_power_containment(rdev, false);
5320 ci_enable_smc_cac(rdev, false);
5321 ci_enable_didt(rdev, false);
5322 ci_enable_spread_spectrum(rdev, false);
5323 ci_enable_auto_throttle_source(rdev, RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL, false);
5324 ci_stop_dpm(rdev);
5325 ci_enable_ds_master_switch(rdev, false);
5326 ci_enable_ulv(rdev, false);
5327 ci_clear_vc(rdev);
5328 ci_reset_to_default(rdev);
5329 ci_dpm_stop_smc(rdev);
5330 ci_force_switch_to_arb_f0(rdev);
5331 ci_enable_thermal_based_sclk_dpm(rdev, false);
5333 ci_update_current_ps(rdev, boot_ps);
5336 int ci_dpm_set_power_state(struct radeon_device *rdev)
5338 struct ci_power_info *pi = ci_get_pi(rdev);
5343 ci_find_dpm_states_clocks_in_dpm_table(rdev, new_ps);
5345 ci_request_link_speed_change_before_state_change(rdev, new_ps, old_ps);
5346 ret = ci_freeze_sclk_mclk_dpm(rdev);
5351 ret = ci_populate_and_upload_sclk_mclk_dpm_levels(rdev, new_ps);
5356 ret = ci_generate_dpm_level_enable_mask(rdev, new_ps);
5362 ret = ci_update_vce_dpm(rdev, new_ps, old_ps);
5368 ret = ci_update_sclk_t(rdev);
5374 ret = ci_update_and_upload_mc_reg_table(rdev);
5380 ret = ci_program_memory_timing_parameters(rdev);
5385 ret = ci_unfreeze_sclk_mclk_dpm(rdev);
5390 ret = ci_upload_dpm_level_enable_mask(rdev);
5396 ci_notify_link_speed_change_after_state_change(rdev, new_ps, old_ps);
5402 void ci_dpm_reset_asic(struct radeon_device *rdev)
5404 ci_set_boot_state(rdev);
5408 void ci_dpm_display_configuration_changed(struct radeon_device *rdev)
5410 ci_program_display_gap(rdev);
5436 static void ci_parse_pplib_non_clock_info(struct radeon_device *rdev,
5454 rdev->pm.dpm.boot_ps = rps;
5456 rdev->pm.dpm.uvd_ps = rps;
5459 static void ci_parse_pplib_clock_info(struct radeon_device *rdev,
5463 struct ci_power_info *pi = ci_get_pi(rdev);
5474 pl->pcie_gen = r600_get_pcie_gen_support(rdev,
5478 pl->pcie_lane = r600_get_pcie_lane_support(rdev,
5528 static int ci_parse_power_table(struct radeon_device *rdev)
5530 struct radeon_mode_info *mode_info = &rdev->mode_info;
5561 rdev->pm.dpm.ps = kcalloc(state_array->ucNumEntries,
5564 if (!rdev->pm.dpm.ps)
5567 rdev->pm.dpm.num_ps = 0;
5574 if (!rdev->pm.power_state[i].clock_info) {
5583 rdev->pm.dpm.ps[i].ps_priv = ps;
5584 ci_parse_pplib_non_clock_info(rdev, &rdev->pm.dpm.ps[i],
5598 ci_parse_pplib_clock_info(rdev,
5599 &rdev->pm.dpm.ps[i], k,
5604 rdev->pm.dpm.num_ps = i + 1;
5610 clock_array_index = rdev->pm.dpm.vce_states[i].clk_idx;
5617 rdev->pm.dpm.vce_states[i].sclk = sclk;
5618 rdev->pm.dpm.vce_states[i].mclk = mclk;
5624 for (i = 0; i < rdev->pm.dpm.num_ps; i++)
5625 kfree(rdev->pm.dpm.ps[i].ps_priv);
5626 kfree(rdev->pm.dpm.ps);
5630 static int ci_get_vbios_boot_values(struct radeon_device *rdev,
5633 struct radeon_mode_info *mode_info = &rdev->mode_info;
5647 boot_state->pcie_gen_bootup_value = ci_get_current_pcie_speed(rdev);
5648 boot_state->pcie_lane_bootup_value = ci_get_current_pcie_lane_number(rdev);
5657 void ci_dpm_fini(struct radeon_device *rdev)
5661 for (i = 0; i < rdev->pm.dpm.num_ps; i++) {
5662 kfree(rdev->pm.dpm.ps[i].ps_priv);
5664 kfree(rdev->pm.dpm.ps);
5665 kfree(rdev->pm.dpm.priv);
5666 kfree(rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries);
5667 r600_free_extended_power_table(rdev);
5670 int ci_dpm_init(struct radeon_device *rdev)
5679 struct pci_dev *root = rdev->pdev->bus->self;
5685 rdev->pm.dpm.priv = pi;
5687 if (!pci_is_root_bus(rdev->pdev->bus))
5714 ret = ci_get_vbios_boot_values(rdev, &pi->vbios_boot_state);
5716 kfree(rdev->pm.dpm.priv);
5720 ret = r600_get_platform_caps(rdev);
5722 kfree(rdev->pm.dpm.priv);
5726 ret = r600_parse_extended_power_table(rdev);
5728 kfree(rdev->pm.dpm.priv);
5732 ret = ci_parse_power_table(rdev);
5734 kfree(rdev->pm.dpm.priv);
5735 r600_free_extended_power_table(rdev);
5759 if ((rdev->pdev->device == 0x6658) &&
5760 (rdev->mc_fw->size == (BONAIRE_MC_UCODE_SIZE * 4))) {
5771 ci_initialize_powertune_defaults(rdev);
5780 ci_get_leakage_voltages(rdev);
5781 ci_patch_dependency_tables_with_leakage(rdev);
5782 ci_set_private_data_variables_based_on_pptable(rdev);
5784 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries =
5788 if (!rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries) {
5789 ci_dpm_fini(rdev);
5792 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.count = 4;
5793 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[0].clk = 0;
5794 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[0].v = 0;
5795 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[1].clk = 36000;
5796 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[1].v = 720;
5797 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[2].clk = 54000;
5798 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[2].v = 810;
5799 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[3].clk = 72000;
5800 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[3].v = 900;
5802 rdev->pm.dpm.dyn_state.mclk_sclk_ratio = 4;
5803 rdev->pm.dpm.dyn_state.sclk_mclk_delta = 15000;
5804 rdev->pm.dpm.dyn_state.vddc_vddci_delta = 200;
5806 rdev->pm.dpm.dyn_state.valid_sclk_values.count = 0;
5807 rdev->pm.dpm.dyn_state.valid_sclk_values.values = NULL;
5808 rdev->pm.dpm.dyn_state.valid_mclk_values.count = 0;
5809 rdev->pm.dpm.dyn_state.valid_mclk_values.values = NULL;
5811 if (rdev->family == CHIP_HAWAII) {
5825 gpio = radeon_atombios_lookup_gpio(rdev, VDDC_VRHOT_GPIO_PINID);
5828 rdev->pm.dpm.platform_caps |= ATOM_PP_PLATFORM_CAP_REGULATOR_HOT;
5831 rdev->pm.dpm.platform_caps &= ~ATOM_PP_PLATFORM_CAP_REGULATOR_HOT;
5834 gpio = radeon_atombios_lookup_gpio(rdev, PP_AC_DC_SWITCH_GPIO_PINID);
5837 rdev->pm.dpm.platform_caps |= ATOM_PP_PLATFORM_CAP_HARDWAREDC;
5840 rdev->pm.dpm.platform_caps &= ~ATOM_PP_PLATFORM_CAP_HARDWAREDC;
5843 gpio = radeon_atombios_lookup_gpio(rdev, VDDC_PCC_GPIO_PINID);
5875 if (radeon_atom_is_voltage_gpio(rdev, VOLTAGE_TYPE_VDDC, VOLTAGE_OBJ_GPIO_LUT))
5877 else if (radeon_atom_is_voltage_gpio(rdev, VOLTAGE_TYPE_VDDC, VOLTAGE_OBJ_SVID2))
5880 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_VDDCI_CONTROL) {
5881 if (radeon_atom_is_voltage_gpio(rdev, VOLTAGE_TYPE_VDDCI, VOLTAGE_OBJ_GPIO_LUT))
5883 else if (radeon_atom_is_voltage_gpio(rdev, VOLTAGE_TYPE_VDDCI, VOLTAGE_OBJ_SVID2))
5886 rdev->pm.dpm.platform_caps &= ~ATOM_PP_PLATFORM_CAP_VDDCI_CONTROL;
5889 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_MVDDCONTROL) {
5890 if (radeon_atom_is_voltage_gpio(rdev, VOLTAGE_TYPE_MVDDC, VOLTAGE_OBJ_GPIO_LUT))
5892 else if (radeon_atom_is_voltage_gpio(rdev, VOLTAGE_TYPE_MVDDC, VOLTAGE_OBJ_SVID2))
5895 rdev->pm.dpm.platform_caps &= ~ATOM_PP_PLATFORM_CAP_MVDDCONTROL;
5902 radeon_acpi_is_pcie_performance_request_supported(rdev);
5907 if (atom_parse_data_header(rdev->mode_info.atom_context, index, &size,
5918 if (rdev->pm.int_thermal_type != THERMAL_TYPE_NONE)
5928 if ((rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc.sclk == 0) ||
5929 (rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc.mclk == 0))
5930 rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc =
5931 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac;
5938 void ci_dpm_debugfs_print_current_performance_level(struct radeon_device *rdev,
5941 struct ci_power_info *pi = ci_get_pi(rdev);
5943 u32 sclk = ci_get_average_sclk_freq(rdev);
5944 u32 mclk = ci_get_average_mclk_freq(rdev);
5952 void ci_dpm_print_power_state(struct radeon_device *rdev,
5967 r600_dpm_print_ps_status(rdev, rps);
5970 u32 ci_dpm_get_current_sclk(struct radeon_device *rdev)
5972 u32 sclk = ci_get_average_sclk_freq(rdev);
5977 u32 ci_dpm_get_current_mclk(struct radeon_device *rdev)
5979 u32 mclk = ci_get_average_mclk_freq(rdev);
5984 u32 ci_dpm_get_sclk(struct radeon_device *rdev, bool low)
5986 struct ci_power_info *pi = ci_get_pi(rdev);
5995 u32 ci_dpm_get_mclk(struct radeon_device *rdev, bool low)
5997 struct ci_power_info *pi = ci_get_pi(rdev);