Lines Matching defs:rdev
52 struct rv7xx_power_info *rv770_get_pi(struct radeon_device *rdev);
53 struct evergreen_power_info *evergreen_get_pi(struct radeon_device *rdev);
55 extern int ni_mc_load_microcode(struct radeon_device *rdev);
1228 static u32 btc_get_valid_mclk(struct radeon_device *rdev,
1231 return btc_find_valid_clock(&rdev->pm.dpm.dyn_state.valid_mclk_values,
1235 static u32 btc_get_valid_sclk(struct radeon_device *rdev,
1238 return btc_find_valid_clock(&rdev->pm.dpm.dyn_state.valid_sclk_values,
1242 void btc_skip_blacklist_clocks(struct radeon_device *rdev,
1261 *sclk = btc_get_valid_sclk(rdev, max_sclk, *sclk + 1);
1264 btc_skip_blacklist_clocks(rdev, max_sclk, max_mclk, sclk, mclk);
1269 void btc_adjust_clock_combinations(struct radeon_device *rdev,
1281 if (((pl->mclk + (pl->sclk - 1)) / pl->sclk) > rdev->pm.dpm.dyn_state.mclk_sclk_ratio)
1282 pl->sclk = btc_get_valid_sclk(rdev,
1285 (rdev->pm.dpm.dyn_state.mclk_sclk_ratio - 1)) /
1286 rdev->pm.dpm.dyn_state.mclk_sclk_ratio);
1288 if ((pl->sclk - pl->mclk) > rdev->pm.dpm.dyn_state.sclk_mclk_delta)
1289 pl->mclk = btc_get_valid_mclk(rdev,
1292 rdev->pm.dpm.dyn_state.sclk_mclk_delta);
1308 void btc_apply_voltage_delta_rules(struct radeon_device *rdev,
1312 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
1319 if ((*vddc - *vddci) > rdev->pm.dpm.dyn_state.vddc_vddci_delta) {
1321 (*vddc - rdev->pm.dpm.dyn_state.vddc_vddci_delta));
1325 if ((*vddci - *vddc) > rdev->pm.dpm.dyn_state.vddc_vddci_delta) {
1327 (*vddci - rdev->pm.dpm.dyn_state.vddc_vddci_delta));
1333 static void btc_enable_bif_dynamic_pcie_gen2(struct radeon_device *rdev,
1336 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
1375 static void btc_enable_dynamic_pcie_gen2(struct radeon_device *rdev,
1378 btc_enable_bif_dynamic_pcie_gen2(rdev, enable);
1386 static int btc_disable_ulv(struct radeon_device *rdev)
1388 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
1391 if (rv770_send_msg_to_smc(rdev, PPSMC_MSG_DisableULV) != PPSMC_Result_OK)
1397 static int btc_populate_ulv_state(struct radeon_device *rdev,
1401 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
1405 ret = cypress_convert_power_level_to_smc(rdev,
1426 static int btc_populate_smc_acpi_state(struct radeon_device *rdev,
1429 int ret = cypress_populate_smc_acpi_state(rdev, table);
1440 void btc_program_mgcg_hw_sequence(struct radeon_device *rdev,
1454 static void btc_cg_clock_gating_default(struct radeon_device *rdev)
1459 if (rdev->family == CHIP_BARTS) {
1462 } else if (rdev->family == CHIP_TURKS) {
1465 } else if (rdev->family == CHIP_CAICOS) {
1471 btc_program_mgcg_hw_sequence(rdev, p, count);
1474 static void btc_cg_clock_gating_enable(struct radeon_device *rdev,
1481 if (rdev->family == CHIP_BARTS) {
1484 } else if (rdev->family == CHIP_TURKS) {
1487 } else if (rdev->family == CHIP_CAICOS) {
1493 if (rdev->family == CHIP_BARTS) {
1496 } else if (rdev->family == CHIP_TURKS) {
1499 } else if (rdev->family == CHIP_CAICOS) {
1506 btc_program_mgcg_hw_sequence(rdev, p, count);
1509 static void btc_mg_clock_gating_default(struct radeon_device *rdev)
1514 if (rdev->family == CHIP_BARTS) {
1517 } else if (rdev->family == CHIP_TURKS) {
1520 } else if (rdev->family == CHIP_CAICOS) {
1526 btc_program_mgcg_hw_sequence(rdev, p, count);
1529 static void btc_mg_clock_gating_enable(struct radeon_device *rdev,
1536 if (rdev->family == CHIP_BARTS) {
1539 } else if (rdev->family == CHIP_TURKS) {
1542 } else if (rdev->family == CHIP_CAICOS) {
1548 if (rdev->family == CHIP_BARTS) {
1551 } else if (rdev->family == CHIP_TURKS) {
1554 } else if (rdev->family == CHIP_CAICOS) {
1561 btc_program_mgcg_hw_sequence(rdev, p, count);
1564 static void btc_ls_clock_gating_default(struct radeon_device *rdev)
1569 if (rdev->family == CHIP_BARTS) {
1572 } else if (rdev->family == CHIP_TURKS) {
1575 } else if (rdev->family == CHIP_CAICOS) {
1581 btc_program_mgcg_hw_sequence(rdev, p, count);
1584 static void btc_ls_clock_gating_enable(struct radeon_device *rdev,
1591 if (rdev->family == CHIP_BARTS) {
1594 } else if (rdev->family == CHIP_TURKS) {
1597 } else if (rdev->family == CHIP_CAICOS) {
1603 if (rdev->family == CHIP_BARTS) {
1606 } else if (rdev->family == CHIP_TURKS) {
1609 } else if (rdev->family == CHIP_CAICOS) {
1616 btc_program_mgcg_hw_sequence(rdev, p, count);
1619 bool btc_dpm_enabled(struct radeon_device *rdev)
1621 if (rv770_is_smc_running(rdev))
1627 static int btc_init_smc_table(struct radeon_device *rdev,
1630 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
1631 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
1637 cypress_populate_smc_voltage_tables(rdev, table);
1639 switch (rdev->pm.int_thermal_type) {
1652 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_HARDWAREDC)
1655 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_REGULATOR_HOT)
1658 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_STEPVDDC)
1664 ret = cypress_populate_smc_initial_state(rdev, radeon_boot_state, table);
1672 ret = btc_populate_smc_acpi_state(rdev, table);
1677 ret = btc_populate_ulv_state(rdev, table);
1684 return rv770_copy_bytes_to_smc(rdev,
1691 static void btc_set_at_for_uvd(struct radeon_device *rdev,
1694 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
1695 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
1715 void btc_notify_uvd_to_smc(struct radeon_device *rdev,
1718 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
1721 rv770_write_smc_soft_register(rdev,
1725 rv770_write_smc_soft_register(rdev,
1731 int btc_reset_to_default(struct radeon_device *rdev)
1733 if (rv770_send_msg_to_smc(rdev, PPSMC_MSG_ResetToDefaults) != PPSMC_Result_OK)
1739 static void btc_stop_smc(struct radeon_device *rdev)
1743 for (i = 0; i < rdev->usec_timeout; i++) {
1750 r7xx_stop_smc(rdev);
1753 void btc_read_arb_registers(struct radeon_device *rdev)
1755 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
1766 static void btc_set_arb0_registers(struct radeon_device *rdev,
1783 static void btc_set_boot_state_timing(struct radeon_device *rdev)
1785 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
1788 btc_set_arb0_registers(rdev, &eg_pi->bootup_arb_registers);
1791 static bool btc_is_state_ulv_compatible(struct radeon_device *rdev,
1795 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
1810 static int btc_set_ulv_dram_timing(struct radeon_device *rdev)
1813 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
1816 radeon_atom_set_engine_dram_timings(rdev,
1820 val = rv770_calculate_memory_refresh_rate(rdev, ulv_pl->sclk);
1823 val = cypress_calculate_burst_time(rdev, ulv_pl->sclk, ulv_pl->mclk);
1829 static int btc_enable_ulv(struct radeon_device *rdev)
1831 if (rv770_send_msg_to_smc(rdev, PPSMC_MSG_EnableULV) != PPSMC_Result_OK)
1837 static int btc_set_power_state_conditionally_enable_ulv(struct radeon_device *rdev,
1841 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
1844 if (btc_is_state_ulv_compatible(rdev, radeon_new_state)) {
1846 ret = btc_set_ulv_dram_timing(rdev);
1848 ret = btc_enable_ulv(rdev);
1916 static int btc_set_mc_special_registers(struct radeon_device *rdev,
1919 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
2017 static int btc_initialize_mc_reg_table(struct radeon_device *rdev)
2021 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
2023 u8 module_index = rv770_get_memory_module_index(rdev);
2042 ret = radeon_atom_init_mc_reg_table(rdev, module_index, table);
2053 ret = btc_set_mc_special_registers(rdev, eg_table);
2066 static void btc_init_stutter_mode(struct radeon_device *rdev)
2068 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
2082 bool btc_dpm_vblank_too_short(struct radeon_device *rdev)
2084 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
2085 u32 vblank_time = r600_dpm_get_vblank_time(rdev);
2095 static void btc_apply_state_adjust_rules(struct radeon_device *rdev,
2104 if ((rdev->pm.dpm.new_active_crtc_count > 1) ||
2105 btc_dpm_vblank_too_short(rdev))
2110 if (rdev->pm.dpm.ac_power)
2111 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac;
2113 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc;
2115 if (rdev->pm.dpm.ac_power == false) {
2164 btc_skip_blacklist_clocks(rdev, max_limits->sclk, max_limits->mclk,
2200 btc_skip_blacklist_clocks(rdev, max_limits->sclk, max_limits->mclk,
2202 btc_skip_blacklist_clocks(rdev, max_limits->sclk, max_limits->mclk,
2205 btc_adjust_clock_combinations(rdev, max_limits, &ps->low);
2206 btc_adjust_clock_combinations(rdev, max_limits, &ps->medium);
2207 btc_adjust_clock_combinations(rdev, max_limits, &ps->high);
2209 btc_apply_voltage_dependency_rules(&rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk,
2211 btc_apply_voltage_dependency_rules(&rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk,
2213 btc_apply_voltage_dependency_rules(&rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk,
2215 btc_apply_voltage_dependency_rules(&rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk,
2216 rdev->clock.current_dispclk, max_limits->vddc, &ps->low.vddc);
2218 btc_apply_voltage_dependency_rules(&rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk,
2220 btc_apply_voltage_dependency_rules(&rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk,
2222 btc_apply_voltage_dependency_rules(&rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk,
2224 btc_apply_voltage_dependency_rules(&rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk,
2225 rdev->clock.current_dispclk, max_limits->vddc, &ps->medium.vddc);
2227 btc_apply_voltage_dependency_rules(&rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk,
2229 btc_apply_voltage_dependency_rules(&rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk,
2231 btc_apply_voltage_dependency_rules(&rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk,
2233 btc_apply_voltage_dependency_rules(&rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk,
2234 rdev->clock.current_dispclk, max_limits->vddc, &ps->high.vddc);
2236 btc_apply_voltage_delta_rules(rdev, max_limits->vddc, max_limits->vddci,
2238 btc_apply_voltage_delta_rules(rdev, max_limits->vddc, max_limits->vddci,
2240 btc_apply_voltage_delta_rules(rdev, max_limits->vddc, max_limits->vddci,
2243 if ((ps->high.vddc <= rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc.vddc) &&
2244 (ps->medium.vddc <= rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc.vddc) &&
2245 (ps->low.vddc <= rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc.vddc))
2250 if (ps->low.vddc < rdev->pm.dpm.dyn_state.min_vddc_for_pcie_gen2)
2252 if (ps->medium.vddc < rdev->pm.dpm.dyn_state.min_vddc_for_pcie_gen2)
2254 if (ps->high.vddc < rdev->pm.dpm.dyn_state.min_vddc_for_pcie_gen2)
2258 static void btc_update_current_ps(struct radeon_device *rdev,
2262 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
2269 static void btc_update_requested_ps(struct radeon_device *rdev,
2273 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
2281 void btc_dpm_reset_asic(struct radeon_device *rdev)
2283 rv770_restrict_performance_levels_before_switch(rdev);
2284 btc_disable_ulv(rdev);
2285 btc_set_boot_state_timing(rdev);
2286 rv770_set_boot_state(rdev);
2290 int btc_dpm_pre_set_power_state(struct radeon_device *rdev)
2292 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
2293 struct radeon_ps requested_ps = *rdev->pm.dpm.requested_ps;
2296 btc_update_requested_ps(rdev, new_ps);
2298 btc_apply_state_adjust_rules(rdev, &eg_pi->requested_rps);
2303 int btc_dpm_set_power_state(struct radeon_device *rdev)
2305 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
2310 ret = btc_disable_ulv(rdev);
2311 btc_set_boot_state_timing(rdev);
2312 ret = rv770_restrict_performance_levels_before_switch(rdev);
2318 cypress_notify_link_speed_change_before_state_change(rdev, new_ps, old_ps);
2320 rv770_set_uvd_clock_before_set_eng_clock(rdev, new_ps, old_ps);
2321 ret = rv770_halt_smc(rdev);
2326 btc_set_at_for_uvd(rdev, new_ps);
2328 btc_notify_uvd_to_smc(rdev, new_ps);
2329 ret = cypress_upload_sw_state(rdev, new_ps);
2335 ret = cypress_upload_mc_reg_table(rdev, new_ps);
2342 cypress_program_memory_timing_parameters(rdev, new_ps);
2344 ret = rv770_resume_smc(rdev);
2349 ret = rv770_set_sw_state(rdev);
2354 rv770_set_uvd_clock_after_set_eng_clock(rdev, new_ps, old_ps);
2357 cypress_notify_link_speed_change_after_state_change(rdev, new_ps, old_ps);
2359 ret = btc_set_power_state_conditionally_enable_ulv(rdev, new_ps);
2368 void btc_dpm_post_set_power_state(struct radeon_device *rdev)
2370 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
2373 btc_update_current_ps(rdev, new_ps);
2376 int btc_dpm_enable(struct radeon_device *rdev)
2378 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
2379 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
2380 struct radeon_ps *boot_ps = rdev->pm.dpm.boot_ps;
2384 btc_cg_clock_gating_default(rdev);
2386 if (btc_dpm_enabled(rdev))
2390 btc_mg_clock_gating_default(rdev);
2393 btc_ls_clock_gating_default(rdev);
2396 rv770_enable_voltage_control(rdev, true);
2397 ret = cypress_construct_voltage_tables(rdev);
2405 ret = cypress_get_mvdd_configuration(rdev);
2413 ret = btc_initialize_mc_reg_table(rdev);
2418 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_BACKBIAS)
2419 rv770_enable_backbias(rdev, true);
2422 cypress_enable_spread_spectrum(rdev, true);
2425 rv770_enable_thermal_protection(rdev, true);
2427 rv770_setup_bsp(rdev);
2428 rv770_program_git(rdev);
2429 rv770_program_tp(rdev);
2430 rv770_program_tpp(rdev);
2431 rv770_program_sstp(rdev);
2432 rv770_program_engine_speed_parameters(rdev);
2433 cypress_enable_display_gap(rdev);
2434 rv770_program_vc(rdev);
2437 btc_enable_dynamic_pcie_gen2(rdev, true);
2439 ret = rv770_upload_firmware(rdev);
2444 ret = cypress_get_table_locations(rdev);
2449 ret = btc_init_smc_table(rdev, boot_ps);
2454 ret = cypress_populate_mc_reg_table(rdev, boot_ps);
2461 cypress_program_response_times(rdev);
2462 r7xx_start_smc(rdev);
2463 ret = cypress_notify_smc_display_change(rdev, false);
2468 cypress_enable_sclk_control(rdev, true);
2471 cypress_enable_mclk_control(rdev, true);
2473 cypress_start_dpm(rdev);
2476 btc_cg_clock_gating_enable(rdev, true);
2479 btc_mg_clock_gating_enable(rdev, true);
2482 btc_ls_clock_gating_enable(rdev, true);
2484 rv770_enable_auto_throttle_source(rdev, RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL, true);
2486 btc_init_stutter_mode(rdev);
2488 btc_update_current_ps(rdev, rdev->pm.dpm.boot_ps);
2493 void btc_dpm_disable(struct radeon_device *rdev)
2495 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
2496 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
2498 if (!btc_dpm_enabled(rdev))
2501 rv770_clear_vc(rdev);
2504 rv770_enable_thermal_protection(rdev, false);
2507 btc_enable_dynamic_pcie_gen2(rdev, false);
2509 if (rdev->irq.installed &&
2510 r600_is_internal_thermal_sensor(rdev->pm.int_thermal_type)) {
2511 rdev->irq.dpm_thermal = false;
2512 radeon_irq_set(rdev);
2516 btc_cg_clock_gating_enable(rdev, false);
2519 btc_mg_clock_gating_enable(rdev, false);
2522 btc_ls_clock_gating_enable(rdev, false);
2524 rv770_stop_dpm(rdev);
2525 btc_reset_to_default(rdev);
2526 btc_stop_smc(rdev);
2527 cypress_enable_spread_spectrum(rdev, false);
2529 btc_update_current_ps(rdev, rdev->pm.dpm.boot_ps);
2532 void btc_dpm_setup_asic(struct radeon_device *rdev)
2534 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
2537 r = ni_mc_load_microcode(rdev);
2540 rv770_get_memory_type(rdev);
2541 rv740_read_clock_registers(rdev);
2542 btc_read_arb_registers(rdev);
2543 rv770_read_voltage_smio_registers(rdev);
2546 cypress_advertise_gen2_capability(rdev);
2548 rv770_get_pcie_gen2_status(rdev);
2549 rv770_enable_acpi_pm(rdev);
2552 int btc_dpm_init(struct radeon_device *rdev)
2562 rdev->pm.dpm.priv = eg_pi;
2565 rv770_get_max_vddc(rdev);
2573 ret = r600_get_platform_caps(rdev);
2577 ret = rv7xx_parse_power_table(rdev);
2580 ret = r600_parse_extended_power_table(rdev);
2584 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries =
2588 if (!rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries) {
2589 r600_free_extended_power_table(rdev);
2592 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.count = 4;
2593 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[0].clk = 0;
2594 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[0].v = 0;
2595 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[1].clk = 36000;
2596 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[1].v = 800;
2597 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[2].clk = 54000;
2598 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[2].v = 800;
2599 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[3].clk = 72000;
2600 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[3].v = 800;
2602 if (rdev->pm.dpm.voltage_response_time == 0)
2603 rdev->pm.dpm.voltage_response_time = R600_VOLTAGERESPONSETIME_DFLT;
2604 if (rdev->pm.dpm.backbias_response_time == 0)
2605 rdev->pm.dpm.backbias_response_time = R600_BACKBIASRESPONSETIME_DFLT;
2607 ret = radeon_atom_get_clock_dividers(rdev, COMPUTE_ENGINE_PLL_PARAM,
2636 radeon_atom_is_voltage_gpio(rdev, SET_VOLTAGE_TYPE_ASIC_VDDC, 0);
2639 radeon_atom_is_voltage_gpio(rdev, SET_VOLTAGE_TYPE_ASIC_MVDDC, 0);
2642 radeon_atom_is_voltage_gpio(rdev, SET_VOLTAGE_TYPE_ASIC_VDDCI, 0);
2644 rv770_get_engine_memory_ss(rdev);
2661 if (rdev->pm.int_thermal_type != THERMAL_TYPE_NONE)
2668 if (rdev->flags & RADEON_IS_MOBILITY)
2682 radeon_acpi_is_pcie_performance_request_supported(rdev);
2687 if (rdev->family == CHIP_BARTS)
2693 if (ASIC_IS_LOMBOK(rdev))
2700 rdev->pm.dpm.dyn_state.mclk_sclk_ratio = 4;
2701 rdev->pm.dpm.dyn_state.vddc_vddci_delta = 200;
2702 rdev->pm.dpm.dyn_state.min_vddc_for_pcie_gen2 = 900;
2703 rdev->pm.dpm.dyn_state.valid_sclk_values.count = ARRAY_SIZE(btc_valid_sclk);
2704 rdev->pm.dpm.dyn_state.valid_sclk_values.values = btc_valid_sclk;
2705 rdev->pm.dpm.dyn_state.valid_mclk_values.count = 0;
2706 rdev->pm.dpm.dyn_state.valid_mclk_values.values = NULL;
2708 if (rdev->family == CHIP_TURKS)
2709 rdev->pm.dpm.dyn_state.sclk_mclk_delta = 15000;
2711 rdev->pm.dpm.dyn_state.sclk_mclk_delta = 10000;
2714 if ((rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc.sclk == 0) ||
2715 (rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc.mclk == 0))
2716 rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc =
2717 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac;
2722 void btc_dpm_fini(struct radeon_device *rdev)
2726 for (i = 0; i < rdev->pm.dpm.num_ps; i++) {
2727 kfree(rdev->pm.dpm.ps[i].ps_priv);
2729 kfree(rdev->pm.dpm.ps);
2730 kfree(rdev->pm.dpm.priv);
2731 kfree(rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries);
2732 r600_free_extended_power_table(rdev);
2735 void btc_dpm_debugfs_print_current_performance_level(struct radeon_device *rdev,
2738 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
2761 u32 btc_dpm_get_current_sclk(struct radeon_device *rdev)
2763 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
2784 u32 btc_dpm_get_current_mclk(struct radeon_device *rdev)
2786 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
2807 u32 btc_dpm_get_sclk(struct radeon_device *rdev, bool low)
2809 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
2818 u32 btc_dpm_get_mclk(struct radeon_device *rdev, bool low)
2820 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);